JPS62154291A - Dynamic ram - Google Patents

Abstract

PURPOSE:To shorten the holding time of a write enable signal and, at the same time, to reduce the power consumption, by separately providing a timer circuit which monitors the falling time of a chip selecting signal and another timer circuit which decides the period of automatic refreshing operations. CONSTITUTION:A timer circuit MT1 is constituted of a delay circuit DL1, NOR gates G11 and G12, and inverter circuits N11 and N12, monitors the falling time of a chip selecting signal CS supplied to the outside, and discriminates whether it is ordinary memory access or self-reflesh starting designation. Another timer circuit TM2 is actuated by the timer circuit TM2 and forms clock pulses phi2 to be used for advancing an address counter CONT one by one at the time of the self-refresh operation. What is designated by a circuit signal CONT is a refresh-address counter and internal complementary address signals a0'-am' for refreshing are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a dynamic RAM (Random Access Memory), and relates to a technique that is effective for use in, for example, a device with a built-in automatic refresh circuit.

[Background technology]

A dynamic memory cell consists of a storage capacitor that stores information in the form of charge and a MOSFET for address selection.
It is composed of In a memory cell formed on a semiconductor substrate, the charge accumulated in the capacitor decreases over time due to leakage current, etc. Therefore, in order to always store accurate information in the memory cell, it is necessary to It is necessary to read the information stored in a memory cell before it is lost, amplify it, and write it back into the same memory cell, a so-called refresh operation. For example, as an automatic refresh method for memory cells in 64-pinto dynamic RAM, "Electronic Technology 1 Magazine Vol. 123, No. 093
The automatic refresh circuit shown on pages 30 to 33 of . That is, by providing a dynamic RAM with an external terminal for refresh control and applying a refresh control signal REF of a predetermined level to this external terminal, a plurality of memory cells in the dynamic RAM are automatically refreshed. and a self-refresh function that operates a built-in timer circuit by keeping the refresh control signal REF at a predetermined level and performs the refresh operation at regular intervals.

The self-refresh cycle in such a conventional automatic refresh circuit performs a refresh operation on all memory cells at the same cycle, so the refresh cycle is relatively short, about 2 to 4 ms, taking into account the source case. is selected. Dynamic RA
In M.

Since the refresh operation is always performed at relatively short time intervals in this way, most of the power consumption is due to the refresh operation.

As a result of studying the information storage times 1 and 9 of memory cells, the inventors of the present application found that the information storage times in most memory cells are as long as about 400 to 10,100 O, and that a large number of semiconductor chips completed on a semiconductor wafer It has been found that only a limited number of memory cells of some chips in a dynamic RAM (dynamic RAM) require a refresh cycle of several + ns due to failure due to process defects or the like.

On the other hand, in order to make dynamic RAM compatible with static RAM, pseudo-static RAM has the same external terminal arrangement as static RAM.
In AM and the like, external address signals are input from separate external terminals for X address and Y address. For this reason, there is not enough external terminals and it is not possible to provide a separate external terminal for the refresh control signal.
A common method is adopted in which the deep selection signal C3 is kept at a low level for a predetermined period of time or longer and is regarded as a refresh start control signal.

In this case, a timer circuit is provided inside the RAM to monitor the fall time of the chip selection signal τ and determine whether it is a normal memory access or a refresh start fi indication, and this timer circuit is the basis of the refresh operation. It is also used as a timer circuit to determine the cycle.

Inside the RAM, a normal read operation is performed in the first cycle even during a refresh operation. 7 must continue to hold the write enable signal ~VE at high level to prevent erroneous writing.

As mentioned above, in order to reduce the power consumption of dynamic RAM, it is effective to set the timer circuit, which determines the refresh cycle, as long as possible, but from the perspective of the external main device, the write enable Signal W
There is a problem that the retention time of E and the like becomes long.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM that has a short control signal retention time during self-refresh operation and that consumes less power.

The above and other objects and novel features of this invention include:
This will become clear from the description in this book and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a timer circuit for monitoring the falling time of the chip selection signal supplied from an external terminal and a timer circuit for determining the period of automatic refresh operation are separately provided, and the period of the latter timer circuit is determined by the manufacturer. By making it possible to change the information storage retention time of the memory cells on each semiconductor chip, the retention time of the write enable signal WE etc. can be shortened and power consumption can be reduced.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a dynamic RAM having a configuration of about 32K×8 bits according to the present invention. In this embodiment, although not particularly limited, the memory array is arranged in two parts, M-ARY 1 and M-ARY 2, on the left and right sides. Each memory array M-A
In RYI M-ARY2, column system (data line)
The signal lines are made up of eight complementary data line pairs, and are arranged in the vertical direction in the figure. In other words, instead of configuring the memory array by dividing it into 8 blocks (mantles), 8-bit data is divided into 8 adjacent complementary data line pairs in the same memory array.
Addresses are allocated and arranged in order in the horizontal direction in the figure. Row-related address selection lines (word lines) are formed so as to extend horizontally in common to each of the memory arrays M-ARY 1 and M-ARY 2, and are arranged sequentially in the vertical direction in the figure.

The above complementary data line pair is connected to the column switch C-3WISC.
-8 pairs of common complementary data lines CDI, C via 3W2
In the 0-to-0 diagram selectively connected to D2, the common complementary data line pair runs in the horizontal direction. The common complementary data line pair CDI, CD2 is connected to the input terminals of main amplifiers MA1, MA2 each consisting of 81 amplifiers.

The sense amplifiers SAI and SA2 receive a minute read voltage on the complementary data line pair of the memory array, are activated by the timing signal φpa, and amplify the complementary data line pair to high/low level according to the read voltage. be.

The row address buffer R-ADB is
It receives the +l bit address signal RAD, forms internal complementary address signals aOxam, aO to afil, and sends them to the row decoder R-DCR.

In the following description and drawings, a pair of internal complementary address signals, for example aOlaO, will be referred to as internal complementary address signal 10. Therefore, the internal complementary address signal a Q w a m, ]F ~ -am-
is expressed as internal complementary address signal 10-1m.

Row decoder R-DCR selects one word line in synchronization with word line selection timing signal φX according to internal complementary address signal aQ-am.

The column address buffer C-ADB receives the address signal CAD of fi+l pin 1- from the external terminal, forms internal complementary address signals aQ-wan, aQ to aT, and supplies the column decoders C-DCRI, C-DCR2. Send to. In accordance with the representation of the internal complementary address signals, in the drawings and the following description, the internal complementary address signals aQ-an, 77 to ding-ding are referred to as internal complementary address signals!
Represented as 0 to an.

The above column decoders C-DCRI and C-DCR2 are:
They are provided corresponding to the divided memory array M-ARY11 and memory array M-ARY2, respectively. In order to connect the eight sets of complementary data line pairs to the corresponding common complementary data line pairs according to the internal complementary address signals 39 to an, the column decoders C-DCRI and C-DCR2 output the internal complementary address signals 0 to 39 to n is decoded to form a selection signal synchronized with the data line selection timing signal φy. Column switches C-5Wl and C-5W2 receive the selection signals formed by column decoders C-DCRi and C-DCR2, and select the eight sets of complementary data line pairs from the corresponding eight sets of common complementary data lines. Connect to pairs.

In the figure, the complementary data line pair and the common complementary data line pair are represented by -tree lines.

The input/output U path 110 is composed of a data output cover for reading and a data output cover for writing, and when reading, one of the main amplifiers MA! And the output of MA2 is amplified and sent to external terminals DO to D7. Further, during a write operation, write signals supplied from the external terminals D0 to D7 are transmitted to the common complementary data line pair CDI by a data line cover and a filter included in the input/output circuit I10, as will be described later.

It is supplied to CD2.

The internal control signal generation circuit TO generates two external control signals, a chip selection signal ττ) and a write enable signal W.
E, and the address signal change detection IFj number φ formed by the address signal 5thi pinching circuit ATD which receives the internal complementary address (B number 0 to am and the internal complementary address signal Oy a n). In response to this, various timing signals necessary for memory operation IY are formed and sent out.
The RAM is operated by internally formed timing No. 18, so from the outside of the IC, it is treated as a pseudo-static type RAM similar to a normal static type RAM.
It can be made to work.

The refresh control circuit REFC includes, but is not particularly limited to, timer circuits TMI and 7M2 as will be described later, and a counter circuit CON T' that forms internal complementary address signals aO' to am°, which are supplied from external terminals. It is activated by the chip selection signal CS.

FIG. 2 shows a circuit diagram of an embodiment of the refresh control circuit REFC. In the figure, the timer circuit TMI is a delay circuit DLL%NOR gate Gll, G1
2 and inverter circuits N11 and N12. The chip selection signal C3 supplied from the external terminal is delayed by a delay circuit, and this delayed signal D 12 E F
is supplied to one input of NOR gate Gll. Furthermore, the chip selection signal C3 is inverted by an inverter circuit Nil, and the inverted signal C8 is sent to another NOR gate.
It is supplied to one input of G12. The other inputs of the two NOR gates G11 and 012 and their respective outputs are cross-connected to form a lunch configuration. Thereby, the timer circuit TMI monitors the fall time of the externally supplied chip selection signal CS and determines whether it is a normal memory access or a self-refresh start instruction. For self-refresh operation, internal refresh control signal 'rRE
F activates the next timer circuit TM2.

The timer circuit TM2 is activated by the timer circuit TMI, and during the self-refresh operation, the address counter C
It forms the clock pulse φ2 for stepping 0NT, and is composed of the following circuit elements. That is, the input signal φ1 formed by the inverter circuit N25 is supplied to the date of the precharge MOSFET QIO1Qll. This pre-3-yarn M OS F
E 'l' Q 10 is a discharge I to be described later.
t OS F E T Q 14, Q! This is the precharge to gate 34 of 5. The above MOS
F E ”rQ i The bolt between O and the circuit ground potential is
Discharge%i Q S F E T'Q14,Q
M in the form of a diode forming the 01 operating voltage of i5
OS F E '1' Q 1''2. G13 is provided in series form. Also, the precharge M OS F
ETQII forms a precharge current for the capacitor C^. And Discharge M OS
FETQ14 and G15 are for flowing a discharge current of the capacitor C in accordance with the above-mentioned operating pressure.

In this embodiment, in order to make the timer 1 hour TF variable by making the discharge current variable, the operating voltage is selectively supplied to the gate of the one MOSFET QI 5 via the switch MO3FET QI 7. . That is, the above switch MO3FETQI
The gate of No. 7 is supplied with an output signal of an inverter circuit N27 which receives an output signal of a memory circuit consisting of a fuse means F made of a polysilicon layer and a high resistance R, although this is not particularly limited. Further, a MOSFET QI 6 controlled by the output of the memory circuit is provided between the gate of the MOSFET QI 5 and the ground potential of the circuit. The voltage VC of the capacitor C is subjected to a high level/low level discrimination operation by the inverter circuit N26 using the logic threshold voltage as a reference.

For example, if fuse means F is not blown, M
OSFET QI 6 is turned on because the power supply voltage VCC is supplied to its gate. This MOSFET G1
When MOSFET G15 is turned on, the ground potential of the circuit is supplied to its gate, so that MOSFET G15 is turned off. Further, the output signal of the inverter circuit N27 is set to a low level by a high level such as the power supply voltage VCC from the storage circuit. This allows the switch M OS F
ETQ17 is turned off. In such a state, the discharge current of the capacitor C is M
Since °ζ is formed only by O3FET QI 4, its discharge time is lengthened. In other words, the period TF of the oscillation operation as described later is lengthened. This time is, for example, 400 times around the refresh period required in a semiconductor chip (dynamic RAM) that does not have the above-mentioned floppy memory cells.
lengthened to match m5.

On the other hand, when the fuse means F is blown, MO3F
ETQI 6 is turned off because its gate is supplied with the circuit ground potential. The inverter circuit N
The output signal of 27 is set to high level. by this,
Switch MO5FETQ17 is turned on. In this state, the operating voltage is supplied to the gate of MO3FET QI5, so the discharge current of capacitor C is equal to MOSFET G14 and G.
15. As a result, the discharge time is short (for example, about 4), so that the refresh 1/tshu period is shortened (for example, about 4) in accordance with the refresh period of a memory cell that tends to decline. be done.

In addition, the above discharge MO3FET QI 4, G1
The conductance characteristics of 5 are precharged MO3FET
Since it is set sufficiently small compared to the conductance characteristic of QI 1, the precharge MO3FET QI
During the precharge period in which VCC 1 is on, capacitor C is precharged to approximately the level of Vcc-vth.

Such a timer circuit TM2 is activated by the internal refresh control signal TREF and starts a self-refresh operation.

The circuit symbol C0NT is a refresh address counter, which forms internal complementary address signals 10° to am' for refresh. Timer circuit TM
The output of I, the internal refresh control signal TREF, is inverted by the inverter circuit N12 and output to the NOR gate G2.
1. This NOR gate G21
The output signal φ3 of the timer circuit TM2 is supplied to the other input of the timer circuit TM2. The output signal φl of this NOR gate G
is supplied on the one hand as a starting signal for the timer circuit TM2 itself, and on the other hand is inverted and delayed by the cascaded inverter circuits N21 to N23 constituting a delay circuit. This inverted delay signal and the output signal φ1 are:
The pulse φ2 is inputted to the NAND gate 1-022, synchronized with the rise of the signal φ1, and has a pulse width of the time set by the delay circuit DL2. This pulse φ2 is input to the refresh address counter C0NT via the gate circuit G23, and is used for its refresh address increment operation. Here, the other input signal φCBR of gate circuit G23 is an input for single-stepping the refresh address counter during auto-refresh operation.

The operation of the refresh control circuit REFC of this embodiment will be explained according to the timing diagram of FIG.

When the chip selection signal CS supplied from the external terminal changes from high level to low level, the signal D RE F'' from the delay circuit DLI changes from high level to low level after a certain period of time TS. This certain period of time TS is as follows. R.A.
It is assumed that the time is set to be sufficiently longer than the time required for a single read operation of M, and sufficiently shorter than the clock cycle TF of the automatic refresh operation. The output Nl of the NOR gate G12 of the launch circuit maintains a low level because it is a refresh control bell. Chip selection +1
<1 ear number 5 interlude number L) RE: l- When it reaches the low level, the large refresh control signal REF is still at the low level even after this delay time TS, that is, its inverted signal C8 is at the low level. NO with the condition that it is at a high level
The output signal TREF of the R gate Gll is set to high level. This output signal TREF becomes low level when the chip selection signal C8 returns to high level. In addition, in the case of a normal single read operation in which the chip selection signal C8 becomes low level once and becomes high level within a predetermined time TS, the NOR gate G
12 input signal REF becomes low level, NOR
The output signal Nl of the gate G12 remains at high level, and the output signal TREF of the NOR gate Gll remains at low level. That is, unless the chip selection signal C8 continues to be at a low level for a predetermined time TS, the activation signal TREF to the next stage timer circuit TM2 is not output.

Next, in the timer circuit TM2, when the inverted signal TREF of the activation signal TREF by the inverter circuit N12 is at a high level, the output signal φ1 of the NOR gate G21 is at a low level. As a result, inverter circuit N25
As a result, the timer circuit input f8-'7Lφ1 is set to high level. Due to the high level of this input signal φ1,
Precharge MO5FETQIO1Qll are both turned on and 6*L/noj 7'j<j Te1. Totobashi 9c! Since v is fixed at a high level, the output signal (timer output signal) of the inverter 1st path N26 (timer output signal) is fixed at a low level (return state) ζ. .

Next, the internal reflex/I shim lock flllrl signal ゛1' R
When E li changes to low level, NOR gate G2
The output signal φ1 of 1 changes from low level to high level, thereby forming the input pulse φ2 of the refresh address counter C0NT as described above. Moreover, since the input signal φl of the timer circuit TM2 is set to low level, if the fuse hand iF is not blown, the MOSFET
ETQ, 14, if the fuse means F is set to % k'fr, the discharge operation of the capacitor C starts in MOSFET: TQI 4 and C15, and if the internal refresh control signal TRE remains at low level, this Due to the discharge operation of capacitor C, the voltage V
C is made below the rosin threshold of inverter circuit N26. In response, the output signal φ3 of the inverter circuit N26 changes from low level to high level. Therefore, the output signal φl of the NOR gate G21 is changed to low level again, so that the capacitor C of the timer circuit TM2 is put into a precharged state, in other words, put into a reset state. By the precharge operation, the output signal φ3 is restored to low level again. As a result, the output signal φ of the NOR gate G21
Since l is changed to low level, timer circuit TM2 is activated again. The above oscillation operation is performed while the internal refresh control signal TRE continues to be at a low level.

The refresh address counter C0NT performs its increment operation in response to the pulse signal φ2. Also, the above signal ψ
1 to the high level, the multiplexer MPX in FIG. 1 is switched to the refresh address counter C0NT side. Therefore, the internal complementary address signals aQ' to am' changed by the stepping operation of the refresh address counter C0NT.
Each time a word line selection operation is performed, a self-refresh operation is performed.

In this embodiment, the set time 'rF of the timer circuit TM2, that is, the repetition period of the automatic refresh 1/source operation, is made variable by the fuse means F, which is a programming element, so that In accordance with the information storage retention time of the memory hill determined by probing tests on the chip (Da.

〔effect〕

(To monitor the fall time of the nap selection signal supplied from the external terminal 11 and generate the timer l path for starting the self-refresh operation and the clock pulse for incrementing the refresh address counter. By providing an independent timer circuit, the fall time of the chip selection signal can be shortened, and the holding time of other external control signals (write enable signal WE, output enable signal OE, etc.) can be shortened. This has the effect of making it easier to control, increasing the increment period of the refresh address counter, and reducing the power consumption of the memory.

(2) By making the time settings of the timer circuits T to 12 variable, the self-refresh cycle can be set according to the performance (information storage retention time) of the memory cells in the dynamic RAM in which the timer circuits are installed. . This allows the self-refresh cycle of most dynamic RAMs manufactured to be longer, allowing standby
The effect is that the power required for erasure IG in the information retention state can be significantly reduced. By the way, about 25
In the case of a dynamic RAM with 6 bits, the current consumption is about 1 mA when the refresh cycle is 4 ms, whereas if the refresh cycle is set to 400 m5, the current consumption is about 10. It can be reduced to c+A.

(3) Since the self-refresh operation is used for storing information (for example, during standby operations where only Q operation is performed, for example when battery banking is increased), it is possible to extend the battery life by reducing the power consumption mentioned above, and also to This has the effect of simplifying control processing.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above examples, and it is possible to make various changes without departing from the gist of the invention. Not even. For example, the set time TS of the above-mentioned timer circuit TMI is not fixed, but can be changed depending on the conditions! The time of the timer circuit TM2 may be set to a time of 3fifi or more. Also, the program element used for setting the time is, for example, 1! Various embodiments can be adopted, such as applying laser annealing to silicon to change its resistance value, using a thin "full mini-lamb wire" as a fuse means, or using a MOS diode as a fuse. , the circuit that changes the timer hour according to the information stored in the storage circuit can be implemented in various embodiments.

Field of Application] The present invention can be widely applied to a dynamic RAM having a built-in automatic refresh circuit using the above-mentioned timer circuit.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing an embodiment of a dynamic RAM according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the refresh control 211 circuit in FIG. 1, and FIG. This is a 11-minute diagram showing its operation. MC...memory cell, DC...dummy cell, CW...
・・Column switch, SA・Sense amplifier, AR・
・Active restore circuit, R・C-D C1?・・・
・Row/column decoder, ADI3...address counter, DOB...data output cover sofa, DIB...
・Data human cover, fa, TC...timing m+j
11 circuits, M P X... multiplexer, REF'
C...Refresh', 1lli control circuit, 1°Ml,
T? v12-, timer circuit, DLl + D
L 2...Delay circuit, CON'1...Ref ref simat L・Scauyu・ri

Claims (1)

[Claims] 1. A first timer circuit that receives a substantial chip selection signal and detects a chip selection state for a relatively short period of time that is longer than a normal memory access time; and the first timer circuit described above. a second timer circuit that is activated by the output signal of the memory cell and forms a pulse signal with a relatively long period according to the information retention time of the memory cell; 1. A dynamic RAM comprising: an address counter circuit for forming an address signal; and an automatic refresh control circuit including an address counter circuit. 2. The dynamic RAM according to claim 1, wherein the second timer circuit has a variable period of output pulses by a program element. 3. The dynamic RAM according to claim 1 or 2, wherein the dynamic RAM is such that the row address and column address are supplied from independent external terminals.