JPH0525213B2 - - Google Patents

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to bus networks.

(Prior art and its problems) Networks in which multiple communication terminals are connected to a bus-like transmission path have advantages such as easy connection and removal of terminals and high reliability due to the passive connection between the terminals and the network. It has the following characteristics. However, it is not suitable for accommodating regular time-based communications such as voice communications, and various studies are currently underway. For example, there is a separate slot bus system described in Mori et al.'s ``An Idea of a Terminal Accommodation System Using Bus-Type Wiring'', Proceedings of the 1985 National Conference of the Institute of Electronics and Communication Engineers, No. 1859. In this method, the slave devices communicate based on synchronization signals from the master device, so communication between the master device and the slave devices can be performed synchronously, but communication between the slave devices is asynchronous. , slave devices need to be synchronized for each passing signal. Therefore, a signal detection circuit is required, leading to an increase in the price and scale of the slave device.

(Object of the Invention) An object of the present invention is to provide a synchronous bus network in which communication between slave devices can also be performed synchronously.

(Structure of the Invention) According to the present invention, a main device, a plurality of slave devices,
A first transmission path that commonly connects the transmitter of the main device and the receivers of the plurality of slave devices, and a first transmission path that commonly connects the receiver of the main device and the transmitter of the plurality of slave devices. A bus network consisting of a second transmission path, wherein the main device sends a synchronization signal indicating the start of a cycle to the first transmission path at every fixed period consisting of a plurality of time slots, and also sends a synchronization signal to the first transmission path. a transmitter that sends out a signal; a receiver that receives the signal supplied from the second transmission path; and a transmitter that delays the received signal to a predetermined time according to the received time slot number. and a delay circuit that supplies a delay circuit to the first transmission line, the slave device is supplied with a received signal from the first transmission path, detects a synchronization signal from the received signal, and is determined based on the detected synchronization signal. The device is characterized in that it is configured to include a receiving section that receives the received signal at a time, and a transmitting section that sends the transmitted signal to the second transmission path at a time slot determined based on the synchronization signal. A synchronous bus network is obtained.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of the present invention, and the first
The distributed control bus network in the figure includes a main device 3, slave devices 4, 5, 6, a transmission line 1 for communication from the main device 3 to these slave devices, and a transmission line 1 for communication from the slave device to the main device 3. It consists of a transmission line 2 and termination circuits 7 and 8 for the transmission lines 1 and 2.

FIG. 2 shows the configuration of the main device 3 used in the first embodiment of the present invention, and FIG. 3 shows the configuration of the transmission line interface of the slave device.

The main device 3 in FIG. 2 has an output terminal 11 and an input terminal 12 connected to the transmission lines 1 and 2, respectively, and a transmission control circuit 17 controls the selector 15 at a constant period T ₀ and further controls the control output 17. -1 activates the synchronization signal generation circuit 16 and supplies the synchronization signal F to the driver 13. A signal block from the slave device is input from the receiver 14 and supplied to the signal detection circuit 20. When the signal detection circuit 20 detects a signal block, it stores it in the register 19. register 1
The signal 9 is transferred to the register 18 at the time position of the determined time slot, and is sent to the driver 13 via the selector 15 under the control of the transmission control circuit 17.
The signal is output to transmission line 1. Therefore, output terminal 1
Continuing with the periodic signal F that gives a constant period to the transmission line 1 from 1 to the transmission line 1, the transmission line 2
A return signal of the signal block received from the slave device is sent out.

In the slave device shown in FIG. 3, the input terminal 43 is connected to the transmission line 1, and the output terminal 44 is connected to the transmission line 2. The signal from the main device 3 is supplied to a synchronization signal detection circuit 28 and a reception buffer 25 via a receiver 24.
When the synchronization signal detection circuit 28 detects the synchronization signal F, it initializes the timing control circuit 29. The timing control circuit 29 specifies a transmission time slot based on the control data from the transmission control circuit 27, that is, the time slot number information, starts the transmission buffer 26 and the driver 23 in that time slot, and transmits the signal block to be transmitted. Send to transmission path 2.

The operation of this embodiment will be described with reference to FIG. 4 in the case where time slots are fixedly assigned to each terminal. Figure 4 a-1 and a-2 show signals at the output terminal 11 and input terminal 12 of the main device 3, and figures b-1 and b-2 show the signals at the input terminal 4 of the slave device 4.
3. The signal at the output terminal 44 is further changed to c- in the same figure.
1, c-2 and d-1, d-2 are slave devices 5 and 6
The signals at the input terminal 43 and output terminal 44 are shown.

As shown in Figure 4 a-1, the main device 3
At T ₀ , synchronization signal F is output to transmission line 1. This synchronization signal F arrives at the slave devices 4, 5, and 6 after a propagation delay, as shown in b-1, c-1, and d-1 in the figure.
Based on this synchronization signal F, each slave device performs transmission control using time slots. Now slave device 4,
5 and 6 respectively, the first time slot τ ₁ and the second time slot τ 1
Assume that a third time slot τ ₂ and a third time slot τ ₃ are assigned as transmission time slots. Note that to simplify the explanation, the time widths of all time slots are assumed to be the same length as T.

In the slave device 4 shown in FIG. 3, the timing control circuit 29 starts the driver 23 based on the instruction to allocate the first time slot τ ₁ from the transmission control circuit 27, and transfers the signal block A in the transmission buffer to the transmission line 2. Output to. The transmission time position of this signal block A is shown in FIG. 4b-2. This signal block A propagates through the transmission line 2 and is received by the main device at the time position shown at a-2 in the figure. This signal block A also arrives at the slave devices 5 and 6 as shown in c-2 and d-2 of the same figure, but the input terminals of these slave devices are not connected to the transmission line 2, so it cannot be received. do not have.
Signal block A shown in FIG. 2 is detected by the signal detection circuit 20 of the main device 3 in FIG. At the second time slot τ ₂ , the transmission control circuit 17 activates the register 18 by the control output 17-1, stores the signal block A in the register 19, and outputs it to the selector 15 at the same time. The selector 15 sends the folded signal block A from the register 18 to the transmission line 1 via the driver 13 under the control of the transmission control circuit 17. Therefore, as shown in FIG. 4a-1, signal block A is supplied to transmission line 1 at the start of time slot _τ2 . In this time slot τ ₂ , the signal block A is supplied to the transmission line 1, and the signal block B from the slave device 5 is supplied to the transmission line 2 as shown in FIG. 4b-2. This signal block B is turned back at the main device 3 and output to the transmission line ₁ at the third time slot τ3. The signal block C sent out in the last time slot of the period _T0 is stored in the register 19 of the main unit 3 in FIG. 2 like the signal blocks A and B, but since the next period _T0 is started, 15
selects the synchronizing signal generation circuit 16 and first sends out the synchronizing signal F. When this transmission is completed, the selector 15 selects the register 18 and at the same time register 19.
The signal block C within is transferred to register 18. Therefore, the signal block C is sent to the transmission line 1 following the synchronizing signal F of the next period _T0 .
FIG. 4a-1 shows a situation in which the signal block C' sent out by the slave device 6 in the previous cycle is sent out following the synchronizing signal F. As described above, the folded signal blocks are sent out at regular intervals to the transmission path 1 from the main device 3 to each slave device.

In this embodiment, the signal block from each slave device must arrive at the main device 3 within the time width of the given time slot, so the length of the time slot is equal to the length of the signal block. ,
It is assumed that it is set longer than the sum of the maximum round-trip propagation delay times of transmission lines 1 and 2.

In FIG. 3, each slave device activates the reception buffer 25 based on the synchronization signal F detected by the synchronization signal detection circuit 28 and receives the signal block on the transmission line 1. At this time, since the signal blocks arrive at regular intervals in synchronization with the synchronization signal F, there is no need to detect the arrival time position of each signal block, and reception control becomes simple.

Next, a case where time slots are not fixedly assigned to each slave device will be explained. Figure 5
At the time of a certain period as shown in a'-1, transmission line 1
Assume that the second time slot τ ₂ above is empty (indicated by a dashed line). In the conventional apparatus shown in FIG. 3, this detection of empty time slots can be carried out by the transmission control circuit 27 reading out the area corresponding to each time slot in the receiving buffer 25 and determining the presence or absence of a signal block. In this example, there is no signal block in the area corresponding to the second time slot. Now, suppose that a transmission request is made to slave devices 4 and 5. When both slave devices detect that the second time slot is vacant on transmission path 1, they will select the second time slot on transmission path 1 in the next cycle. A signal block is transmitted at the time slot on the transmission line 2 corresponding to the slot, that is, at the first time slot _τ1 . In addition, Figure 5 a-1 to c-2 are the same figure.
The signal of the period following the period indicated by a'-1 is shown. When the slave devices 4 and 5 receive the synchronization signal F at the time positions shown in FIG. The signal blocks A and B are sent out.

This transmission control will be explained using FIG. When the transmission control circuit 27 detects that the second time slot of the transmission path 1 is vacant, it notifies the timing control circuit 29 that transmission will be performed in the previous time slot, that is, the first time slot. Based on this notification, the timing control circuit 29 starts up the transmission buffer 26 and the driver 23 in the first time slot, and sends out the signal block in the transmission buffer 26 to the transmission line 2.

The signal blocks A and B sent to the transmission line 2 are partially overlapped and sent to the main device 3 as shown in Figure 5 a-2.
will be received. Note that the overlapping portions are indicated by diagonal lines. In the main device 3 of FIG. 2, the signal detection circuit 20 stores the received signal block in the register 19 by detecting the signal block A that arrived first. However, part of this signal block is destroyed by collision with signal block B. This destroyed signal block is turned back at the next time slot τ ₂ and sent out to the transmission line 1 in the same manner as the normally received signal block.

In FIG. 3, the transmission control circuit 27 of the slave devices 4 and 5 reads out the area of the reception buffer 25 corresponding to the time slot next to the transmitted time slot and determines whether or not it matches the transmitted signal block. In this case, the received signal block has been corrupted by a collision and does not match the transmitted signal block. Therefore, slave devices 4 and 5 recognize the time slot acquisition conflict and retry. As a method for this retry, a known method such as waiting for a random time and then retrying can be used. If the received signal block and the transmitted signal block match, it is recognized that there is no conflict in capturing the time slot, and that time slot can be captured. Once you have acquired the right to use a time slot, you will not compete with other slave devices as long as you always transmit in that time slot. In this example, the case where the second time slot τ ₁ of the transmission line 1 is vacant has been explained, but if the first time slot τ ₁ is vacant, the last time slot τ in the same period At _{step 3} , transmission is performed to capture the time slot. In this way, the present invention can be applied to networks in which time slots are not fixedly allocated, and even in this case, it is not necessary for each slave device to detect the reception time position for each received signal block. do not have.

In the present invention, the lengths of the time slots within the period T ₀ do not necessarily have to be all the same.

That is, time slots of several lengths may be used. Further, the main device 3 may loop back signal blocks of several time slots at once instead of every time slot.

Next, a second embodiment will be described. In this embodiment, there are time slots of two different lengths within the period _T0 , and the main device 3 loops back signal blocks for one period all at once.

6a and b show signals on the output terminal 11 of the main device 3, that is, the transmission line 1, and the input terminal 12, that is, the signal on the transmission line 2.
The signal above is shown. The period T ₀ on the transmission line 1 consists of short time slots τ ₁ ′, τ ₂ ′, τ ₃ ′, τ ₄ ′,
It consists of time slots τ ₅ ′ and τ ₆ ′ with long time widths.
On the other hand, the period T ₀ on the transmission line 2 corresponds to the time slots τ ₁ , τ ₂ , τ ₃ , τ ₄ corresponding to the aforementioned time slots τ 1 ′, τ 2 ′, τ 3 ′, τ 4 ′, and the aforementioned time slots τ _{1 ′} , τ _{2 ′} , τ ₃ ′, τ _{4 ′} . τ ₅ ′,
It is composed of time slots τ ₅ and τ ₆ corresponding to τ ₆ ′. Note that this configuration is set in advance.
As in the first embodiment, the time slots τ ₁ , τ ₂ , τ ₃ , τ ₄ , τ ₅ , τ ₆ are given by the time width equal to or longer than the signal block length plus the round-trip propagation delay time. Lot τ ₁ ′, τ ₂ ′, τ ₃ ′, τ ₄ ′, τ ₅ ′, τ ₆ ′
is given with the same length as the signal block. As shown in FIG. 6b, short signal blocks S ₁ , S ₂ , S ₃ , S ₄ and time slots τ ₅ , τ received in time slots τ ₁ , τ ₂ , τ ₃ , τ ₄ The long signal blocks S _{5 and} S ₆ received by the main unit 3 at step 6 are continuously sent out from the main unit 3 in the next cycle in one cycle as shown in a in FIG.

FIG. 7 shows the configuration of the main device 3 used in this embodiment. The main device 3 in FIG. 7 has an expansion circuit 22 added to the main device 3 in FIG. It has a register 21 for storing. The register 19 once stores the received signal block based on the detection result of the signal detection circuit 20, and then supplies it to the register 21 via the expansion circuit 22. The transmission control circuit 17 controls the expansion circuit 22 in response to the time slots τ ₁ , τ ₂ , τ ₃ , τ ₄ and τ ₅ , τ ₆ on the transmission path 2, and stores them in predetermined positions of the register 21. let For example, at time slot τ ₁ , the output of register 19 is transmitted to register 21 via expansion circuit 22.
It is connected to the next area of the synchronization signal area, and further connected to the next area at time slot τ ₂ ,
The last time slot τ ₆ is connected to the last area of register 21. The area of the register 21 corresponding to each time slot is made equal to the signal block length at each time slot.

At the start of the next cycle, the synchronization signal F is output from the synchronization signal generation circuit 16 to the synchronization signal area.
is stored, and the register 21 serially supplies the synchronizing signal F and each signal block to the transmission line 1 via the driver 13 by a shift operation. The signal on the transmission line 1 at this time is shown in FIG. 6a.

Control in the slave device used in this embodiment will be explained using FIG. 3.

The reception buffer 25 continuously receives signal blocks based on the synchronization signal F detected by the synchronization signal detection circuit 28. On the other hand, the transmission control circuit 28 and the timing control circuit 29 store the time slot configuration on the transmission line 2, and the timing control circuit 2
When a transmission time slot number is designated by the transmission control circuit 27, the transmission control circuit 9 performs transmission using a predetermined time slot only for a time width corresponding to the transmission time slot number. In this case, whether the time slot is fixed or the time slot is not fixed, communication can be performed by the same control as in the first embodiment.

In addition, when there are time slots of various lengths as in this example, it is possible to transmit to a certain slave device using only one of the time slots, or to use multiple types of time slots. It is also possible to enable the transmission.
In the latter case, the transmission control circuit 27 notifies the timing control circuit 29 of the time slot number depending on the length of the signal block in the transmission buffer 26.

By providing time slots with multiple lengths in this way, you can select a time slot depending on the length of the signal block to be transmitted, or if the length of the signal block of the slave device is known in advance, It is possible to allocate transmission time slots to slave devices according to their lengths, allowing efficient use of the transmission path.

In this embodiment, as shown in FIG. 6a, by continuously transmitting the folded signal blocks for one cycle, the transmission line 1 becomes idle only at the rear end of the cycle _T0 . Therefore, this idle time can also be used for optional communication, for example, communication from the main device 3 to each slave device, or communication from an external network to the slave devices. Signals on transmission lines 1 and 2 in such a case are shown in FIGS. 8a and 8b. In this example, from the slave device to the main device 3
Since the communication to and from is the same, FIG. 6b and FIG. 6b are the same. The main device 3 adds signal blocks X and Y using optional slots to the signal block to be looped back and sends it to the transmission line 1. FIG. 9 shows the configuration of the main device 3 when an optional time slot is added. This configuration is obtained by adding registers 41 and 42 for optional communication to the configuration shown in FIG. The register 41 receives a signal block (signal block
is supplied with a signal block (signal block Y in FIG. 8a) which is sent out in a time slot with a long time width, and is stored in the register 21 and sent out to the transmission line 1 at the start of the period _T0 . In a network where time slots are not fixedly assigned, each slave device performs acquisition control only on time slots other than the time slot for optional communication.

The present invention has been explained above using an example in which the transmission path from the main device to the slave device and the transmission path in the opposite direction are physically separate lines. can also be applied.

FIG. 10 shows a third embodiment. In the bus network shown in FIG.
It is terminated by FIG. 11 shows signals on the transmission line 31 when the transmission line 31 is used for bidirectional communication by time division. The transmission line ₃₁ is connected from the main device ₃ to the slave devices 4, 5, and
6, and during the remaining time T ₀ is used for transmission in the reverse direction. The time T ₀ is the time slot τ ₁ ,
The signal block from the slave device that is divided into τ ₂ , τ ₃ , τ ₄ , τ ₅ , and τ ₆ and sent out in a certain period is stored once in the main device 3, and is sent during the time T ₁ of the next period. is concatenated with and sent.

FIGS. 12 and 13 show the configurations of the main device 3 and slave devices used in this embodiment. The main device 3 in FIG. 12 is connected to a transmission line 31 through a terminal 31. The main device 3 shown in FIG. This configuration is the same as the main device shown in FIG. 7, except that the driver 32 and receiver 33 are subject to operation switching control depending on time. The transmission control circuit 17 has a period T ₀
At the start of the control output 17-3, the driver 3
2 is brought into operation, and the signal block stored in the register 21 is sent to the transmission path 31 in the same manner as the main device shown in FIG. This transmission control is carried out until all the signal blocks in the register 21 are transmitted, that is, for a time _T1 , during which time the receiver 33 is in an inhibited state. Once the time T ₁ has elapsed,
The driver 32 is in a prohibited state, the receiver 33 is in an active state, and reception control is started. The signal block received within each time slot within time _T2 is
The data is stored in the register 21 in preparation for transmission control in the next cycle. The slave device shown in FIG. 13 is connected to the transmission line 31 via a terminal 34. This configuration is the same as the slave device of FIG. 3, except that receiver 35 is active only during time _T1 . In this embodiment, the timing control circuit 29 uses the synchronization signal F
After time _T1 has elapsed since the reception of , control for providing a transmission time slot is started.

Next, the length of the time slot in transmission from the slave device to the main device will be briefly described. As mentioned above, the time width of the time slot should be greater than or equal to the sum of the length of the signal block and the round-trip propagation time of the transmission path, but as shown in FIG.
This is not the case if the signals are unevenly distributed on the bus-like transmission path 36. In other words, the transmission path length (L ₁ +L ₂ )
If a slave device of length L ₁ is connected to
It is sufficient that the length is greater than the sum of the signal block length and the propagation time of the distance _2L1 , and there is no need to make it greater than the sum of the signal block length and the round trip time length of the total transmission path length.

(Effects of the Invention) As described above, according to the present invention, the slave device can perform transmission and reception in synchronization with the synchronization signal, thereby simplifying the configuration of the transmission line interface circuit. Furthermore, by providing multiple types of time slots with different lengths, it is possible to use time slots according to the transmission signal block length.
Transmission lines can be used efficiently. Furthermore, by collectively looping back signal blocks for multiple time slots in the main device, it is possible to add signal blocks other than the looped signal blocks to the transmission path from the main device to the slave device, increasing communication capacity. be able to. Furthermore, communication can be performed using a pair of buses, and installation conditions can be relaxed.

[Brief explanation of the drawing]

FIGS. 1, 10, and 14 are diagrams showing the configuration of the network in the present invention, and FIGS.
9 and 12 are diagrams showing the configuration of the main device used in the present invention, FIGS. 3 and 13 are diagrams showing the configuration of the slave device used in the present invention, FIG. 4, FIG.
FIG. 6, FIG. 8, and FIG. 11 are diagrams showing signals on the transmission path. In the figure, 1, 2, 31, 36 are transmission lines, 3
4, 5 and 6 are slave devices, and 7, 8 and 30 are terminal circuits. Figure 2, Figure 3, Figure 7, Figure 9
In Figures 12 and 13, 13, 2
3 and 32 are drivers; 14, 24, 33 and 35 are receivers; 15 is a selector; 17 and 27 are transmission control circuits; 16 is a synchronization signal generation circuit; 18, 19,
21, 41, and 42 are registers, 20 is a signal detection circuit, 28 is a synchronization signal detection circuit, 29 is a timing control circuit, 25, 26 is a buffer, and 22 is an expansion circuit.

Claims (1)

[Claims] 1 A first transmission path that commonly connects a main device, a plurality of slave devices, a transmitting section of the main device, and a receiving section of the plurality of slave devices; A second terminal that is commonly connected to the transmitting section of the slave device.
In the bus network, the main device sends out a synchronization signal indicating the start of a cycle to the first transmission path at regular intervals consisting of a plurality of time slots, and also sends a transmission signal to the first transmission path. a transmitter that transmits the signal; a receiver that receives the signal supplied from the second transmission path; and a receiver that delays the received signal until a predetermined time according to the received time slot number and supplies the signal to the transmitter. The slave device is supplied with a received signal from the first transmission path, detects a synchronization signal from the received signal, and performs a synchronization signal at a predetermined time based on the detected synchronization signal. A synchronization device characterized in that it is configured to include a receiving section that receives the received signal, and a transmitting section that sends out the transmission signal to the second transmission path in a time slot determined based on the synchronization signal. expression bus network.