JPH05252055A - Coder and decoder - Google Patents

Abstract

PURPOSE:To easily recognize disregard bit number information at the time of decoding by applying time division multiplex to first disregard bit number information of a C1 block of an error correction code C1 parity in Cm-byte. CONSTITUTION:Input data are subjected to variable length coding and the result is stored in a memory 3 and a code length of variable length codes is detected and the results are accumulated by an accumulator 4 and inputted to a MIN 5 which outputs a constant C when an accumulated value is larger than (C=mX8-5) bits or the received input that is smaller at all times. An output of a subtractor 6 is (mX8-5-C), data are subject to time division multiplex for a first 5-bit period in a succeeding parity C1 block through the selection of a switch 7 to attain prescribed data arrangement. While the switch 7 is used to select disregard bit number data, the memory 3 is controlled to avoid reading, and the accumulator 4 implements a prescribed operation when a succeeding parity C1 block is transited. A value (mX8-5-C) is selected for a desired value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding / decoding device for performing variable length coding and attaching error correction codes to fixed length data for transmission.

[0002]

2. Description of the Related Art FIG. 17 shows a code structure for error correction called double Reed-Solomon, which is very often used in recent years. First, an error correction code of C _n × m bytes is attached to the data of m bytes × n bits in the vertical direction,
Further, an error correction code of C _m × (n + C _n ) bytes is added in the horizontal direction so that double error correction can be performed and transmission is performed.

FIG. 18 shows an example of specific transmission. The simplest transmission method is to repeat (n + C _n ) × 8 times with the code of m + C _m bytes in FIG. 18 as a unit (1 byte is 8 bits). Here, the error correction code of C _m bytes is called C1 parity, and the error correction code of C _n rows is called C2 parity. Further, since a normal digital transmission system normally transmits data in 1-bit units, sync data for synchronization in order to convert data in byte units (hereinafter referred to as S
YNC) and the identity data representing the number of the uppermost row in FIG. 17 (which position in the vertical direction) and their parity data (hereinafter collectively referred to as ID data) are m + C. _It is added to _m bytes and transmitted. Further, as shown in FIG. 18, before the entire (n + C _n ) × 8 cycles, a synchronization area, which may be called a preamble, may be added and transmitted in order to improve the pull-in of the decoding system PLL.

In recent years, there is a helical scan type recorder for recording a large amount of data (especially video data) on a magnetic tape for business use or consumer use. FIG. 19 shows an example of the tape pattern. As shown in FIG. 19, a track pattern oblique to the tape running direction is generated.
This direction is a very effective method because the areal recording density can be relatively easily improved as compared with recording parallel to the running direction of the tape. However, as can be seen from FIG. 19, it is difficult to realize temporal continuity between tracks in a microscopic sense. For example, in a VTR for consumer use,
The joint between the tracks is applied to a portion of the video signal, which is called a vertical blanking period, which is less affected by damage. In other words, such 2
In such a VTR application, double error correction is usually performed with a block size of an error correction code which is closed in one track and does not cross tracks.

A variable length coding is one of the means for efficiently converting highly redundant data. This will be described with reference to FIG. AF shown in FIG. 20
Is called a symbol and represents the state of data to be compressed. When the run length coding is combined, the 0 run length becomes a symbol, and in the case of a multi-gradation video signal, the value itself becomes a symbol. In the high efficiency coding of the video signal, orthogonal transformation and run The length coding and the value itself may be combined into a symbol.
A code is assigned to each symbol according to its frequency of occurrence. FIG. 20 shows an example in which the frequency of occurrence is low from A to F. The code length of A is 1 bit, whereas the code length of F is 5 bits, and a code with a shorter code length is assigned as the frequency of occurrence increases. In this way, the total code amount is shortened and the coding can be performed efficiently. The variable length coding that is often used is the Huffman code. FIG. 21 shows a block diagram in which variable-length coded data coded in this way is given an error correction code.

In FIG. 21, reference numeral 31 is a code conversion circuit for performing variable length coding, 32 is a buffer memory for storing the capacity of m × n bytes shown in FIG. 17, and 33 is error correction with an error correction code of C1 parity C2 parity. It is an encoder. As an operation, for example, a code table as shown in FIG. 20 is used to perform code conversion by a ROM or the like, and the data after code conversion is stored in a buffer memory 32 having a capacity of one error correction code unit for output to an error correction encoder. Is stored, and an error correction code is added to the output by the error correction encoder 33 and the code is sent to the transmission line.

[0007]

Since the conventional encoder is constructed as described above, there are the following problems when the helical scan type tape recorder is used as the transmission medium. FIG. 23 shows a locus of a head trace in a trick play state such as fast-forwarding of a helical scan type tape recorder. In FIG. 23, the symbols L and R represent the directions of azimuth recording for the purpose of eliminating crosstalk components of adjacent tracks in a normal helical scan type tape recorder, and L azimuth represents R azimuth and the track longitudinal direction. It is symmetrical about the orthogonal axes. A track of L azimuth cannot be reproduced by a head of R azimuth, and a track of R azimuth cannot be reproduced by a head of L azimuth. FIG. 23 shows a head trace locus on the tape pattern when the tape feeding speed is increased to eight times that of the normal running for high-speed reproduction. If the azimuth of the head is L azimuth, the R azimuth track cannot be reproduced, and therefore the head reproduction output can be obtained only in the shaded area in FIG. This output is shown in FIG. As shown in FIG. 22, at the time of high-speed reproduction, the output that can be satisfied is limited to a certain fixed period, and even if one or more C1 blocks are not included in the period, error correction in the C1 direction is performed. It is not possible, and normally one or more C1 blocks are included. In the case of such trick play, although the code is a double product code, only error correction in one direction can be performed, and decoding during trick play is usually performed with C1 as one unit. At this time, for example, the data shown in FIG. 24 is recorded,
Assuming that the part before the dotted line is at the time of reverse azimuth tracing and cannot be decoded and the part after the dotted line is decoded, when decoding is performed using the code table of FIG. There is a problem that is converted into a symbol of D and is decoded. For example, when encoding a video signal, as shown in FIG. 25, a transform to a frequency domain called Discrete Cosine Transform (DCT) is performed, and run length coding is performed as indicated by an arrow to change the variable length. Encode. In the case of such encoding, the problem of garbled symbols is garbled data in different frequency regions, resulting in a completely different image. In addition, sub-band coding, which is often used for high-efficiency coding of audio signals, is shown in FIG.
The signal shown in FIG. 6 is passed through a sub-band filter to be frequency-divided, and is band-divided and encoded as shown in the lower diagram of FIG. The problem of high efficiency coding and blocking of error correction is a serious problem in a tape medium transmission system, especially in trick play.

The present invention has been made to solve the above problems, and an encoding device and a decoding device capable of eliminating errors during decoding in an intermittent data transmission system such as trick play. The purpose is to provide a device.

[0009]

An encoding apparatus according to the first invention of the present application counts the code amount at the time of variable length coding, and C
The first ignored bit number of one block is calculated, the information is time-division multiplexed, and an error correction code is added. Alternatively, the number of codes is counted during variable-length coding, the first ignored bit number of the C1 block is calculated, an error correction code is added, and the information is time-division multiplexed.

The decoding device according to the second invention of the present application is based on the ignore bit number information which is time-axis multiplexed at the time of encoding.
A mode is provided in which the first few bits of the error-correction-decoded data in one direction are not sent to the variable length decoder, but the rest are sent to the variable length decoder.

The encoding apparatus according to the third invention of the present application is C1.
When performing variable length coding so as to straddle blocks, special data not existing in the variable length code table is inserted into all the rest of the C1 block.

The encoding device according to the fourth invention of the present application is C1.
When variable-length coding is performed so as to straddle blocks, the variable-length coded data that has been straddled inserts a code again from the beginning of the next C1 block.

The decoding device according to the fifth invention of the present application is C1.
The last data of the block and the variable length decoding of which is not established are discarded.

The encoding device according to the sixth aspect of the present invention is such that, at a preset position in the variable-length encoded data, certain specific information (for example, high-efficiency encoded data of a certain frame out of several tens of frames , Data with increased compression ratio of each frame).

The decoding device according to the seventh aspect of the present invention has a mode for decoding only certain information having a preset position after error correction decoding.

In the decoding device according to the eighth invention of the present application, when the subsequent data is unusable and the block delimiter data is not variable length decoded, 0 is added to other data in the block. It is configured to insert and perform inverse orthogonal transform.

The decoding device according to the ninth invention of the present application is configured to discard the data of the block when the subsequent data is unusable and the block delimiter data is not variable length decoded. ..

[0018]

According to the first invention of the present application, the ignored bit number information is calculated, and the information is time-division multiplexed, so that it can be used at the time of decoding.

According to the second invention of the present application, variable length decoding is performed by ignoring the leading several bits of the data error-corrected in the C1 direction based on the ignored bit number information.

In the third invention of the present application, dummy data which does not normally exist is assigned to the variable-length code table, and the dummy data is inserted when straddling the C1 block, so that the data is not decoded in the decoding system. Is encoded in.

In the fourth invention of the present application, when the C1 block is straddled, the beginning of the next C1 block is the beginning of new variable-length code data.

In the fifth invention of the present application, variable-length decoding is performed on the last data in the C1 block during normal decoding of the coded data that has been coded as in the third and fourth inventions. The data that does not hold is discarded and acts so as not to be decrypted.

In the sixth invention of the present application, since certain information is time-axis-multiplexed at a preset position during variable-length coding, it is important at a predetermined position to be traced in trick play or the like. Data can be placed.

In the seventh invention of the present application, a mode capable of decoding only a limited position after error correction decoding is provided, and it operates so as not to output a decoding error when used for trick play or the like.

In the eighth invention of the present application, when the end code of the block cannot be reached even though the subsequent data is in the unusable state, the remaining block data is set to 0.
Is inserted and decrypted, it acts to prevent erroneous insertion of erroneous data and abnormal decoding.

In the ninth invention of the present application, if the end code of the block cannot be reached even though the subsequent data falls into the unusable state, the data of the block is discarded, so that the erroneous data is incorrect. It acts so that it is not decrypted.

[0027]

EXAMPLES Examples of the first to seventh inventions of the present application will be described below.

First, the first invention of the present application will be described with reference to the drawings. In FIG. 1, 1 is a code converter, 2 is a code length detector, 3 is a buffer memory, 4 is a cumulative adder, 5 is a minimum value circuit (hereinafter referred to as MIN), 6 is a subtractor, 7 is a switch, and 8 is It is an error correction encoder.

Next, the operation will be described. The input data is variable-length coded by the code converter 1 that performs code conversion according to a coding table designed such that the code length becomes shorter as the occurrence frequency becomes higher, such as Huffman code, and is stored in the buffer memory 3. At the same time, the code length of the variable length coding generated by the code length detector 2 is detected, the code length is cumulatively added by the cumulative adder 4, and a constant C and a MIN 5 that always outputs the smaller one are passed. ..
A certain constant is, for example, m which is an addition unit of C1 parity.
Bytes, that is, m × 8 bits, the number of bits of data created by the ignore bit number data creation circuit (usually about 5 bits because the code length per symbol in variable length coding is usually less than 30 bits) You can create the number of ignored bits data if there is) is given. C = m × 8−5 When the value of the cumulative adder 4 is larger than C, the output of MIN5 selects C. Since the output of the subtractor 6 is m × 8−5−C, the next C1
It is equal to the number of data bits that overflowed the block. This value is selected by the switch 7 for the first 5 bits of the next C1 block and time-division-multiplexed to form the data shown in FIG. At this time, it is controlled so that the buffer memory 3 is not read while the data for the number of ignored bits is selected by the switch 7. Then, when moving to the next C1 block, the cumulative adder 4 performs the intended operation. The expected value is m × 8-5
The value of C may be used.

Therefore, the circuit for creating the neglected bit data does not need to be limited to that shown in FIG. 1, and it is needless to say that, for example, an operation of dividing the cumulative addition result by C to obtain the remainder is possible. Absent. Further, as the ignored bit number data, the bit number of the code arranged in the previous C1 block may be obtained.

The same applies to the arrangement of the memory and the presence / absence of the switch 7. If only the above-mentioned operation is performed, if the buffer memory 3 has m bytes, the minimum operation is possible, and the data storage function for adding an error correction code to m × n bytes of data has an error correction encoder. 8, but the same thing can be realized by providing an area for storing the neglected bit data output from the subtractor 6 in the buffer memory 3 and writing the same, and the neglected bit data output from the subtractor 6 can be realized. The same is true by separately providing a memory for storing the data and controlling the reading with the buffer memory 3. With such a configuration, it is convenient for the buffer memory 3 to have a capacity of m × n bytes.

Further, such neglected bit number data is
It is not necessary to have it as data in m bytes.
It may be held in the ID data area in 6. FIG. 2 shows an embodiment for time-axis-multiplexing ignored bit number data in addition to m-byte data. 9 is a switch and 10 is a memory.

Next, the operation will be described. Basically,
Since the operation is the same as that in FIG. 1, only different points will be described. One input value of MIN5 is C (m ×
8-5), it becomes m × 8 in FIG. This is because the ignored bit number data and the m-byte data are stored outside the m-byte data so that the m-byte data can be fully used. Therefore, C ′ = m × 8 in FIG. Further, since the output of the subtracter 6 is time-division multiplexed after being given an error correction code, it becomes necessary to store it in the memory once. The memory 10 is a memory for that purpose, and is configured so that the data stored in the memory 10 and the output of the error correction encoder 8 can be switched by the switch 9. However, when the switch 9 is connected to one side, the other side must necessarily stop the output (reading). The data output from the circuit operating in this way is as shown in FIG.

Needless to say, the original ID data and SYNC data may be added to and stored in the memory 10, and if not, the ID and ID are stored somewhere else.
There is a block to which SYNC data is added. Also,
In FIG. 2, the ignore bit is multiplexed with the ID data, but for example, 1976 of IEEE Transactions on Information Theory.
Year No. 4 P462 ~ P468 `` New Classes of Binary Co
des Constructed on the Basis of Concatenated Codes
A method of multiplexing in C1 parity using a technique such as a superposition code disclosed in “and Product Codes” may be used. Further, it goes without saying that the above-mentioned variable length coding may be a variable length code having a mode of escaping to a fixed length.

Next, the second invention of the present application will be described with reference to the drawings. FIG. 3 shows an embodiment of a decoding device when the data is encoded by the encoding device of FIG. 1 and is decoded via a transmission medium such as a tape. In a transmission system such as a tape medium, there may be a product only for reproduction, and thus a product using a decoding device may also exist. In FIG. 3, 11 is an ignoring bit number data recognition circuit, 12 is a switch, 13 is a code inverse converter,
14 is an error correction decoder.

Next, the operation will be described. The signal that has passed through the transmission medium (reproduced output by the tape recorder) is corrected by the error correction decoder 14 due to the poor S / N of the transmission line and the error is corrected, and is output as correct data. ..
In the case of special high-speed reproduction at the time of reproduction on a tape recorder or the like, it is convenient to perform decoding in C1 block units, but after performing error correction decoding in C1 block units,
In order to control how many bits of data are ignored and variable length decoding is performed by the ignore bit number data recognition circuit 11 that takes in the ignore bit number data at a specific position from m bytes of data, the switch 12 is used. Control signal to
It controls the input to the code reverse converter 13. In the above description, the ignored bit number data is 5 bits. Therefore, assuming that the ignored bit number is k bits, the switch 12 may be turned off so that k + 5 bit data is not subjected to code reverse conversion. Further, the code inverse conversion circuit 13 may perform the variable length decoding operation after the switch 12 is turned on. If the code reverse conversion circuit 13 is allowed to perform the decoding inhibition mask operation, the flag of the bit performing the mask operation is set to k +.
It suffices to set up 5 bits, and in that case, erroneous operation does not occur without the switch 12. With such a configuration, for example, 3 bits after the dotted line in FIG. 22 are not subjected to variable length decoding, and correct decoding is performed from the 4th bit, so that a problem such as symbol garbling does not occur.

When the embodiment as shown in FIG. 2 of the present application is taken, the input of the ignore bit number data recognition circuit 11 may be a signal taken out from before the error correction decoder 14.

Further, in the first and second inventions of the present application, the case where only the variable length coding is performed has been described. However, even in the coding in which the fixed length coding and the variable length coding are combined, the variable length coding is performed. The encoding using a plurality of encoding methods may be used, and the double Reed-Solomon code is adopted as the error correction code, but any error correction code for fixed length data whose length is not variable in block units may be used, for example, BCH.
It goes without saying that coding such as codes, cross-interleaved codes, and trellis coding in which the code length is variable to some extent may be used. Further, in the embodiment, one ignore bit data is added to the C1 block, but if the error correction block size is small, one ignore bit data may be added to m × n bytes. When multiple variable-length coding methods (including fixed-length coding) are used, the encoder attaches the information indicating the method together with the data of the number of ignored bits, and the decoding side recognizes the information. Then, it may be decoded by a decoder that performs variable length decoding (including fixed length decoding). The simplest example is to use a fixed-length encoder in some cases (for example, when the frequency of occurrence in a statistical sense is not biased), and a variable-length encoder in other cases. In some cases, some variable length coding tables are used for coding. Also, if there is other header information, it may be multiplexed with it.

Next, the third invention of the present application will be described with reference to the drawings.
FIG. 6 is a block diagram showing an embodiment of the encoding device of the third invention of the present application. In FIG. 6, 15 is a comparator,
Reference numeral 16 is a switch, and 17 is a save buffer.

Next, the operation will be described. The input data is variable-length coded by the code converter 1 and temporarily stored in the save buffer 17. On the other hand, the code length detector 3 detects the code length of the generated conversion code,
The code length generated by the cumulative adder 4 is cumulatively added to count the total code amount generated, and the code length generated by the cumulative adder 4 is cumulatively added to count the total code amount generated. It is determined whether the output of the cumulative adder 4 is input to a comparator 15 that compares it with a constant C ', and a predetermined number C'is not exceeded. If a certain number C'is exceeded, a control signal is sent to the switch 16, and the switch 16 is turned off so that the variable length code of one symbol of the variable length code that causes the overflow is not sent to the buffer memory 3. At the same time, in the reading of the save buffer, the reading is stopped after reading the symbol immediately preceding the one symbol of the variable-length code that caused the overflow. The buffer memory 3 has a capacity capable of writing m × n bytes of data, and the m × n bytes of data are stored in the error correction encoder 8
Every time the transmission is completed, the data is initialized to all 0s. Normally, the buffer memory 3 is composed of DRAM, etc.
Since there are two n-byte memories and the memory used for reading and the memory used for writing are selectively switched, the memory allocated to the write side after the memory switching operation at the time of this switching. Should be initialized to all 0s before writing the data. In the above operation, it is detected that the variable-length coded data crosses the boundary of m bytes, and the variable-length code for one symbol, which is the cause, is distributed to the next m bytes. Which is equivalent to inserting 0 in the margin. That is, the output data of the encoding device is as shown in FIG.
The pattern is as shown in. In FIG. 7, when the symbol after variable-length coded data of 0001 is code-converted to have 3 bits or more, 2-bit 0 of 00 is inserted. Of course, the variable-length code corresponding to the symbol having more than 3 bits is the next m
When the byte data is created, it is read from the save buffer 17 and arranged so as to be arranged at the head of the m-byte data.

In the above description, the data of all 0s is inserted in the margin, but this requires some work when creating the coding table. In other words, the idea is to create an encoding table so that symbols corresponding to all 0's do not actually exist. This will be described with reference to FIG. FIG. 8 is a variable length coding table for variable length coding the same symbols as in FIG. At this time, in FIG.
8 is assigned to the symbol, but in FIG. 8, the number of symbols called dummy data is increased by one and the symbols of all 0 are assigned to the dummy data. Performing variable-length coding based on such a variable-length coding table is the premise of the third invention of the present application. This (special) dummy data of all 0s is included in the variable length coding table, but it is not always all 0s.
Alternatively, the branch conversion of the binary tree representation of FIG. 8 may be performed so that the data of all 1s becomes dummy data, or even if all do not have the same value, the dummy data Any value may be used as long as it is a code that takes out an arbitrary bit from the beginning and never matches any code having the same number of bits in other symbols.
When the dummy data is all 1, all 1's worth of m × n bytes may be written during the above initialization operation.

The operation of the decoder for such an encoder will be described below. In an extremely special case such as special reproduction, the start of variable length decoding is m bytes in the usable C1 block because the start of m bytes is always the start bit of the variable length code in such an encoder. It only has to be set for each. This is because there is no applicable symbol for the special code at the tail of m bytes. Specifically, FIG.
There is no symbol that applies to the last 2-bit data of 00 in, and at the beginning of the next m bytes,
Since it is guaranteed that it is the head of the variable length coding of another symbol, this 2-bit 00 data may be discarded. That is, the data can be decoded by recognizing the boundary of m bytes and finally providing a data discarding circuit for discarding the data for which the variable length decoding is not successful. Further, the data discarding circuit described above is realized as a circuit for generating the inverse conversion prohibition bit mask of the code inverse converter 13. If this data discarding circuit does not exist, when decoding consecutive C1 blocks, the special data of the previous C1 block is not discarded and remains in the code inverse converter 13. A new problem arises that the data at the beginning of the next C1 block is garbled into data of a different symbol. For example, if the last 2-bit data of 00 remains without being discarded and there is a variable length code 1 such that the next symbol is A, the code inverse converter 13 calls 001. The code reverse conversion is established for the data, and the symbol C is garbled. This is the same as the fifth embodiment of the present invention.

Next, the fourth invention of the present application will be described with reference to the drawings.
FIG. 9 shows an embodiment of the encoding device of the fourth invention of the present application.

The input data is variable-length coded by the code converter 1 and temporarily stored in the save buffer 17.
On the other hand, the code length detector 2 detects the generated code length, and the cumulative adder 4 performs cumulative addition to count the generated code amount and inputs it to the comparator 15. The comparator 15 compares the generated code amount with a certain constant C ′, and when it exceeds a certain constant C ′, sets a retransmission request flag in the save buffer 17. Upon receiving the retransmission request flag from the comparator 15, the save buffer 17 reads the variable length code again from the beginning of the code. A specific example will be described. For example, since the data after the data of 0001 (symbol D) in FIG. 7 is controlled to have a fixed length of m bytes, there is a margin of 2 more bits. The symbol to be transcoded next is E
Considering the case of, the two bits from the head bit of E, that is, 00 which is the first two bits of the code of 00001 is added after 0001 of the symbol D.
Immediately after this, if the retransmission request is not issued, the symbol E of 0000
The remaining 3 bits of 001, 001, will be placed at the beginning of the next m-byte C1 block.
Comparator 15 reports that the first two bits of the 01 code, 00, are added and the C1 block is full.
Is detected and a retransmission request flag is set, the save buffer 17 stores the data of symbol 00001 in the next C
It operates so that the first bit is read again in one block. In other words, the leading 2 bits of the symbol E are placed in the margin bits of the C1 block, and the next C1 block is placed 5 bits from the beginning of the symbol E.
The first 2 bits are duplicated in this example, but C1
At the beginning of the block, the beginning of the variable length code is guaranteed.

Next, the fifth invention of the present application will be described with reference to the drawings. FIG. 10 shows an embodiment of the decoding device of the fifth invention of the present invention. In FIG. 10, 19 is a code reverse conversion availability determination circuit, 20 is a buffer, and 21 is a switch.

Next, the operation will be described. The basic principle is
Since it is the same as the decoding device corresponding to the encoding device of the third invention of the present application, the basic description is omitted. The input in Figure 10 is
It is a signal obtained by passing the data encoded by the encoding device through a transmission medium. The error correction decoder 14 detects and corrects the error generated in the transmission line of the input signal shown in FIG. 10, and it is output as a code of a minimum m-byte unit and temporarily stored in the buffer 20. On the other hand, it is input to the code reverse conversion propriety determination 19, and it is determined whether variable length decoding (code reverse conversion) is established by monitoring the first 1 bit of m-byte data, and if it is determined, the buffer 20 The variable length code established from the above is read, the switch 21 is turned on, and the code inverse converter 13 successively performs variable length decoding for each symbol. Third of the present invention
The encoders of the fourth and fourth inventions differ in the processing method of the tail of m bytes, but in both cases, if the processing of the data of m bytes is completed without the variable length decoding being established in the tail, the data may be discarded. While the variable length decoding is not established, the switch 21 is in the OFF state, and since the variable length code is not sent to the code inverse converter 13, the processing of m-byte data is completed or the switch 21 remains OFF. The operation of initializing all m-byte data and storing the next m-byte data is performed. In this way, an operation equivalent to that of the data discarding circuit described above becomes possible.

The third invention of the present application is devised from the case of creating the encoding table and inserts the special code in the margin. The fourth invention does not perform any such operation, and the next C1 block However, the decoding apparatus according to the fifth invention of the present application enables decoding without the problem of symbol garbling. It is necessary to perform such an operation not only during this decoding and trick play but also during normal transmission.

Next, the encoding device of the sixth invention of the present application will be described with reference to the drawings. FIG. 11 shows an embodiment of the sixth invention of the present application. In the figure, 22 and 23 are switches, 24 is a buffer memory 1, and 25 is a buffer memory 2.

Next, the operation will be described. The input signal is variable length coded by the code converter 1 and stored in the buffer memory 24. On the other hand, when special data is coded, the switch 22 is turned on and stored in the buffer memory 25. The switch 23 is normally connected to the upper side, but when it reaches a certain position of m × n bytes, the switch 23 is connected to the lower side and the reading of the buffer memory 25 is started, and only a certain fixed data length is set. Buffer memory
The contents of 25 are time-division multiplexed and supplied to the error correction encoder 8. Naturally, the buffer memory 25 is read out while the switch 23 is connected to the lower side, and the reading of the buffer memory 24 is stopped during that time. Switch 23
When the connection is changed, the reading of the buffer memory 24 starts from the stopped address, and the reading of the buffer memory 25 stops.

Now, a specific example of when the switch 22 is turned on will be described with a specific example. When encoding a video signal, it is usual to apply DCT and variable length code the coefficients of the DCT, but since a lower order sequence of DCT coefficients usually has more important meaning, only a lower order sequence of an image is used. A rough recognition is possible. In such a case, if the switch 22 is turned on so as to send only the encoding result of the low-order sequence, the data of the low-order sequence has the image of being written twice in the time axis multiplex state. In extreme cases, low-order sequences are DC
Only the DC component is sufficient, and the DC component alone is data that can be used to understand a scene. Therefore, only the DC component is written twice. In consideration of the transmission capacity, the smaller the data written twice, the more convenient it is. Therefore, only the upper few bits of the DC component may be encoded. However, in such a case, the fixed length code before code conversion may be connected to the switch 22. Further, in the case of a scanning mode such as the NTSC or PAL system, since the odd field and the even field in one frame are similar signals, DC
An arithmetic means for obtaining the inter-field sum of the components may be provided, or an arithmetic means for gathering four DCT blocks to obtain an average value of the DC components may be provided and the arithmetic results thereof may be stored in the buffer memory 25. .. For example, if four DCT blocks are grouped, the DC components are averaged, the inter-field sum is calculated, rounded to 5 bits, and stored in a buffer memory, the code amount of about 3% of all data (excluding error correction code) So, the basic data of the image can exist. If this data is time-axis-multiplexed so as to be located in the shaded area in FIG. 23, it is possible to obtain the basic data with a certain high-speed reproduction. According to the calculation, it is possible to arrange the data so that the data can be reproduced up to an ultra high speed reproduction of about 20 times speed. Further, the twice-written data does not necessarily have to be written every frame, and the coding result of only one frame for several tens of frames is stored in the buffer memory 25 and then for the tens of frames. Even if the switches 23 are switched so that they are time-multiplexed little by little at a corresponding time, it is possible to arrange so that the data can be reproduced at the ultra-high speed reproduction. Furthermore, it is also possible to appropriately combine the above-described examples such that a low-order sequence, which is higher than DC of only one frame among dozens of frames, is encoded to some extent.

Next, the seventh invention of the present application will be described. In FIG. 12, 26 is an inverse DCT circuit, and 27 is an overlap smoothing circuit.

Next, the operation will be described. What is different from a normal decoding device is that it has a mode in which an image is decoded only from twice-written data when it is in an operation state such as ultra-high speed reproduction. The approach method is slightly different depending on what data was written twice. For example, as mentioned above, DC
When the encoding device is operated so that only one DCT block is written twice, only one data is present in one DCT block (or four), so that the boundary of the DCT block can be detected properly, and this block can be detected. Since the shape of the boundary is a rectangle, it may hinder the scene recognition of the image. A circuit for reducing this is shown in FIG. Inverse DCT circuit 26 inverse DCTs only DC,
A block-shaped image as shown in the upper diagram of FIG. Figure 1
3 In the above figure, 8 blocks A to J centering on the block E
Is shown. The size of this block E is the DCT when the data of each block of the DCT is written twice.
Matches the block size (usually 8x8 pixels) and is 4D
4DC if the average DC value of the CT block is attached
Matches the T block size. After obtaining data such as a block-shaped reproduction screen, the overlap smoothing circuit 27 described later makes the boundaries of the blocks inconspicuous,
It becomes the basic data output to the TV monitor as an ultra-high speed playback screen. The operation of the overlap smoothing circuit 27 will be described below. It is considered that the decoded data of each block A to J in FIG. 13 is, for example, a block that is expanded about itself four times in area and twice in length as its center.
By doing so, 9 in the upper diagram of FIG.
The three blocks overlap each other, and the blocks overlap as shown in the lower diagram of FIG. A in the lower diagram of FIG. 13 indicates that A in the upper diagram is expanded, B ′ is B, C ′ is C, D ′ is D, and E ′ is E, respectively. In this way, for example, it is shown how the value of the shaded portion of the block E (shown by a dotted line in the lower part of FIG. 13) can make the block boundary inconspicuous. In the shaded area in the lower part of FIG. 13, the part near the center of the block E passes through the block E in the upper part of FIG. 13 as it is, and the part near the boundary of the block E halves the data in the block E, and the data from other blocks is overwritten. The laps are added and averaged. In particular,
A window function such as a sine function is applied to the block of E ′ and added with the overlap data. At this time, it should be noted that the dynamic range is not expanded when the overlap amount is added. That is, it is necessary to prevent the result of adding by multiplying a function having a value of 1 or more from becoming 1 or more. As a smoothing means other than the overlap smoothing, the same DCT coefficient may be obtained by interpolating the own DCT coefficient from the DCT coefficients of adjacent blocks as shown in FIG. The effect is obtained. For example, an example for interpolating the next higher-order sequence from only the DC component will be shown below. For example, the C ₂₁ component of the E block (shown in the lower diagram of FIG. 14) may be obtained by subtracting the DC component of the H block from the DC component of the B block and multiplying a certain coefficient ρ, and the C ₂₁ component is the DC component of the D block. It is sufficient to subtract the DC component of the F block from the component and multiply it by a certain coefficient ρ. It can be understood that such interpolation works well when considering the basis function of DCT.

Next, the eighth invention of the present application will be described with reference to the drawings. FIG. 15 shows a decoding device according to the eighth invention of the present application. Figure 1
Reference numeral 28 in 5 is a validity determining circuit for the C1 block.

Next, the operation will be described. For example, since the encoding device of the present application attaches an error correction code to fixed-length data, if there is no error in the unit of error correction block, it becomes possible to perform variable-length decoding without symbolization. For example, a video signal In the case of performing variable length coding by blocking as in the coding of No. 2, there is always a code called a block delimiter called EOB (End of Block). So unless such a code is decrypted,
The DCT coefficients to be inversely transformed by DCT do not exist. For example, C
When the validity determination circuit 28 of the C1 block detects that an error has occurred in one block, the EOB code may not be reached. In such a case, 0 is inserted in the remaining sequence, inverse DCT is performed, and a reproduced image is operated. By doing so, the last block is decoded for the time being, and moreover, by substituting 0 for the higher-order sequence, it is possible to prevent decoding into abnormal data.

Next, the ninth invention of the present application will be described with reference to the drawings. In FIG. 16, 29 is a switch and 30 is a buffer.

Next, the operation will be described. The operation of this circuit is very similar to the ninth invention of the present application. When the validity judging circuit of the C1 block judges that the following C1 block has an uncorrectable error, and when the EOB data cannot be reached, the EOB data stored in the buffer 30 is missing. By discarding the DCT coefficient of the DCT block by turning off the switch 29, it is possible to avoid causing an abnormal decoding result.

The eighth and ninth inventions of the present application are specific examples on the premise that data of variable length code of video signal of m × n bytes is continuously reproduced.
The first invention of the present application in which information of a certain fixed position in xn bytes of data is filled with other data, or
In the case of the encoding device according to the sixth aspect of the invention, it goes without saying that such data does not need to be connected to the inverse DCT circuit and may be configured to be turned off by the switching operation at that position.

In addition, m obtained in the double reed solomon
It is usual to shuffle data of × n bytes and perform error correction coding, but there are cases where error correction is performed in C1 units, and when the data is variable length coding, Data shuffling should not be done in a chaotic manner.

Further, although the above-mentioned method deals with a very limited encoding method, as described above, the error-correcting code may be another code as long as it is attached to fixed-length data,
It goes without saying that the variable length code may be, for example, a Fano code other than Huffman coding, and the DCT may be another orthogonal transform. With respect to shuffling, there is no particular problem even if shuffling with EOB as one unit is applied so that the order of the variable length code is not broken, and information indicating the position of the block of the video signal is displayed on the time axis. May be multiplexed.

Also, when decoding by the encoding device of the sixth invention of the present application, special reproduction was mainly described, but if an uncorrectable error occurs, interpolation is performed based on the twice-written data. Needless to say, it may be used for such error data interpolation work. For example, a method of using DC component data may be used.

[0061]

As described above, according to the first invention of the present application, since the first ignored bit number information of the C1 block is time-division multiplexed, the ignored bit number information can be easily recognized at the time of decoding. Has the effect of becoming.

According to the second invention of the present application, since the ignore bit is recognized at the time of decoding and the data not subjected to the variable length decoding is ignored and decoded, the symbol is prevented from being garbled at the time of decoding. The effect is that you can.

According to the third invention of the present application, the case where the variable length code of one symbol is arranged so as to cross the C1 block is detected, and in such a case, a special code is inserted into the C1 block. Since this is done, there is an effect that it is possible to realize a decoding device in which there is no symbol garbled at the time of decoding.

According to the fourth invention of the present application, the case where the variable length code of one symbol is arranged so as to cross the C1 block is detected, and in such a case, the symbol is placed at the head of the next C1 block. Since the variable length code of 1 is arranged again from the first bit, there is an effect that it is possible to realize a decoding device that does not garble symbols during decoding.

According to the fifth invention of the present application, the data for which variable length decoding is not established at the end of the C1 block at the time of decoding is
Next, since the decoding is performed without considering the variable length decoding of the C1 block, it is possible to prevent the symbol garbling from occurring during the decoding.

According to the sixth invention of the present application, since the data having a high compression rate is inserted again at a specific position at the time of encoding, it is necessary to put important data at a position that can be always reproduced at the time of special reproduction. Will be able to
Only important data can now be played during special playback.

According to the seventh invention of the present application, a mode for decoding only important data is provided at the time of decoding, so that a good decoded image can be obtained even at ultra-high speed reproduction.

According to the eighth invention of the present application, E is applied in the case of encoding such as orthogonal transform encoding like a video signal.
If it is detected that there is an uncorrectable error in the subsequent data without reaching the OB data, the data is not used and is decoded by inserting 0, resulting in an abnormal decoding result. There is an effect that it can be decrypted without any.

According to the ninth invention of the present application, in the case of encoding such as orthogonal transform encoding such as a video signal, E
When it is detected that an uncorrectable error exists in the subsequent data without reaching the OB data, the data in that block is discarded, so that the decoding can be performed without an abnormal decoding result. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an encoding device of a first invention of the present application.

FIG. 2 is a block diagram showing an embodiment of the encoding device of the first invention of the present application.

FIG. 3 is a block diagram showing an embodiment of a decoding device according to a second invention of the present application.

FIG. 4 is a code configuration of the encoding device of the first invention of the present application when encoded in FIG. 1.

5 is a code configuration of the encoding device of the first invention of the present application when encoded in FIG.

FIG. 6 is a block diagram showing an embodiment of an encoding device of a third invention of the present application.

FIG. 7 is a code configuration of the encoding device of the third invention of the present application when encoded in FIG.

FIG. 8 is an example of creating an encoding table of a variable-length encoder of the encoding device of the third invention of the present application.

FIG. 9 is a block diagram showing an embodiment of an encoding device according to the fourth invention of the present application.

FIG. 10 is a block diagram showing an embodiment of a decoding device according to the fifth invention of the present application.

FIG. 11 is a block diagram showing an embodiment of an encoding device according to the sixth invention of the present application.

FIG. 12 is a block diagram showing a device of a decoding device according to a seventh invention of the present application.

FIG. 13 is a diagram for explaining the circuit operation of FIG.

FIG. 14 is a diagram illustrating a device other than that shown in FIG. 12;

FIG. 15 is a block diagram showing an embodiment of a decoding device of an eighth invention of the present application.

FIG. 16 is a block diagram showing an embodiment of a decoding device of the ninth invention of the present application.

FIG. 17 is a code configuration diagram of a double Reed-Solomon code.

FIG. 18 shows a conventional code configuration example.

FIG. 19 is a tape pattern of a helical scan type tape recorder.

FIG. 20 is an example of a variable length coding table.

FIG. 21 is a conventional encoding device.

FIG. 22 is an example of a reproduction envelope when performing high-speed reproduction with a helical scan type tape recorder.

FIG. 23 is a head locus when the envelope shown in FIG. 22 is output.

FIG. 24 is a diagram pointing out a problem of a conventional encoding device.

FIG. 25 is a diagram showing that a video signal is subjected to two-dimensional orthogonal transform and variable-length coding.

FIG. 26 is a diagram showing subband encoding of audio data.

[Explanation of symbols]

 1 Code Converter 2 Code Length Detector 3 Buffer Memory 4 Cumulative Adder 5 Minimum Value Circuit (MIN) 6 Subtractor 7 Switch 8 Error Correction Encoder 9 Switch 10 Memory 11 Ignored Bit Number Data Recognition Circuit 12 Switch 13 Code Reverse Converter 14 Error correction decoder 15 Comparator 16 Switch 17 Save buffer 19 Code reverse conversion propriety determination circuit 20 Buffer 21 Switch 22 Switch 23 Switch 24 Buffer memory 25 Buffer memory 26 Inverse DCT circuit 27 Overlap smoothing circuit 28 C1 block Validity judgment circuit 29 Switch 30 Buffer

Claims (9)

[Claims] 1. A variable length coding means for code-converting digital data into a variable length code length, and a constant length for a data string including data which is no longer fixed length by the variable length coding means. An error correction coding means for adding an error correction code by separating with an error correction code. An encoding device characterized in that the means and the data generated by the calculating means are time-axis multiplexed. 2. A decoding device for decoding a data string in which digital data is coded by variable length coding and error correction coding, and error correction decoding means for detecting and correcting an error generated in a transmission line. And a variable length decoding means for performing code reverse conversion of variable length code length data,
Decoding characterized by including means for extracting data of the number of ignored bits up to the beginning of the variable-length code after delimitation of the error-correcting code, and mode for not performing variable-length decoding on the number of ignored bits generated by the extracting means. Device. 3. A variable length coding means for code-converting digital data into a variable length code length, and a constant length for a data string including data which is no longer fixed length by the variable length coding means. It is an encoding device provided with an error correction encoding means which is divided by and is attached with an error correction code, and it is detected whether a code for one symbol of variable length encoding is arranged before and after the above division. Means for inserting the special code, and the special code inserting means for inserting the special code in front of the delimiter, and the inserted bit number for shifting the code of the symbol backward. An encoding device, comprising: a code rearrangement means for arranging the code. 4. A variable length coding means for code-converting digital data into a variable length code length, and a fixed length for a data string including data which is no longer fixed length by the variable length coding means. It is an encoding device provided with an error correction encoding means which is divided by and is attached with an error correction code, and it is detected whether a code for one symbol of variable length encoding is arranged before and after the above division. And a code rearrangement means for rearranging from the first bit of the code for the symbol after the delimiter when the arrangement detects such arrangement. Characteristic encoding device. 5. A decoding device for decoding a data string in which digital data is coded by variable length coding and error correction coding, and error correction decoding means for detecting and correcting an error generated in a transmission path. And a variable length decoding means for performing code reverse conversion of variable length code length data,
If the code reverse conversion does not work even if the code reverse conversion progresses to the position corresponding to the delimiter of the error correction code, the data is discarded, and the code reverse conversion when proceeding to the next delimiter of the error correction code is the above delimiter. A decoding device characterized in that the inverse conversion is started again from the beginning of the. 6. An encoding device for encoding and transmitting digital data such as video and audio, wherein a rough content is multiplexed and encoded at a specific position on the transmission medium. Device. 7. A decoding device for decoding digital data, comprising a mode for decoding data such as video and audio using only data of a preset part of all codes. Device. 8. A decoding device for decoding a data sequence transmitted by dividing digital data into blocks, orthogonally transforming and variable-length encoding and dividing the data with a certain length,
If the subsequent delimited data string becomes unusable due to the transmission path, and if the valid data is interrupted while the data indicating the end of the block has not been transmitted, the rest of the blocked data A decoding device, characterized in that 0 is inserted into the data of (1) to perform an inverse orthogonal transform. 9. A decoding device for decoding a data sequence transmitted by dividing digital data into blocks, orthogonally transforming and variable-length coding and dividing the data with a certain length.
If the subsequent delimiter data string becomes unusable due to the transmission path, and if the valid data is interrupted while the data indicating the end of the block has not been transmitted, the data in the block is discarded. A decoding device characterized by: