JP2720717B2 - Video signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus for compressing a digital video signal and recording and reproducing it on a recording medium.

[0002]

2. Description of the Related Art In recent years, D1, D2 video tape recorders (hereinafter referred to as VT) for digitizing and recording / reproducing video signals.
Abbreviated as R. ) Has been developed. As consumer devices, video floppy capable of recording and reproducing digital still images and VTR capable of recording digital moving images have been developed. Examples of development of consumer digital VTRs include the Journal of the Institute of Television Engineers of Japan (Vol.45, No.7, pp813-
819, 1991). In this consumer digital VTR, the degree of redundancy of the video signal is recorded by compressing the data amount to about 1/5 using various methods.

[0003] A conventional video signal processing apparatus will be described below. FIG. 4 is a block diagram of a conventional video signal processing device. 5 is an explanatory diagram of the format of the video signal processed in FIG. 4, FIG. 6 is an explanatory diagram of a configuration of one block, and FIG. 7 is a configuration diagram of a signal for one track of a tape.

In FIG. 1, reference numeral 1 denotes an input terminal to which a digitized video signal is input, and 2 denotes a video signal input to the input terminal 1 as a luminance signal (hereinafter abbreviated as a Y signal) and a color difference signal (R-signal). A shuffling unit 3 for blocking each of the Y signal and the BY signal into a signal of 8 × 8 pixels, and 3 a two-dimensional discrete cosine transform (hereinafter DC) of an output signal of the shuffling unit 2.
Abbreviated as T. ), A DCT unit for quantizing an input signal using nine types of quantization steps, a quantization controller for obtaining a minimum quantization step with a data amount equal to or less than a predetermined data amount, and a quantization controller for 5 In the quantization step obtained in step 4, D
A quantizer for quantizing the signal output from the CT unit 3;
Is a variable-length encoder that converts a signal output from the quantizer 5 into a code of 3 to 16 bits using a Huffman code,
7 is a shuffling unit 2, a DCT unit 3, a quantization controller 4,
This is a compressor composed of a quantizer 5 and a variable length encoder 6. The video signal compressed by the compressor 7 is formatted into a predetermined format by a formatter 8, and an error correction code is added by a first error correction unit (hereinafter abbreviated as an ECC unit) 9. Reference numeral 10 denotes a modulator. The modulated output is amplified by an amplifier 11 and then recorded on a tape 13 by a first magnetic head 12. 14, a second amplifier for amplifying the signal reproduced by the second magnetic head 15, 16 a demodulator, 17 a memory 1
8 is a second ECC unit for performing error correction processing via the reference numeral 8, 19 is a deformatter for returning the rearrangement processing performed by the formatter 8 during recording, and 20 is a variable length for decoding a variable length code which is an output signal of the deformatter 19. A decoder 21 is an inverse quantizer which multiplies the output signal of the variable length decoder 20 by the reciprocal of the quantization step at the time of recording. A decoder 22 is a signal of 8 × 8 unit output from the inverse quantizer 21 and is two-dimensional. ID for calculating inverse DCT
The CT unit 23 outputs the output signal of the IDCT unit as a Y signal, RY
Signal and a BY signal, which are converted into parallel signals.
4 is output. Reference numeral 25 denotes an expander including a variable length decoder 20, an inverse quantizer 21, an IDCT unit 22, and a deshuffling unit 23.

The operation of the conventional video signal processing device configured as described above will be described below.

First, the operation at the time of recording will be described. The video signal input to the input terminal 1 (one frame is a Y signal 7
20 × 480 pixels, the color difference signals of the RY and BY signals are each composed of 180 × 480 pixels, and each pixel is an 8-bit value) is input to the compressor 7 and compressed. In the compressor 7, first, the input signal is a Y signal, an RY signal,
Each of the BY signals is divided into 8 × 8 pixel units.
Each of the blocked signals is output to the DCT unit 3 where a two-dimensional DCT operation is performed. The DCT unit 3 outputs the operation result of the two-dimensional DCT operation from the DC value having low horizontal and vertical frequency components to the AC value having high frequency to the quantizer 5 and the quantization controller 4. The quantization controller 4 is for 20 blocks of the Y signal output from the DCT unit 3 and for 5 blocks of the RY signal,
The data amount is calculated using a total of 30 blocks for 5 blocks of the BY signal as one unit. The nine types of quantization steps used here are performed by multiplying the input signal by 1, 1/2, 1/4, 1/8, or the like. The quantization controller 4 compares the number of accumulated codewords when performing variable length coding on the signal after quantization with a predetermined target value, and sends the minimum quantized value Brn not exceeding the target to the quantizer 5. Output. The quantizer 5 performs quantization based on the quantization step value Brn supplied from the quantization controller 4. The variable-length encoder 5 performs variable-length encoding using a Huffman code in which a combination of the number of consecutive zero values of the input signal and the subsequent value is assigned to a short bit length in the order of occurrence probability. The AC component of each block is variable-length coded into a code word of 3 to 16 bits excluding the DC value. Each variable-length coded block includes a 9-bit DC value, a variable-length coded AC component, and an end flag (hereinafter abbreviated as EOB) indicating the end of the block.

[0007] The output signal of the compressor 7 is supplied to a formatter 8 where it is divided into a low frequency component and a high frequency component and formatted. FIG. 5 shows a format of 30 blocks. Thirty blocks are formatted into three syncs. Sink 0 and Sink 1 are provided with ten 10-byte areas for each Y signal, and five five-byte areas for color difference signals of RY or BY signals. The signal output from the compressor 7 is first packed in this area without gaps in code word units from low frequency component code words in order from the DC value. Then, in the case of the block of the Y signal, the blocks are packed until the total number of bits of the code word becomes 65 or more. In other words, writing is performed up to the maximum number of words in which the code word is not missing (the maximum code word length is 16 bits, so that the process is stopped when the Y signal block becomes 64 bits or more. Will be discontinued.) This process is 3
This is performed on the signal of block 0. The signal packed in this process is a low-frequency signal (abbreviated as LAC), and the overflow signal that cannot be processed is a high-frequency signal (abbreviated as HAC).

[0008] After the formatter 8 packs each LAC of the signal of 30 blocks into a predetermined position, it performs a process of packing the remaining HAC. This operation will be described with reference to FIG.
If the EOB is not packed, a 10-byte area for the Y signal packed with the LAC or a 5-byte area for the RY signal or the BY signal has a free area of 0 to 15 bits. The HAC is packed into this empty area without any gap. At this time, the HAC generated in the first sync 0 is the sync 0
The HAC generated in the sink 1 is packed into the empty area of the sink 1. Since the stuffing is performed so as to completely fill the empty area, the codeword may be divided in units of one bit at the worst and stuffed over many areas. If the HACs of the sinks 0 and 1 cannot fill the free area of each sink, the remaining H
AC is packed. And after packing the highs,
Is output to the ECC unit 9. At the same time, a TOP indicating the position of the boundary of the HAC between the sink 0 and the sink 1 in the sink 2 is also output. The first ECC unit 9 applies a double error correction code (ER0) to the 81 syncs output from the formatter 8.
And ER1), and outputs the result to the modulator 10. The modulator 10 converts the input signal into 8/10 and outputs the converted signal to the first amplifier 11. The first amplifier 11 amplifies the input signal,
The signal is recorded on the tape 13 by supplying the signal to the magnetic head 60. FIG. 7 shows the structure of a signal for one track recorded on a tape. One track has 81 syncs (Y signal 54
0 block, 135 blocks of RY signal, 1 block of BY signal
35 blocks), one frame of video signal is recorded on 10 tracks.

Next, the operation at the time of reproduction will be described. The signal reproduced by the second magnetic head 15 is supplied to the second amplifier 14.
Is added to The signal amplified by the second amplifier 14 is
The signal is demodulated by the demodulator 24 and output to the second ECC unit 17. The second ECC unit 17 detects an error position using the error correction codes ER0 and ER1 added at the time of recording, and if an error can be corrected, corrects the error and writes it to the memory 18. Here, when there is a portion where even one bit cannot be corrected among the three syncs, it is not written into the memory 18. Memory 1
Since 8 has a capacity of 810 syncs for one frame, when an uncorrectable error occurs in the recording / reproducing system, signals of three syncs at the same position one frame before are supplied to the deformatter 19. . The deformatter 19 is the second EC
The signal output from the C unit 17 is reconstructed, and the LAC and HAC of the same block formatted at different positions are connected and output to the variable length decoder 20. The variable length decoder 20 detects and decodes a codeword from the input signal.
In the case of decoding, if there is an error even in one bit, the error propagates and causes a great deterioration in image quality.
When an error has occurred in the variable length decoder 20, there is no malfunction in the variable length decoder 20 because the signal has been replaced with the correct signal of three syncs one frame before. The output signal of the variable length decoder 20 is supplied to an inverse quantizer 21 where the output signal is multiplied by a reciprocal of a value used for quantization at the time of recording and output to an IDCT unit 22. IDCT2
2 performs a two-dimensional IDCT operation on the input signal,
Output to the deshuffling unit 23. Deshuffling part 2
Reference numeral 3 rearranges the input signal in parallel with the Y signal, the RY signal, and the BY signal, and outputs the rearranged signal to the output terminal 24.

[0010]

However, in the above-described configuration, in order to prevent a malfunction in the variable length decoder, when an error that cannot be corrected even in one bit is generated in three syncs, three bits before one frame are used. Replace with sync block. Therefore, in the case of an image signal having a sharp movement, interpolation is performed using a signal that is significantly different from the information one frame before, and the image quality is greatly deteriorated. During high-speed playback, 1
Since the magnetic head for reproducing the track obliquely crosses and reproduces the track, the probability that the signals of three syncs are completely reproduced is reduced. In this case, if a previous correct signal stored in the memory is output, this signal is a signal several frames or more before, and this causes a great deterioration in image quality.

The present invention solves the above-mentioned conventional problems. When an error occurs in three syncs, it is possible to decode a variable-length signal using only low-frequency components of a sink where no error occurs. Then, the number of interpolation points using the previous frame information is reduced. As a result, it is an object of the present invention to provide a video signal processing device that reduces image quality deterioration.

[0012]

In order to achieve this object, a video signal processing apparatus according to the present invention uses a discrete cosine transform and a variable length coding for one or a plurality of blocks each composed of m × n pixels. A low-frequency component obtained by dividing the compressed signal of each block output from the compressor by a predetermined data amount or less from a lower frequency component, and a high-frequency component exceeding the predetermined data amount. A formatter for formatting components into different regions, an error corrector for adding an error correction code to the output signal of the formatter, a recording / reproducing device for recording and reproducing the output signal of the error correcting device, and a signal reproduced from the recording / reproducing device And an error corrector that outputs a correction flag indicating an uncorrectable position from the added error correction code, and a signal output from the error corrector and a correction flag. Based on the modification flag has a deformatter for adding end flag to low frequency components of each block, and inputs the output signal of the deformatter, the structure having a decompressor for decompressing an input signal.

[0013]

According to the present invention, when an uncorrectable error occurs in a signal recorded and reproduced by the above configuration, the error correction circuit detects in which block the error has occurred from the error correction code added during recording. Then, an end flag is added to the low-frequency signal of the block in which no error has occurred to enable decoding of the variable-length signal. As a result, a malfunction in the variable length decoder is prevented, and it is possible to reduce the reproduction quality of an image signal with a sharp movement and the deterioration of the image quality at the time of special reproduction such as high-speed reproduction.

[0014]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a video signal processing device according to the present invention. FIG. 2 is a diagram for explaining an error position, and FIG. 3 is a diagram for explaining the operation of a deformatter.

In FIG. 1, reference numeral 50 denotes an input terminal to which a digitized video signal is input, and reference numeral 51 denotes a video signal input to the input terminal 50 by converting a Y signal, an RY signal, and a BY signal into 8 × each. A shuffling unit 52 that blocks the signal into eight pixels, and 52 outputs a two-dimensional D
A DCT unit that performs CT, a quantization controller 53 quantizes the signal input from the DCT unit 52 in nine types of quantization steps, and obtains a minimum quantization step that is equal to or less than a predetermined data amount. A quantizer that quantizes the signal output from the DCT unit 52 in the quantization step obtained by the controller 53. A signal 55 is output from the quantizer 54 using a Huffman code to generate a code of 3 to 16 bits. A variable length encoder for conversion, 56 is a shuffling unit 51, a DCT unit 5
2, a compressor including a quantization controller 53, a quantizer 54, and a variable length encoder 55. Reference numeral 57 denotes a first ECC unit which formats the video signal compressed by the compressor 56 into a predetermined format by the formatter 57, and adds an error correction code to the signal, 59 denotes a modulator, and the modulation output of the modulator 59 is After being amplified by the amplifier 60, it is recorded on the tape 62 by the first magnetic head 61. 63 is a second magnetic head 64
, A second amplifier 65 for amplifying the signal reproduced by the above, a demodulator 65, a second ECC unit 66 for performing error correction via a first memory 67, and 68 an output signal of the second ECC unit 66. A second memory 69 for storing a code length detector for combining the low band and the high band of each block while detecting the word length of the code word stored in the second memory 68, and 70 is a second ECC An end flag inserter that adds an end flag to the output signal of the code length detector 69 based on the modification flag output from the unit 66, 71 is a third memory that stores the output signal of the end flag inserter 70, and 72 is a second memory. , A code length detector 69, an end flag inserter 70, and a third memory 71. 73 is a variable length decoder that decodes a variable length code that is an output signal of the deformatter 72, 74 is an inverse quantizer that multiplies the output signal of the variable length decoder 73 by the reciprocal of the quantization step at the time of recording, and 75 is An IDCT unit that performs a two-dimensional inverse DCT operation on the 8 × 8 unit signal output from the inverse quantizer 74 is a deshuffling unit that rearranges the output signal of the IDCT unit 75. The rearranged digital video signal is output to an output terminal 77. Is output to 7
Reference numeral 8 denotes a variable length decoder 73, an inverse quantizer 74, and an IDCT unit 7.
5, an expander configured by the deshuffling unit 76.

The operation of the video signal processing apparatus according to the embodiment configured as described above will be described below.

First, the operation at the time of recording will be described. The digital video signal input to the input terminal 50 (one frame is composed of 720 × 480 pixels of a Y signal, the color difference signals of RY and BY signals are each composed of 180 × 480 pixels, and each pixel is 8 bits) is a compressor. 56, and the data amount is compressed. The shuffling unit 51 of the compressor 56 blocks the input signal into the Y signal, the RY signal, and the BY signal in units of 8 × 8 pixels. Each of the blocked signals is supplied to the DCT unit 52.
And a two-dimensional DCT operation is performed. DCT unit 52
Outputs the result of the two-dimensional DCT operation from the DC value to the AC component having higher horizontal and vertical frequencies to the quantizer 54 and the quantization controller 53. The quantization controller 53 performs nine types of quantization steps using a total of 30 blocks of 20 blocks for the Y signal, 5 blocks for the RY signal, and 5 blocks for the BY signal output from the DCT unit 52 as one unit. Calculate the data amount when used. Here, the nine types of quantization are performed by multiplying the input signal by 1, 1/2, 1/4, 1/8, or the like. The quantization controller 53 compares the cumulative addition value of the codewords subjected to the variable length coding with respect to the signal of 30 blocks after the quantization with a predetermined target value, and obtains the minimum quantization value Brn that does not exceed the target. Is output to the quantizer 54. The quantizer 54 performs quantization based on the quantization step value Brn supplied from the quantization controller 53. If the target value is exceeded even if the maximum quantization value is used (overflow), the maximum quantization value is output to the quantizer 54.

The variable-length encoder 55 performs variable-length encoding using a Huffman code in which a combination of the number of consecutive zero values of the input signal and the following value is assigned to a short bit length in order of occurrence probability. The components of each block are 3 to
It is variable-length coded into a 16-bit codeword. Each variable-length coded block includes a 9-bit DC value, a variable-length coded AC component, and an EOB indicating the end of the block.

The output signal of the compressor 56 is output to the formatter 5
7 and is divided into low frequency components and high frequency components and formatted. FIG. 5 shows a format of 30 blocks. When formatting 30 blocks, 3 syncs are formed. Sink 0 and Sink 1 are provided with ten 10-byte areas for each Y signal, and five five-byte areas for color difference signals of RY or BY signals. The signal output from the compressor 56 first has a D
The code words of components having lower frequencies are packed without gaps in code word units in order from the C component. In the case of a Y signal block, the blocks are packed until the total number of bits becomes 64 or more. In other words, writing is performed up to the maximum number of words in which a code word is not missing (the maximum code word length is 16 bits, so if the next code word is packed with 65 bits or more in the Y signal block,
There is a possibility of exceeding the 0-bit area. Therefore, when it is 65 or more, it is stopped. Similarly, in the case of a color difference signal block, the operation is stopped at 25 bits or more. ). This process is performed on the signals of 30 blocks. The signal packed in this processing is the LAC, and the signal that cannot be processed and overflows is the high-frequency signal HAC.

The formatter 57 packs each LAC of the 30-block signal into a predetermined position, and then stores the remaining HAC.
Is performed. This operation will be described with reference to FIG. If the EOB is not packed in the 10-byte or 5-byte area packed with the LAC, a free area of 0 to 16 bits exists. In this vacant area, H
Pack AC. At this time, the HAC generated in the first sink 0 is packed in the free area of the sink 0, and the HAC generated in the first sink is packed in the free area of the sink 1. Since the stuffing is performed so as to completely fill the empty area, the codeword may be divided in units of one bit at the worst and stuffed over many areas. When the HACs of the sinks 0 and 1 cannot be packed in the empty area of each sink,
Sink 2 is packed with the remaining HAC. After the sink 2 is filled with the HAC of the sink 0, the HAC of the sink 1 is packed. Here, since the quantization controller 53 exceeds the target value, when a signal compressed by the maximum quantization is input, all the HACs cannot be packed in the sink 2.
The remaining HAC and EOB are discarded. The packed HAC is packed, and the signal after the format processing is output to the first ECC unit 58. At the same time, T indicating the position of the boundary of the HAC between sink 0 and sink 1 at sink 2
An OP signal is also output. The first ECC unit 58 adds a double error correction code (ER0 and ER1) and various control signals (synchronization signals SYNC, ID, Brn, TOP, etc.) to the 81 syncs output from the formatter 57, and modulates them. Output to the container 59. Modulator 59 converts the input signal to 8/10
The signal is converted and output to the first amplifier 60. First amplifier 6
0 amplifies an input signal and supplies it to the first magnetic head 61 to record the signal on the tape 62. FIG. 7 shows the structure of a signal for one track recorded on a tape. One track is composed of 81 syncs (540 blocks for the Y signal, 135 blocks for the RY signal, and 135 blocks for the BY signal), so that one frame of the video signal is recorded on 10 tracks.

Next, the operation at the time of reproduction will be described. The signal reproduced by the second magnetic head 64 is supplied to the second amplifier 63
Is added to The signal amplified by the second amplifier 63 is
The signal is demodulated by the demodulator 65 and output to the second ECC unit 66. The second ECC unit 66 detects an error position using the error correction codes ER0 and ER1 added at the time of recording, corrects a position where the error can be corrected, and writes the corrected position into the first memory 67.
In this case, if there is a portion where even one bit cannot be corrected in the sync 0 and the sync 1 out of the three syncs, the first memory 6
7 is not written with the contents of the sink. Since the first memory 67 has a capacity of 810 syncs for one frame, when an uncorrectable error occurs in the recording / reproducing system, the signal of the sync at the same position one frame before is supplied to the deformatter 19. I do.

As shown in FIG. 2, of the three sinks, the sink 2
In the case of pattern 1 having an uncorrectable error, the second E
The CC unit 66 outputs the modification flag F2 to the deformatter 72 and stores the sync 0 and the sync 1 in the first memory 67.
Write the data of Pattern 1 with uncorrectable error in either sync 0 or sync 1 of 3 syncs
In the case of (2), the second ECC unit 66 outputs a modification flag F0 (when an error exists in the sink 0) or F1 (when an error exists in the sink 1) to the deformatter 72, and outputs an error-free sink. Write to the first memory 67. The second ECC unit 66 stores the 1 written in the first memory 67.
The frame (810 sync) signals are sequentially output to the deformatter 72. The deformatter 72 stores the signal output from the second ECC unit 66 in the second memory 68 in units of three syncs.

The operation of the deformatter 72 when the modification flag is not output from the second ECC unit 66 to the deformatter 72 (when all three syncs can be corrected) will be described. The code length detector 69 first detects the LACs of the sink 0 and the sink 1 one codeword at a time and outputs the codewords to the end flag inserter 70. The end flag inserter 70 uses this LA
C is stored in the third memory 71 as it is. The code length detector 69 accumulatively adds the word lengths of the codewords in the area allocated to one block of LAC, and when this value is a Y signal, 65,
In the case of the RY signal or the BY signal, when it becomes 25 or more, it is detected that the LAC has ended. Then, the remaining HACs of the sink 0, the sink 1, and the sink 2 are sequentially connected and output to the code length detector 69. In this case, the code length detector 69 detects that the code word of one block is completed by detecting the EOB. HA of each block
C and EOB are sent through the end flag inserter 70 to the third
In the same block as the LAC of the same block. FIG. 3A shows an example of the signal format of each block stored in the third memory 71. The code length detector 69 counts the total word number TC of 30 blocks and the number of detected EOBs simultaneously with the cumulative addition operation of the number of LAC code words of one block. Despite the TC exceeding the data value in the area of 3 syncs, the detected EO
If the number of B is 30 or less, it is determined that an overflow occurs in the quantization, and EOB is added to the currently processed HAC. Then, the EOB is also added to the LACs of the subsequent blocks, thereby preventing a malfunction of the variable length decoder 73.

The case where an error occurs in the sink 0 as in the pattern 2 in FIG. 2 and the modification flag F0 is input from the second ECC unit 66 to the defo-matter 72 will be described. The code length detector 69 first detects the LAC signals of sync 0 and sync 1 one codeword at a time, and outputs them to the end flag inserter 70. The end flag inserter 70 adds EOB to the end of the LAC of each block of the sink 0 and stores it in the third memory 71. The LAC of the sink 1 is stored in the third memory 71 as it is.
To memorize. Next, HA connected to each block of sink 1
Only C is read from the second memory 68 and the third memory 7
One LAC is stored in a coupled form. Since the sync 0 has an error, it has been replaced by the sync of the previous frame by the second ECC unit 66. Therefore, when the sink 0 is connected to the HAC of the sync 2, a malfunction occurs in the variable length decoder 73. The insertion of the EOB enables decoding of the variable length signal of the LAC of the sink 0. FIG. 3B shows an example of the signal format of each block stored in the third memory 71. As described above, even when there is an error in three syncs, half of the 15 blocks can be decoded without interpolating with the signal of the previous frame.

Next, a case where an error occurs in the sink 2 as in the pattern 1 in FIG. 2 and the modification flag F2 is input from the second ECC unit 66 to the deformatter 72 will be described. The code length detector 69 detects the LACs of the sink 0 and the sink 1 stored in the second memory 68 and outputs them to the end flag inserter 70. The end flag inserter 70 adds the last end flag of the LAC of each block and stores it in the third memory 71. At this time, the HAC of each sink is discarded. As described above, a signal of 30 blocks recorded by 3 syncs can be decoded into a variable length signal only by the LAC.

The signal stored in the third memory 71 is output to the variable length decoder 73. The variable length decoder 73 detects and decodes a codeword from the input signal. The output signal of the variable length decoder 73 is supplied to an inverse quantizer 74, where the output signal is multiplied by a reciprocal of quantization at the time of recording, and output to an IDCT unit 75. The IDCT unit 75 applies a two-dimensional ID to the input signal.
It performs a CT operation and outputs the result to the deshuffling unit 76. The deshuffling unit 76 converts the input signal into a Y signal, an RY signal,
The signals are rearranged into parallel signals of BY signals and output to the output terminal 77. Reference numeral 78 denotes a variable length decoder 73, an inverse quantizer 74, and an IDC
This is an expander including a T section 75 and a deshuffling section 76.

As described above, according to the present embodiment, the compressor (56) for compressing one or a plurality of blocks composed of m × n pixels using discrete cosine transform and variable length coding.
And, the compressed signal of each block output from the compressor is divided into a low frequency component divided by a predetermined data amount or less from a lower frequency component and a high frequency component exceeding the same, and both components are divided into different regions. A formatter (57) for formatting, an error corrector (58) for adding an error correction code to an output signal of the formatter, a recording / reproducing device (60-64) for recording and reproducing an output signal of the error correcting device, and a recording / reproducing device Error corrector (66) for inputting a signal reproduced from the error corrector and outputting a correction flag indicating an uncorrectable position from the added error correction code, and a signal output from the error corrector and a correction flag. A deformatter (72) for adding an end flag to the low-frequency component of each block based on the modification flag, and an output signal of the deformatter, By providing the decompressor (78), when an error occurs in three syncs, it is possible to decode a variable-length signal using only low-frequency components of each block recorded in a sink where no error occurs. By doing so, it is possible to reduce the interpolation using the information of the previous frame and to reduce the image quality deterioration.

In this embodiment, 30 blocks are replaced by 3
Although the format is divided into sinks, different values may be used.

[0029]

As described above, according to the present invention, when an error occurs in three syncs, it is possible to decode a variable-length signal using only the low-frequency component of each block recorded in the sink where no error has occurred. I do. As a result, it is possible to reduce the interpolation using the information of the previous frame and to reduce the image quality when the same portion of the screen can be reproduced only once in several frames, such as interpolation of a video signal with high motion or high-speed reproduction. It can be reduced, and the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an error state in the embodiment;

FIG. 3 is an explanatory diagram for explaining a deformatter operation in the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 5 is a schematic diagram for explaining a format of a video signal of the conventional example.

FIG. 6 is a schematic diagram showing a configuration of one block in the conventional example.

FIG. 7 is a schematic diagram showing a configuration of a signal recorded on one track in the conventional example.

[Explanation of symbols]

 Reference Signs List 50 input terminal 51 shuffling unit 52 DCT unit 53 quantization controller 54 quantizer 55 variable length encoder 56 compressor 57 formatter 58, 66 ECC unit 59 modulator 60, 63 amplifier 61, 64 magnetic head 67, 68 , 71 Memory 62 Tape 69 Code Length Detector 70 End Flag Inserter 72 Deformatter 73 Variable Length Decoder 74 Dequantizer 75 IDCT Unit 76 Deshuffling Unit 77 Output Terminal 78 Expander

Claims (2)

(57) [Claims] 1. A compressor for compressing one or more blocks composed of m × n pixels using discrete cosine transform and variable length coding, and a compressed signal of each block output from the compressor. Is divided into a low frequency component divided by a predetermined data amount or less from a lower frequency component and a high frequency component exceeding it, and a formatter that formats both components into different regions, and an error correction to an output signal of the formatter. An error corrector that adds a code, a recording / reproducing device that records and reproduces an output signal of the error corrector, and a signal that is reproduced from the recording / reproducing device is input and cannot be corrected from the added error correction code. An error corrector that outputs a modification flag indicating a position; a signal output from the error corrector and a modification flag are input; and a low-frequency component of each block is input based on the modification flag. A video signal processing device comprising: a deformatter for adding an end flag to a minute; and a decompressor that receives an output signal of the deformatter as input and decompresses the input signal. 2. An end signal is input to a (a + 1) -th block if the input signals of a blocks input to the deformatter include only b (a> b) end flags. The video signal processing device according to claim 1, wherein