JPH0525204B2 - - Google Patents
Info
- Publication number
- JPH0525204B2 JPH0525204B2 JP59253003A JP25300384A JPH0525204B2 JP H0525204 B2 JPH0525204 B2 JP H0525204B2 JP 59253003 A JP59253003 A JP 59253003A JP 25300384 A JP25300384 A JP 25300384A JP H0525204 B2 JPH0525204 B2 JP H0525204B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply terminal
- voltage
- external power
- vcc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920006395 saturated elastomer Polymers 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims 3
- 239000004065 semiconductor Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 230000001771 impaired effect Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
［発明の技術分野］
この発明は、例えば実行チヤンネル長が1μｍ
以下の高密度に微細化されたMOSトランジスタ
を含むMOS型半導体装置に関する。[Detailed description of the invention] [Technical field of the invention]
The present invention relates to a MOS semiconductor device including the following highly miniaturized MOS transistors.
［発明の技術的背景］
一般にMOSトランジスタを含むMOS型半導体
装置の発展には目覚ましいものがあり、1960年代
の後半では実効チヤンネル長が約10μｍのMOSト
ランジスタによる集積度が数十乃至数百素子のも
のが実現されている。さらに微細加工化、高集積
化が進み、近年では、実効チヤンネル長が1.5μｍ
程度で素子数も数十万素子のVLSIへと発展を続
け、さらには実効チヤンネル長が1μｍ以下の高
集積度MOSトランジスタによる、より高速で低
消費電力の半導体装置が実現されるようになつて
きた。[Technical Background of the Invention] In general, the development of MOS type semiconductor devices including MOS transistors has been remarkable, and in the latter half of the 1960s, the integration density of MOS transistors with an effective channel length of about 10 μm increased from several tens to hundreds of elements. things are being realized. Furthermore, with advances in microfabrication and high integration, in recent years the effective channel length has become 1.5μm.
The number of elements has continued to evolve into VLSI with hundreds of thousands of elements, and even higher speed and lower power consumption semiconductor devices have been realized using highly integrated MOS transistors with an effective channel length of 1 μm or less. Ta.
ところで、従来のMOS型半導体装置は、外部
供給電源で直接に内部機能回路を動作させてい
て、供給電源電圧も内部機能回路を構成する
MOSトランジスタの実効チヤンネル長の縮小と
共に低減されてきている。例えば、上記1.5μｍの
実効チヤンネル長のものでは、5V単一電源下で
動作させている。 By the way, in conventional MOS semiconductor devices, the internal functional circuits are operated directly by external power supply, and the supply power supply voltage also constitutes the internal functional circuits.
It has been reduced as the effective channel length of MOS transistors has been reduced. For example, the device with an effective channel length of 1.5 μm is operated under a single 5V power supply.
しかしながら、さらに微細化されたMOS素子
は、信頼性の面から考えて、従来と同一の電源電
圧下で動作させるのは困難である。何故ならば、
MOS素子中での電界が高まることにより高いエ
ネルギーを持つたキヤリアが酸化膜中に飛込み、
素子の信頼性を損うためである。このため、例え
ば5Vに標準化された外部電源電圧をチツプ内部
にて降下させ使用することが考えられている。 However, from the viewpoint of reliability, it is difficult to operate a further miniaturized MOS element under the same power supply voltage as before. because,
As the electric field in the MOS device increases, carriers with high energy jump into the oxide film.
This is because the reliability of the element is impaired. For this reason, it is being considered to use an external power supply voltage that is standardized to, for example, 5V and lower it inside the chip.
［背景技術の問題点］
しかしながら、微細化されたMOS型回路に低
電圧を供給するための従来の回路は、上記主回路
と同様にしてMOS型にて構成されているため、
主回路にて消費される全ての大電流は供給するこ
とが困難である。このため、小さな電流を消費す
る部分回路にのみ低電圧を供給し、大電流を消費
する回路へは着接外部からの電源電圧を供給する
という方法が取られている。このため、微細化さ
れた素子で構成され、且つ大電流を消費する
MOS型回路の場合には、外部から供給される電
源電圧を、標準の5Vより例えば3V程度の低電圧
まで降下させなければならず、電源コストが高く
なるという欠点がある。[Problems with the Background Art] However, since the conventional circuit for supplying low voltage to the miniaturized MOS type circuit is constructed of the MOS type in the same way as the main circuit described above,
All the large currents consumed in the main circuit are difficult to supply. For this reason, a method has been adopted in which a low voltage is supplied only to partial circuits that consume a small amount of current, and a power supply voltage from outside the bond is supplied to circuits that consume a large amount of current. Therefore, it is composed of miniaturized elements and consumes a large amount of current.
In the case of a MOS type circuit, the power supply voltage supplied from the outside must be lowered from the standard 5V to a lower voltage of, for example, 3V, which has the disadvantage of increasing the power supply cost.
［発明の目的］
本発明は上記の点に鑑みてなされたもので、例
えば大電流を消費する微細化素子で構成される場
合でも、標準化された高い外部電源電圧が直接供
給されることなく、低電圧にて信頼性の高い動作
が可能になるMOS型半導体装置を提供すること
を目的とする。[Object of the Invention] The present invention has been made in view of the above points. For example, even when configured with miniaturized elements that consume large currents, the present invention can be realized without being directly supplied with a standardized high external power supply voltage. The purpose of the present invention is to provide a MOS type semiconductor device that can operate with high reliability at low voltage.
［発明の概要］
すなわちこの発明に係わるMOS型半導体装置
は、MOS型主回路の内部電源端子に、同一基板
上に形成されたトランジスタのコレクタ電極また
はエミツタ電極を接続し、このトランジスタのベ
ース電極を上記内部電源端子の電位に応じてその
内部電源端子または外部電源端子に切換え接続
し、常に低電圧の駆動電圧を得るようにしたもの
である。[Summary of the Invention] That is, the MOS type semiconductor device according to the present invention connects the collector electrode or emitter electrode of a transistor formed on the same substrate to the internal power supply terminal of the MOS type main circuit, and connects the base electrode of this transistor to the internal power supply terminal of the MOS type main circuit. According to the potential of the internal power supply terminal, the connection is switched between the internal power supply terminal and the external power supply terminal, so that a low driving voltage is always obtained.
［発明の実施例］
以下図面を参照して本発明の一実施例を説明す
る。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.
第１図はその概略的な回路構成を示すもので、
このMOS型半導体装置はそれぞれ同一の半導体
チツプ上に形成されるMOS型主回路１１とその
電源回路１２とから構成される。ここでVccは高
電位側の外部電源端子、またVssは低電位側の外
部電源端子である。そして、Vsは上記MOS型主
回路１１の低電位側の内部電源端子であり、この
内部電源端子Vsを上記電源回路１２内のNPNト
ランジスタTrのコレクタ電極ｃに接続すると共
に、スイツチ回路SWの固定接点Ｂに接続する。
このスイツチ回路SWは、上記高電位側の外部電
源端子Vccと上記回路１１の内部電源端子Vsと
の電位差、所謂MOS回路駆動電圧（Vcc−Vs）
が、予め設定される所定の電圧Vcrより大きいか
否かに応じてスイツチング動作するもので、この
スイツチ回路SWの固定接点Ａには上記高電位側
の外部電源端子Vccを、また可動接点には上記ト
ランジスタTrのベース電極ｂを接続する。そし
て、このトランジスタTrのエミツタ電極ｅを上
記低電位側の外部電源端子Vssに接続する。ここ
で、上記スイツチ回路SWは、電位差（Vcc−
Vs）が上記所定の電圧Vcrより大きい場合に、
その接点Ｂを介してトランジスタTrのベース電
極ｂを上記MOS型主回路１１の内部電源端子Vs
に接続し、また電位差（Vcc−Vs）が上記所定
電圧Vcr以下の場合には、上記ベース電極ｂをそ
の接点Ａを介して高電位側の外部電源端子Vccに
接続する。 Figure 1 shows its schematic circuit configuration.
This MOS type semiconductor device is composed of a MOS type main circuit 11 and its power supply circuit 12, which are each formed on the same semiconductor chip. Here, Vcc is a high potential side external power supply terminal, and Vss is a low potential side external power supply terminal. Vs is an internal power supply terminal on the low potential side of the MOS type main circuit 11, and this internal power supply terminal Vs is connected to the collector electrode c of the NPN transistor Tr in the power supply circuit 12, and the switch circuit SW is fixed. Connect to contact B.
This switch circuit SW has a potential difference between the high potential side external power supply terminal Vcc and the internal power supply terminal Vs of the circuit 11, the so-called MOS circuit drive voltage (Vcc - Vs).
The switching operation is performed depending on whether or not the voltage is higher than a predetermined voltage Vcr set in advance.The fixed contact A of this switch circuit SW is connected to the high potential side external power supply terminal Vcc, and the movable contact is connected to the external power supply terminal Vcc on the high potential side. The base electrode b of the transistor Tr is connected. Then, the emitter electrode e of this transistor Tr is connected to the external power supply terminal Vss on the low potential side. Here, the switch circuit SW has a potential difference (Vcc-
Vs) is larger than the above predetermined voltage Vcr,
The base electrode b of the transistor Tr is connected to the internal power supply terminal Vs of the MOS type main circuit 11 through the contact B.
and when the potential difference (Vcc-Vs) is less than the predetermined voltage Vcr, the base electrode b is connected to the high potential side external power supply terminal Vcc via its contact A.
第２図は上記電源回路１２における電流電圧特
性を示すもので、Ic１，Ic２はそれぞれ外部電源
電圧Vccの異なるトランジスタTrのコレクタ電
流、またIm１，ｍ２はMOS回路電流である。
すなわち、例えば、予め設定される所定の電圧
Vcrを3V程度に設定すると、まず外部電源電圧
Vccが上記所定電圧Vcrより高い場合Vcc(H)には、
トランジスタTrはそのベース電極ｂがスイツチ
回路SWを介して内部電源端子Vsに接続されるこ
とにより非飽和動作し、上記Ic１・Im１の交点
Ｈに対応する内部電源電圧Vs１が与えられる。
つまり、上記MOS型主回路１１には、実際上
Vcc(H)−Vs１の低駆動電圧（この場合2.5V程度）
が供給されるようになる。これにより、外部電源
電圧Vccが高い場合でも、主回路１１の動作信頼
性が損われることはない。一方、外部電源電圧
Vccが上記所定電圧Vcr以下に低下した場合Vcc
(L)には、トランジスタTrは、そのベース電極ｂ
がスイツチ回路SWを介して高電位側の外部電源
端子Vccに接続されることにより飽和領域にて動
作し、コレクタ電極ｃの電位は略低電位側の外部
電源電圧Vssと同等になり、上記Ic２・Im２の交
点Ｌに対応する内部電源電圧Vs２（≒0V）が与
えられる。つまり、上記MOS型回路１１には、
上記Vcc(L)の低駆動電圧（この場合2.5〜3V程度）
がほとんどそのまま供給されるようになる。 FIG. 2 shows the current-voltage characteristics in the power supply circuit 12, where Ic1 and Ic2 are collector currents of transistors Tr having different external power supply voltages Vcc, and Im1 and m2 are MOS circuit currents.
That is, for example, a predetermined voltage that is set in advance
When Vcr is set to about 3V, first the external power supply voltage
When Vcc is higher than the above specified voltage Vcr, Vcc(H) is
The base electrode b of the transistor Tr is connected to the internal power supply terminal Vs via the switch circuit SW, so that the transistor Tr operates in a non-saturated state, and is supplied with the internal power supply voltage Vs1 corresponding to the intersection H of Ic1 and Im1.
In other words, the MOS type main circuit 11 actually has
Low driving voltage of Vcc(H)-Vs1 (about 2.5V in this case)
will be supplied. Thereby, even when the external power supply voltage Vcc is high, the operational reliability of the main circuit 11 is not impaired. On the other hand, external power supply voltage
When Vcc drops below the above specified voltage Vcr, Vcc
(L), the transistor Tr has its base electrode b
is connected to the external power supply terminal Vcc on the high potential side via the switch circuit SW, so that it operates in the saturation region, and the potential of the collector electrode c becomes approximately equal to the external power supply voltage Vss on the low potential side, and the above Ic2 - Internal power supply voltage Vs2 (≒0V) corresponding to the intersection L of Im2 is given. In other words, in the MOS type circuit 11,
Low driving voltage of Vcc(L) above (about 2.5 to 3V in this case)
will be supplied almost as is.
したがつて、第３図に、本実施例における外部
電源電圧Vccに対するMOS回路駆動電圧（Vcc
−Vs）の特性を実線にて示すように、外部電源
電圧Vccの変動に対する駆動電圧（Vcc−Vs）の
変動が充分に抑えられるようになり、外部電源電
圧Vccに対する動作マージンが増加すると共に、
微細化素子における信頼性の向上を図ることがで
きる。 Therefore, FIG. 3 shows the MOS circuit drive voltage (Vcc) with respect to the external power supply voltage Vcc in this embodiment.
-Vs) as shown by the solid line, the fluctuation of the drive voltage (Vcc - Vs) with respect to the fluctuation of the external power supply voltage Vcc is sufficiently suppressed, and the operating margin with respect to the external power supply voltage Vcc increases.
It is possible to improve the reliability of miniaturized elements.
第４図は上記第１図におけるスイツチ回路SW
を具体化した回路構成を示すもので、Ｑ１，Ｑ２
はそれぞれＰチヤンネルおよびＮチヤネルの
MOSトランジスタ、またＲ１，Ｒ２は抵抗素子
である。この場合、上記抵抗素子Ｒ１，Ｒ２は例
えばMOSトランジスタないしはポリシリコン抵
抗等で形成される。このようなスイツチ回路SW
において、まずVcc−Vs間の電位が高い場合に
は、トランジスタＱ１がONすることによりその
コンダクタンスは抵抗Ｒ１のそれよりも大きくな
り、点Ａの電位は略Vccに近い高電位レベルＨに
設定される。これによりトランジスタＱ２がON
となり、トランジスタTrのベース電極ｂには主
としてこのMOSトランジスタＱ２を介して電流
が供給される。このため、トラジスタTrのコレ
クタ電位は、そのベース電位に等しいかあるいは
より高い電位となり、内部電源端子Vsの端子電
圧は大きくなる。すなわち、MOS型主回路１１
の駆動電圧（Vcc−Vs）は、低電圧に抑えられ
るようになる。一方、Vcc−Vs間の電位が上記
所定電圧Vcr以下である場合には、トランジスタ
Ｑ１がOFFすることによりそのコンダクタンス
は抵抗Ｒ１のそれよりも小さくなり、点Ａの電位
は略Vsに近い低電位レベルＬに設定される。こ
れによりトランジスタＱ２はOFFとなり、トラ
ンジスタTrのベース電流は抵抗Ｒ２を介して高
電位側の外部電源端子Vccより供給される。ここ
で、抵抗Ｒ２の抵抗値は、電位差（Vcc−Vs）
の値が所定電圧Vcrに等しくなり、MOS回路１
１の消費電流がコレクタ電流として供給された時
に、上記NPNトランジスタが飽和領域で動作す
るに充分なベース電流を供給できるように設定す
ればよい。この場合、MOS型主回路１１の駆動
電圧（Vcc−Vs）は、低い外部電源電圧Vccと略
同等になる。 Figure 4 shows the switch circuit SW in Figure 1 above.
This shows the circuit configuration that embodies Q1, Q2
are for P channel and N channel respectively.
The MOS transistor and R1 and R2 are resistance elements. In this case, the resistive elements R1 and R2 are formed of, for example, MOS transistors or polysilicon resistors. Such a switch circuit SW
First, when the potential between Vcc and Vs is high, transistor Q1 turns on and its conductance becomes larger than that of resistor R1, and the potential at point A is set to a high potential level H, which is approximately close to Vcc. Ru. This turns transistor Q2 on.
Therefore, current is supplied to the base electrode b of the transistor Tr mainly through this MOS transistor Q2. Therefore, the collector potential of the transistor Tr becomes equal to or higher than its base potential, and the terminal voltage of the internal power supply terminal Vs increases. That is, the MOS type main circuit 11
The driving voltage (Vcc-Vs) of the device can be suppressed to a low voltage. On the other hand, when the potential between Vcc and Vs is below the predetermined voltage Vcr, the conductance of transistor Q1 becomes smaller than that of resistor R1 by turning off transistor Q1, and the potential of point A becomes a low potential approximately close to Vs. It is set to level L. This turns off the transistor Q2, and the base current of the transistor Tr is supplied from the high potential side external power supply terminal Vcc via the resistor R2. Here, the resistance value of resistor R2 is the potential difference (Vcc - Vs)
becomes equal to the predetermined voltage Vcr, and MOS circuit 1
The setting may be made such that when a consumption current of 1 is supplied as a collector current, a base current sufficient for the NPN transistor to operate in the saturation region can be supplied. In this case, the driving voltage (Vcc-Vs) of the MOS type main circuit 11 becomes approximately equal to the low external power supply voltage Vcc.
次に、第５図は前記スイツチ回路SWの他の実
施例を示すもので、まずVcc−Vs間の電位が所
定電圧Vcrより高い場合には、トランジスタＱ４
がONすることによりそのコンダクタンスはＱ３
のそれよりも大きくなり、点Ａの電位は略Vsに
近い低電位レベルＬに設定される。これによりイ
ンバータＧの出力電位が略Vccに近い高電位レベ
ルＨとなつてトランジスタＱ２がON、Ｑ１が
OFFとなり、トランジスタTrにはベース電流が
上記Ｑ２を介して供給された非飽和動作となる。
一方、Vcc−Vs間の電位が上記所定電圧Vcr以下
である場合には、トランジスタＱ３がONするこ
とによりそのコンダクタンスはトランジスタＱ４
のそれよりも大きくなり、点Ａの電位は略Vccに
近い高電位レベルＨに設定される。これによりイ
ンバータＧの出力電位が略Vsに近い低電位レベ
ルＬとなつてトランジスタＱ１がON、Ｑ２が
OFFとなる。ここで、MOSトランジスタＱ１の
コンダクタタンスを、トランジスタTrが飽和動
作するに充分なだけのベース電流を供給できるよ
うに設定すれば、内部電源端子Vsの端子電圧は
略Vssと同等になり、MOS型主回路１１には、
上記所定電圧Vcrより低い外部電源電圧Vccが駆
動電圧として供給されるようになる。 Next, FIG. 5 shows another embodiment of the switch circuit SW. First, when the potential between Vcc and Vs is higher than the predetermined voltage Vcr, the transistor Q4
When it turns on, its conductance becomes Q3
, and the potential at point A is set to a low potential level L approximately close to Vs. As a result, the output potential of inverter G becomes a high potential level H approximately close to Vcc, transistor Q2 is turned on, and Q1 is turned on.
The transistor Tr is turned off, and the base current is supplied to the transistor Tr via the Q2, resulting in a non-saturated operation.
On the other hand, when the potential between Vcc and Vs is below the predetermined voltage Vcr, transistor Q3 turns on and its conductance changes to transistor Q4.
, and the potential at point A is set to a high potential level H approximately close to Vcc. As a result, the output potential of inverter G becomes a low potential level L close to Vs, transistor Q1 is turned on, and Q2 is turned on.
It becomes OFF. Here, if the conductance of the MOS transistor Q1 is set to supply enough base current for the transistor Tr to operate in saturation, the terminal voltage of the internal power supply terminal Vs will be approximately equal to Vss, and the MOS transistor In the main circuit 11,
An external power supply voltage Vcc lower than the predetermined voltage Vcr is supplied as a drive voltage.
尚、上記実施例では述べていないが、電源回路
１２はMOS型主回路１１の高電位側に接続する
等の応用構成も可能である。また、上記各回路に
はPNP型のバイポーラントランジスタを用いて
も構成可能であることはいうまでもない。 Although not described in the above embodiment, an applied configuration such as connecting the power supply circuit 12 to the high potential side of the MOS type main circuit 11 is also possible. Furthermore, it goes without saying that each of the above circuits can also be constructed using PNP type bipolar transistors.
［発明の効果］
以上のようにこの発明によれば、MOS型主回
路の内部電源端子に、同一基板上に形成されたト
ランジスタのコレクタ電極またはエミツタ電極を
接続し、このトランジスタのベース電極を上記内
部電源端子の電位に応じてその内部電源端子また
は外部電源端子に切換え接続し、常に低電圧の駆
動電圧が得られるようにしたので、例えば大電流
を消費する微細化素子で構成される場合でも、標
準化された高い外部電源電圧が直接供給されるこ
となく、常に低電圧にて信頼性の高い動作が可能
になるMOS型半導体装置を提供できる。[Effects of the Invention] As described above, according to the present invention, the collector electrode or emitter electrode of a transistor formed on the same substrate is connected to the internal power supply terminal of the MOS type main circuit, and the base electrode of this transistor is connected to the internal power supply terminal of the MOS type main circuit. Depending on the potential of the internal power supply terminal, the connection is switched between the internal power supply terminal or the external power supply terminal, so that a low drive voltage can always be obtained, so even when configured with miniaturized elements that consume large currents, for example. Therefore, it is possible to provide a MOS type semiconductor device that can always operate with high reliability at a low voltage without being directly supplied with a standardized high external power supply voltage.
第１図はこの発明の一実施例に係わるMOS型
半導体装置を示す概略的構成図、第２図は上記
MOS型半導体装置における電源回路の電流電圧
特性を示す図、第３図は上記MOS型半導体装置
の外部電源電圧に対するMOS回路駆動電圧の変
動特性を示す図、第４図は上記MOS型半導体装
置におけるスイツチ回路を具体化して示す回路構
成図、第５図は上記第４図におけるスイツチ回路
の他の実施例を示す図である。
１１……MOS型主回路、１２……電源回路、
Vcc，Vss……外部電源端子、Vs……内部電源端
子、Tr……トランジスタ、SW……スイツチ回
路。
FIG. 1 is a schematic configuration diagram showing a MOS type semiconductor device according to an embodiment of the present invention, and FIG. 2 is the above-mentioned
FIG. 3 is a diagram showing the current-voltage characteristics of the power supply circuit in the MOS semiconductor device. FIG. 3 is a diagram showing the fluctuation characteristics of the MOS circuit drive voltage with respect to the external power supply voltage of the MOS semiconductor device. FIG. FIG. 5 is a circuit configuration diagram showing a concrete example of the switch circuit. FIG. 5 is a diagram showing another embodiment of the switch circuit in FIG. 4. 11...MOS type main circuit, 12...power supply circuit,
Vcc, Vss...external power supply terminal, Vs...internal power supply terminal, Tr...transistor, SW...switch circuit.
Claims (1)
源端子と、 MOS型主回路の駆動電圧が設定される内部電
源端子と、 この内部電源端子と他方の外部電源端子との間
にそのコレクタ電極とエミツタ電極とが接続され
て介在される上記MOS型主回路と同一基板上に
形成される降圧用トランジスタと、 上記一方の外部電源端子と内部電源端子との端
子間電圧で駆動されその電位差が所定値より大き
いか否かを検出する電位差検出回路と、 この電位差検出回路からの出力信号により駆動
され、上記一方の外部電源端子と内部電源端子と
の間の電位差が所定値より大きい場合には上記降
圧用トランジスタが非飽和動作するようそのベー
ス電極を上記内部電源端子に接続し、上記電位差
が所定値以下の場合には上記降圧用トランジスタ
が飽和動作をするようそのベース電極を上記一方
の外部電源端子に接続するスイツチ回路とを具備
したことを特徴とするMOS型半導体装置。[Claims] 1. One external power supply terminal to which a power supply voltage is supplied from the outside, an internal power supply terminal to which the driving voltage of the MOS type main circuit is set, and a connection between this internal power supply terminal and the other external power supply terminal. A step-down transistor formed on the same substrate as the MOS type main circuit whose collector electrode and emitter electrode are connected in between, and the voltage between the one external power supply terminal and the internal power supply terminal. a potential difference detection circuit that is driven and detects whether or not the potential difference is larger than a predetermined value; and a potential difference detection circuit that is driven by an output signal from this potential difference detection circuit so that the potential difference between the one external power supply terminal and the internal power supply terminal is a predetermined value. If the potential difference is less than a predetermined value, the base electrode of the step-down transistor is connected to the internal power supply terminal so that the step-down transistor operates in a non-saturated manner. and a switch circuit for connecting the terminal to one of the external power supply terminals.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59253003A JPS61131555A (en) | 1984-11-30 | 1984-11-30 | Mos type semiconductor device |
| US06/800,301 US4698789A (en) | 1984-11-30 | 1985-11-21 | MOS semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59253003A JPS61131555A (en) | 1984-11-30 | 1984-11-30 | Mos type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61131555A JPS61131555A (en) | 1986-06-19 |
| JPH0525204B2 true JPH0525204B2 (en) | 1993-04-12 |
Family
ID=17245133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59253003A Granted JPS61131555A (en) | 1984-11-30 | 1984-11-30 | Mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61131555A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163849A (en) * | 1983-03-08 | 1984-09-14 | Toshiba Corp | Semiconductor integrated circuit |
-
1984
- 1984-11-30 JP JP59253003A patent/JPS61131555A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59163849A (en) * | 1983-03-08 | 1984-09-14 | Toshiba Corp | Semiconductor integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61131555A (en) | 1986-06-19 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |