JPH05252038A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain an A/D converter whose A/D conversion accuracy is made high with low power consumption and high speed processing. CONSTITUTION:A 1st constant current source Iin supplying a current proportional to an input current (2nd constant current sources IR0-IR3) is connected in series with a resistor R1 (R2). A 1st switch S (2nd switches SR0-SR3) is connected in series with each current source. Moreover, the A/D converter is provided with a comparator section 3 comparing voltage drops of the resistors R1 and R2 and a logic section 4 controlling the 2nd switches SR0-SR3 based on an output of the comparator section 3. The A/D conversion is executed by comparing an input current and a comparison current in this way. In this case, since the circuit is configured so that the current depends only on the relative accuracy of components, the effect of parasitic elements is not caused.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter (hereinafter referred to as an A / D converter) for converting an analog input current into a digital output.

[0002]

2. Description of the Related Art There are various types of conventional A / D converters, and among them are current comparison type A / D converters.

FIG. 5 is a circuit diagram of an A / D converter showing such a conventional example. As shown in FIG. 5, in the conventional A / D converter, the voltage drop I _D × R _in due to the output current I _D of the D / A converter composed of the R-2R resistance ladder becomes equal to the input voltage V _in. A / D conversion is performed by finding a suitable combination. This D / A converter is R-
The reference current I _R is sequentially halved from the left by the 2R resistor ladder.
Each of the switches S _{0 to} S corresponding to each bit of the digital code to form a binary weighted current source.
By connecting ₇ to the output terminal side, the analog current _ID corresponding to the digital code is output. This current I
_{If D} is greater than V _in / R, the switch switches to decrease the current, and if current I _D is less than V _in / R, the switch switches to increase the current. In the determination of the magnitude, the input of the comparison unit 6 is negative if the current I _D is larger than V _in / R, and the input of the comparison unit 6 is positive if the current I _D is smaller than V _in / R. This is performed by determining whether the input of the unit 6 is positive or negative. As a result, if the currents I _D and V _in / R become equal, the digital code to be input to the D / A converter at that time should be A
This is the output code that has been D / D converted.

[0004]

DISCLOSURE OF THE INVENTION The above-mentioned conventional A / D
The converter uses an R-2R resistor ladder to obtain a binary weighted current source for use in a D / A converter. Therefore, the accuracy of the current source is governed by the degree of coincidence of the resistance values. However, due to the parasitic resistance of the bipolar transistor and the parasitic resistance of the switch, even if the resistances themselves have the same value, the circuit resistance values do not match. As a result, the accuracy of the D / A converter deteriorates, so that the accuracy of the A / D conversion deteriorates. Further, the conventional A / D converter has a drawback that it consumes a large amount of current and is difficult to operate at high speed.

An object of the present invention is to provide an A / D converter which can improve the conversion accuracy, reduce the current consumption, and increase the speed.

[0006]

An A / D converter according to the present invention comprises first and second resistive loads each having one end connected to a first constant voltage source, and the other end of the first resistive load. And the second
A first switch connected in series with the constant voltage source and a first constant current source for supplying a current proportional to the input current,
N sets of binary weighted second constant current sources connected in parallel between the other end of the second resistive load and the second constant voltage source and the second constant current source. N sets of second switches, each connected in series, and the first and second switches.
Comparing the potentials of the other ends of the resistance loads, the comparison unit that outputs the result of determining the magnitude relationship and the logic unit that controls the opening and closing of the N sets of the second switches according to the result of the comparison unit are included. The first and second constant current sources are composed of a current mirror circuit composed of MOS transistors.

In the A / D converter of the present invention, the first and second resistance loads each having one end connected to the first constant voltage source, the other end of the first resistance load, and the second resistance load. A first switch connected in series with a constant voltage source and a first constant current source for flowing a current proportional to an input current, the other end of the second resistive load and the second constant voltage source The second switch connected in series between and and a second constant current source for flowing a comparison current, and the potentials at the other ends of the first and second resistive loads are compared to determine the magnitude relationship. A comparator is configured with a comparison unit that outputs a result, and 2 ^N (N is A / D conversion resolution) number of the comparators are connected in parallel, and the second constants that flow respective comparison currents of the comparators. The current of the current source is constructed in proportion to the digital value.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of an A / D converter showing an embodiment of the present invention. As shown in FIG. 1, this embodiment shows a circuit of a 4-bit A / D converter, which includes resistive loads R ₁ and R ₂ each having one end connected to a first constant voltage source 1 and the resistors R ₁ and R _2. A first switch S composed of MOS transistors connected to points A and B, which are the other ends of ₁ and R ₂ , respectively, and a plurality of second switches S _{R0 to} S _R0 connected in parallel.
_R3 and these first switch S and second switch S
_A first constant current source I _in connected between the other end of _{R0 to} S _R3 and the second constant voltage source 2 and a binary weighted second constant current source I _{R0 to} I _R3 , and A , A comparison unit 3 for comparing the potentials at points B, and a second switch S _{R0 to} S _R3 based on the comparison result.
And a logic unit 4 for controlling Further, although a current proportional to the input current flows through the resistor R1, a current I _in equal to the input current flows for simplicity of explanation. Moreover, the binary-weighted constant current sources I _R3 , I _R2 , I _R1 ,
I _R0 current values are I _R / 2, I _R / 4, I _R /
8, I _R / 16. Further, the resistors R ₁ and R _{2 have} the same value, and the value is R.

FIGS. 2 (a) to 2 (c) are three types of configuration diagrams of the first constant current source shown in FIG. 1, respectively. 2A shows a circuit composed of a current mirror composed of MOS transistors, FIG. 2B shows a structure in which current mirrors are vertically stacked in two stages, and FIG. 2C shows an active feedback type grounded gate circuit. Is used for the output side of the current mirror circuit. Each of FIGS. 2 (a) to 2 (c)
The ratio of the current flowing through the MOS transistor M1 connected to the input terminal IN and the current flowing through the MOS transistor M2 connected to the output terminal OUT is the ratio W1 / L of the channel width W1 and the channel length L1 of the transistor M1.
1 and the ratio W2 / L2 of the channel width W2 and the channel length L2 of the transistor M2 (W1 / L1) /
It is proportional to (W2 / L2). Therefore, by making the element sizes of the transistors M1 and M2 equal, a current having the same magnitude as the input current can be taken out from the output terminal OUT. Note that BI in FIG. 2C is a bias current terminal.

FIG. 3 is a block diagram of the binary weighted second constant current source shown in FIG. As shown in FIG. 3, this second constant current source uses the reference current I _R instead of the input current I _in of FIG. 2 described above, and sets the ratio of the element size of the transistor to a required value. A configuration similar to that of FIG. 2 can be realized. That is, in the configuration example of the 4-bit A / D converter, the MOS transistors M _R , M _R3 , M _R2 ,
The ratio of the element sizes of M _R1 and M _R0 is 1: 1/2: 1/4: 1
/ 8: It may be set to 1/16.

The circuit operation of the A / D converter shown in FIG. 1 will be described below. Since the resistors R ₁ through current I _in the same size as the input current, the voltage drop across the resistor R ₁ R × I _in
, And the potential V _A of the contact A is when the first power supply voltage to V _DD, a _{V A = V DD -R × I} in. First, in the first step of A / D conversion, the switch S _R3 is turned on and the switch S _R3 is turned on.
To turn off the _R2 ~S _R0. In this case, the resistor R ₂ I _R /
A current of 2 flows, and the voltage drop becomes R × (I _R / 2).
Therefore, the potential V _{B of the} contact B becomes V _DD −R × (I _R / 2). The comparison unit 3 compares this V _A and V _B to obtain V _A <V _B
If so, the most significant bit D ₃ becomes “1”, and V _A > V _B
Then, D ₃ becomes “0”. Also, the first switch S
Remains on if the D ₃ is "1", D ₃ is "
If it is 0 ", it is turned off. Next, in the second step, the switch S _R2 is turned on, and D ₃ is set to" 1 "to the resistance R _2.
1, "electric current of _{(I R / 2 + I R} / 4), D
₃ electric current of If _{"0" (I R / 4} ). Here, the potentials V _A and V _B at points A and B are again compared to obtain the second higher-order bit. After that, the same switch is repeatedly turned on and off to find a combination of switches so that the currents flowing through the resistors R ₁ and R ₂ become equal to each other.
Obtain the bit A / D conversion result. When this conversion is N bits, I ₂ = {D _N-1 × (I _R / 2) + D _N-2 × (I _R / 4) + D _N-3 × (I _R / 8) + … + D ₀ × (I _R / 2 ^N )} is equal to the input current I _in Digital code D _N-1 ·
D _N-2 , D _N-3 ... D ₁ , D ₀ are the output results of the A / D converter.

In such an A / D converter, the accuracy is determined by the accuracy of the resistors R1 and R2 and the accuracy of the element size of the transistor. If the element size ratio of the transistors is determined by parallel connection of transistors that are unit sizes, the accuracy can be relatively accurate, so that the structure can be accurately configured. Moreover, since the parasitic resistance of the switch is evenly applied to each circuit, the relative accuracy does not deteriorate, and the high accuracy A /
Enable D conversion. Further, even during the A / D conversion, the switch is turned off in an unnecessary circuit, so that current does not flow and power consumption can be reduced.

FIG. 4 is a circuit diagram of an A / D converter showing another embodiment of the present invention. As shown in FIG. 4, in the present embodiment, the input current and the comparison current are compared by the same principle as in the above-described embodiment, and A / D conversion is executed. This embodiment and the resistive load R _1, R _2, and these resistance load R _1, the first switch S1 and the first constant current source I _in which each of R ₂ are connected in series, and a second switch S2 The second constant current source (for example, I _r0 ) and the comparator 5 constitute one comparator, and 16 comparators are connected in parallel. Hereinafter, these 16 pieces will be referred to as N.

As described above, in executing the A / D conversion, 2 ^N comparators including the comparison unit 5 are prepared and the respective comparison currents are set to current values proportional to the digital values. That is, while the above-described one embodiment requires N steps to determine N bits, in the present embodiment, A / D conversion can be executed in one step, and high-speed A / D conversion is possible. Can be realized. Further, if the switch in each comparator is turned off, the comparison current will not flow, so that the power consumption can be reduced by allowing the current to flow only when necessary.

In the present embodiment, although faster conversion can be executed as compared with the above-mentioned one embodiment, either one may be selected depending on the hardware amount.

[0016]

As described above, the A / D converter of the present invention can not only realize high-precision A / D conversion that is not affected by parasitic resistance, but can also reduce current consumption.
It has the effect of speeding up.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an A / D converter showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of three types of first constant current sources shown in FIG.

3 is a block diagram of the binary weighted second constant current source shown in FIG. 1. FIG.

FIG. 4 is a circuit diagram of an A / D converter showing another embodiment of the present invention.

FIG. 5 is a circuit diagram of an A / D converter showing a conventional example.

[Explanation of symbols]

1 first constant voltage source 2 the second constant voltage source 3,5 comparator unit 4 logic R ₁ first resistive load R ₂ second resistive load S, S1 first switch S _R0 ~S _R3, S2 Second switch I _in First constant current source I _{R0 to} I _R3 , I _{r0 to} I _r15 Second constant current source IN input terminal OUT output terminal M1, M2, M _R , M _{R0 to} M _R3 MOS transistor BI Bias current terminal

Claims (2)

[Claims] 1. A first constant voltage source, first and second resistance loads each having one end connected thereto, and a series connection between the other end of the first resistance load and the second constant voltage source. Connected in parallel between the first switch and the first constant current source for flowing a current proportional to the input current, and the other end of the second resistive load and the second constant voltage source. A set of binary weighted second constant current sources and N sets of second switches each connected in series to the second constant current source;
And a comparison unit that outputs a result of comparing the potentials of the other ends of the second resistive loads to determine the magnitude relationship, and a logic unit that controls opening and closing of the N sets of second switches according to the result of the comparison unit. And has the first and second constant current sources MO
An analog / digital converter comprising a current mirror circuit including an S transistor. 2. A first constant voltage source, one end of which is connected to each of the first and second resistance loads, and a second constant voltage source connected in series between the other end of the first resistance load and the second constant voltage source. A first constant current source that supplies a current proportional to the input first switch and an input current, and a first constant current source connected in series between the other end of the second resistive load and the second constant voltage source. A second comparator and a second constant current source for flowing a comparison current, and a comparator for comparing the electric potentials of the other ends of the first and second resistive loads to determine the magnitude relationship and output the result. And connecting 2 ^N (N is A / D conversion resolution) of the above-mentioned comparators in parallel, and making the current of the second constant current source for flowing each comparison current of the above-mentioned comparator proportional to the digital value. The characteristic analog / digital converter.