JPH05251837A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH05251837A
JPH05251837A JP4409391A JP4409391A JPH05251837A JP H05251837 A JPH05251837 A JP H05251837A JP 4409391 A JP4409391 A JP 4409391A JP 4409391 A JP4409391 A JP 4409391A JP H05251837 A JPH05251837 A JP H05251837A
Authority
JP
Japan
Prior art keywords
layer
glass
glass layer
peripheral edge
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4409391A
Other languages
Japanese (ja)
Inventor
Tokio Ogoshi
時夫 大越
Yukio Nagano
幸雄 永野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokuyama Corp
Original Assignee
Tokuyama Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokuyama Corp filed Critical Tokuyama Corp
Priority to JP4409391A priority Critical patent/JPH05251837A/en
Publication of JPH05251837A publication Critical patent/JPH05251837A/en
Pending legal-status Critical Current

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  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

PURPOSE:To prevent the generation of a crack and a cutaway in the peripheral edge of a glass insulating layer by a method wherein the crystalline glass layer is formed on the side more inner than the peripheral edge of an amorphous glass layer. CONSTITUTION:An amorphous glass layer 2 and a crystalline glass layer 3 are formed in order on the surface of a metal substrate 1. At this time, the layer 3 is formed in such a way that it is formed on the side more inner than the peripheral edge of the layer 2. By such a way, the generation of a crack and a cutaway in the peripheral edge part of the layer 3, which are caused by a heat history due to heating at the time of formation of the layer 3 on the layer 2 or heating and cooling in the forming process of a conductor layer subsequent to the formation of the layer 3, can be effectively prevented. Moreover, it is desirable that the distances (d and d') between the peripheral edge of the layer 2 and the peripheral edge of the layer 3 are apart by 50mum or above, preferably 100mum or above.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は金属基板表面をガラス絶
縁層で被覆した新規な回路基板に関する。詳しくは、金
属基板表面に形成されるガラス絶縁層の耐クラック性に
対する信頼性が極めて高い回路基板である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel circuit board whose surface is covered with a glass insulating layer. Specifically, it is a circuit board having extremely high reliability with respect to crack resistance of the glass insulating layer formed on the surface of the metal substrate.

【0002】[0002]

【従来の技術】セラミック基板を使用した回路基板の機
械的、物理的強度を改良する目的で、鉄,アルミニウム
等の金属基板が使用されることがある。
2. Description of the Related Art Metallic substrates such as iron and aluminum are sometimes used for the purpose of improving the mechanical and physical strength of a circuit substrate using a ceramic substrate.

【0003】上記金属基板を使用した回路基板は、その
表面への配線パターンの形成に際し、配線パターン間の
短絡を防ぐ為、金属基板上にガラス絶縁層が一般に設け
られる。例えば、特公昭62−269396号には、ア
ルミニウムを含有する鉄合金基体の表面にガラス絶縁層
を形成した回路基板が示されている。
A circuit board using the above-mentioned metal substrate is generally provided with a glass insulating layer on the metal substrate in order to prevent a short circuit between the wiring patterns when forming a wiring pattern on the surface thereof. For example, Japanese Patent Publication No. 269396/1987 discloses a circuit board having a glass insulating layer formed on the surface of an iron alloy substrate containing aluminum.

【0004】ところが、金属基体上にガラス絶縁層を構
成した従来の回路基板は、例えば絶縁層として、SiO
2 を主成分とした非晶質ガラスを使用した場合、該ガラ
ス絶縁層の表面に配線パターンを形成後、該パターン上
に更に絶縁層、配線パターンなどを積層する際の加熱に
より、ガラス層が溶融し易いために高密度配線には適さ
ない。また、配線パターンとガラス絶縁層との接着性評
価としてのビーリング強度試験法の結果においても接着
強度が弱いという欠点がある。
However, in a conventional circuit board in which a glass insulating layer is formed on a metal substrate, for example, the insulating layer is made of SiO.
When an amorphous glass containing 2 as a main component is used, the glass layer is formed by heating a wiring pattern formed on the surface of the glass insulating layer and then laminating an insulating layer, a wiring pattern, etc. on the pattern. It is not suitable for high-density wiring because it melts easily. Further, the result of the beeling strength test method for evaluating the adhesiveness between the wiring pattern and the glass insulating layer has a drawback that the adhesive strength is weak.

【0005】本発明者は、金属基体上に設けるガラス絶
縁層に金属基板と接する面を非晶質ガラスにより形成
し、該非晶質ガラス層に他方の面を結晶質ガラスを積層
することにより、温度変化に対する耐クラック性、導体
の密着性等に優れ、且つ配線パターンの信頼性の高い回
路基板を提案した。
The inventor of the present invention forms a surface of a glass insulating layer provided on a metal substrate in contact with the metal substrate with amorphous glass, and stacks the other surface of the amorphous glass layer with crystalline glass, We have proposed a circuit board with excellent crack resistance against temperature changes, adhesion of conductors, etc., and a highly reliable wiring pattern.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、上記の
回路基板は、非晶質ガラス層の上部に形成した結晶質ガ
ラスの厚さを厚くした場合、該結晶質ガラス層の形成
時、更には該結晶質ガラス層の表面への配線パターン等
の形成時の加熱により、形成する絶縁ガラス周縁にクラ
ックあるいはクラックによるガラスの欠落を生じ、配線
パターンに致命的な損傷を与える欠点があった。即ち、
金属を導体から絶縁する意味でのガラス絶縁層の厚さ
は、その上部に形成される配線パターン等の導体層と金
属基板との間の絶縁層を支配し、上記回路基板において
は、十分な絶縁性を維持するために、結晶質ガラスを概
ね20〜30μmの厚みで形成することが必要となる場
合がある。しかし、かかる厚みを有する結晶質ガラス層
の形成を非晶質ガラス層の全面を完全に覆うように積層
した場合、形成された2層構造のガラス絶縁層の周縁に
クラックが容易に生じてしまうことがわかった。また、
この現象はガラス絶縁層形成後の導体、抵抗体形成にお
ける室温から高温(800〜1000℃)にわたる熱工
程に曝された場合でも発生する。さらに導体層を2層必
要とする回路基板の作製では結晶質ガラス層は更に厚く
する必要があり、その周縁部でのクラックの発生は免れ
ない。
However, in the above-mentioned circuit board, when the thickness of the crystalline glass formed on the upper portion of the amorphous glass layer is increased, when the crystalline glass layer is formed, The heating at the time of forming a wiring pattern or the like on the surface of the crystalline glass layer has a drawback that cracks or glass loss due to the cracks occurs at the peripheral edge of the insulating glass to be formed, and the wiring pattern is fatally damaged. That is,
The thickness of the glass insulating layer in the sense of insulating the metal from the conductor governs the insulating layer between the conductor layer such as the wiring pattern formed on the metal layer and the metal substrate, and in the above circuit board, is sufficient. In order to maintain the insulating property, it may be necessary to form the crystalline glass with a thickness of approximately 20 to 30 μm. However, when the crystalline glass layer having such a thickness is formed so as to completely cover the entire surface of the amorphous glass layer, cracks easily occur at the periphery of the formed glass insulating layer having a two-layer structure. I understood it. Also,
This phenomenon occurs even when exposed to a heating step from room temperature to high temperature (800 to 1000 ° C.) in forming the conductor and resistor after forming the glass insulating layer. Furthermore, in the production of a circuit board that requires two conductor layers, the crystalline glass layer needs to be made thicker, and cracks are inevitable at the peripheral edge thereof.

【0007】[0007]

【課題を解決するための手段】本発明者等は、金属基板
を非晶質ガラス層及び結晶質ガラス層よりなるガラス絶
縁層で被覆した回路基板における上記問題点を解消すべ
く鋭意検討を重ねた。その結果、非晶質ガラス層上部に
積層される結晶質ガラス層を該非結晶質ガラス層の周縁
より内側に形成することによりガラス絶縁層の周縁にお
けるクラック・欠落を防止できることを見出し、本発明
を完成するに至った。
DISCLOSURE OF THE INVENTION The inventors of the present invention have conducted extensive studies to solve the above problems in a circuit board in which a metal substrate is covered with a glass insulating layer composed of an amorphous glass layer and a crystalline glass layer. It was As a result, it was found that by forming a crystalline glass layer laminated on the upper portion of the amorphous glass layer on the inner side of the peripheral edge of the amorphous glass layer, cracks / missing at the peripheral edge of the glass insulating layer can be prevented, and the present invention is achieved. It came to completion.

【0008】以下、本発明を添付図面に従って具体的に
説明するが、本発明はこれらの図面に限定されるもので
はない。図1は、本発明の回路基板の代表的な態様を示
す平面図であり、図2はその側面図である。
The present invention will be specifically described below with reference to the accompanying drawings, but the present invention is not limited to these drawings. FIG. 1 is a plan view showing a typical aspect of the circuit board of the present invention, and FIG. 2 is a side view thereof.

【0009】本発明の回路基板は、金属基板1の表面に
非晶質ガラス層2および結晶質ガラス層3が順次形成さ
れてなり該結晶質ガラス層3が非晶質ガラス層2の周縁
より内側に形成されたことを特徴とする回路基板であ
る。
The circuit board of the present invention comprises an amorphous glass layer 2 and a crystalline glass layer 3 which are sequentially formed on the surface of a metal substrate 1, and the crystalline glass layer 3 is formed from the periphery of the amorphous glass layer 2. It is a circuit board characterized by being formed inside.

【0010】本発明において、金属基板1の材質は、特
に限定されるものではなく、公知の材質が制限なく使用
される。例えば、鉄、チタン、銅、ニッケル、クロム、
アルミニウム等の金属、あるいはこれらの金属よりなる
合金が好適に使用される。これらの材質のうち特に、ア
ルミニウムを含有する鉄合金が一般に使用される。
In the present invention, the material of the metal substrate 1 is not particularly limited, and known materials can be used without limitation. For example, iron, titanium, copper, nickel, chromium,
A metal such as aluminum or an alloy composed of these metals is preferably used. Among these materials, an iron alloy containing aluminum is generally used.

【0011】また、非晶質ガラス層2を構成するガラス
は、非晶質であり、且つ絶縁層を有するものであれば特
に限定されず、公知の組成が特に制限なく使用される。
一般には、非晶質成分を30重量%(wt%)以上、好
ましくは45wt%以上含有する絶縁性のガラスが好適
に使用される。代表的な組成を例示すれば、SiO2
主成分とし、これにAl2 3 ,CaO,PbO,Ba
O,ZnO等を配合したケイ酸ガラス;PbO−B2
3 を主成分とし、これにSiO2 ,ZnO,CaO等を
配合した鉛ホウ酸ガラス;Na2 O−CaO−SiO2
を主成分とし、これにMgO,PbO等を配合したソー
ダ石灰ガラス、Na2 O−B2 3 −SiO2 を主成分
とし、この系にPbO,ZnO,Al2 3 等を配合し
たホウケイ酸ガラス、CaO−MgO−Al2 3 −S
iO2 を主成分とし、これにNa2 O等を配合したアル
ミノケイ酸ガラス等が挙げられる。上記ガラス組成のう
ちSiO2 を主成分として含むガラスにおいて、SiO
2 の割合は、30wt%以上、特に40〜70wt%が
好適である。
The glass constituting the amorphous glass layer 2 is not particularly limited as long as it is amorphous and has an insulating layer, and a known composition is used without particular limitation.
Generally, insulating glass containing 30% by weight (wt%) or more, preferably 45% by weight or more of an amorphous component is preferably used. A typical composition is, for example, SiO 2 as a main component and Al 2 O 3 , CaO, PbO, Ba.
O, silicate glass was formulated with ZnO or the like; PbO-B 2 O
Lead borate glass containing 3 as a main component and SiO 2 , ZnO, CaO or the like mixed therein; Na 2 O-CaO-SiO 2
Is a main component, soda lime glass in which MgO, PbO and the like are mixed, Na 2 O-B 2 O 3 -SiO 2 as a main component, and PbO, ZnO, Al 2 O 3 and the like in this borosilicate acid glass, CaO-MgO-Al 2 O 3 -S
Examples include aluminosilicate glass containing iO 2 as a main component and Na 2 O or the like mixed therein. In the glass containing SiO 2 as a main component among the above glass compositions,
The ratio of 2 is preferably 30 wt% or more, particularly 40 to 70 wt%.

【0012】また、結晶質ガラス層3を構成するガラス
は、結晶性を示し、且つ絶縁性を有するものであれば特
に限定されず、公知の組成が制限なく使用される。一般
には、酸化物フリットを25重量%以上、好ましくは3
5〜60wt%含有する絶縁性ガラスが好適に使用され
る。代表的な成分を例示すれば、上記した非晶質ガラス
に、Al2 3 ,ZrO2 ,CaO,PbO,Ti
2 ,BaOより選ばれた少なくとも1種の酸化物フリ
ットを配合したガラスが好適である。
The glass constituting the crystalline glass layer 3 is not particularly limited as long as it exhibits crystallinity and has an insulating property, and a known composition can be used without limitation. Generally, the oxide frit is at least 25% by weight, preferably 3
Insulating glass containing 5 to 60 wt% is preferably used. As typical examples of the components, Al 2 O 3 , ZrO 2 , CaO, PbO, Ti can be added to the above-mentioned amorphous glass.
A glass containing at least one oxide frit selected from O 2 and BaO is preferable.

【0013】本発明の最大の特徴は、結晶質ガラス層3
が該非晶質ガラス層2の周縁より内側に形成されること
にある。即ち、かかる構造とすることにより、非晶質ガ
ラス層2上に結晶質ガラス層3の形成時の加熱、或い
は、結晶質ガラスの形成後の導体層の形成工程における
加熱冷却による熱履歴による結晶質ガラス層の周縁部で
のクラックの発生、欠落を極めて効果的に防止すること
ができる。
The greatest feature of the present invention is that the crystalline glass layer 3
Are formed inside the peripheral edge of the amorphous glass layer 2. That is, by adopting such a structure, the crystal due to the heat history due to the heating during the formation of the crystalline glass layer 3 on the amorphous glass layer 2 or the heating and cooling in the step of forming the conductor layer after the formation of the crystalline glass. It is possible to extremely effectively prevent the occurrence and cracking of cracks at the peripheral portion of the high quality glass layer.

【0014】本発明において、結晶質ガラス層3は、非
晶質ガラス層2の周縁より内側に形成すれば上記効果を
発揮するが、特に好ましくは、非晶質ガラス層周縁から
結晶質ガラス層周縁までの距離(d,d′)を50μm
以上、好ましくは100μm以上隔てるのが望ましい。
尚、結晶性ガラス層の周縁部は必ずしも非晶質ガラス層
と平行である必要はなく、また、全ての部分で同じ距離
とする必要はない。上記距離が50μmより短い場合、
結晶質ガラス層の形成厚みを実用的な厚み、一般には、
20μm以上とした場合、該層の形成時、次の工程の導
体層の形成、更にそれに続く抵抗体の形成時等におい
て、結晶質ガラス層周縁にクラックを生じ、導体パター
ンの損傷、欠落を招く傾向がある。
In the present invention, if the crystalline glass layer 3 is formed inside the peripheral edge of the amorphous glass layer 2, the above effect is exhibited, but it is particularly preferable that the crystalline glass layer 3 extends from the peripheral edge of the amorphous glass layer. Distance (d, d ') to the periphery is 50 μm
As described above, it is desirable that they are separated by 100 μm or more.
The peripheral edge of the crystalline glass layer does not necessarily have to be parallel to the amorphous glass layer, and it is not necessary to have the same distance in all the portions. If the distance is shorter than 50 μm,
The formation thickness of the crystalline glass layer is a practical thickness, generally,
When the thickness is 20 μm or more, a crack is generated in the peripheral edge of the crystalline glass layer during the formation of the layer, the formation of the conductor layer in the next step, and the subsequent formation of the resistor, and the conductor pattern is damaged or missing. Tend.

【0015】また、非晶質ガラス周縁から結晶質ガラス
周縁までの距離は、非晶質ガラスの金属との密着性、該
ガラスと金属との熱膨張係数差等を考慮し、且つ、導体
パターンの形成に支障を与えない最小限度にとどめるこ
とが好ましい。
The distance from the peripheral edge of the amorphous glass to the peripheral edge of the crystalline glass is determined in consideration of the adhesion between the amorphous glass and the metal, the difference in the coefficient of thermal expansion between the glass and the metal, and the conductor pattern. It is preferable to limit the amount to the minimum level that does not hinder the formation of

【0016】本発明において、非晶質ガラス層は、金属
基板に対して熱膨張率の差が6×10-6/℃以下また、
結晶質ガラス層は非晶質ガラス層に対して、熱膨張率の
差が4×10-6/℃以下となるようにその組成を調整し
て使用することが好ましい。
In the present invention, the amorphous glass layer has a difference in coefficient of thermal expansion of 6 × 10 −6 / ° C. or less with respect to the metal substrate.
The crystalline glass layer is preferably used by adjusting its composition so that the difference in coefficient of thermal expansion from the amorphous glass layer is 4 × 10 −6 / ° C. or less.

【0017】上記熱膨張率の調整は、前記ガラス組成に
Na,K,Li等のアルカリ金属の酸化物を配合するこ
とにより行なうことができる。
The adjustment of the coefficient of thermal expansion can be performed by adding an oxide of an alkali metal such as Na, K or Li to the glass composition.

【0018】本発明の回路基板の製造方法は特に制限さ
れないが、代表的な製造方法を例示すれば、下記の方法
が挙げられる。
The method of manufacturing the circuit board of the present invention is not particularly limited, but the following method can be mentioned as a representative manufacturing method.

【0019】すなわち、金属基板上にスクリーン印刷法
にて、非晶性ガラスペーストを塗布、乾燥後、焼付けし
て非晶質ガラス層を形成し後、同様にして結晶性ガラス
ペーストを非晶質ガラス層の周縁より内側に印刷塗布
後、乾燥、焼付して結晶質ガラス層を形成する方法が好
ましい。また、上記方法により、非晶質ガラス層を形成
させた後、該層の表面に前記した酸化物フリット粉を均
一に振りかけた後、焼成して表面に結晶質ガラス層を形
成させる方法も採用できる。この場合は非晶質ガラス層
が露出するようマスキング等の被覆を施す。
That is, an amorphous glass paste is applied onto a metal substrate by a screen printing method, dried, and baked to form an amorphous glass layer, and then the crystalline glass paste is similarly amorphous. A method is preferred in which a crystalline glass layer is formed by printing and coating the inside of the periphery of the glass layer, and then drying and baking. Further, a method of forming an amorphous glass layer by the above method, then sprinkling the above oxide frit powder evenly on the surface of the layer, and then firing to form a crystalline glass layer on the surface is also adopted. it can. In this case, coating such as masking is applied so that the amorphous glass layer is exposed.

【0020】上記焼成温度は、前記した組成の結晶質ガ
ラスが結晶化し得る温度が採用される。一般には700
〜1,100℃が好適である。また、非晶質ガラス層の
形成の前に、該ガラス層の金属基板への密着性を改良す
る為に、該金属基板の表面を活性化処理することが好ま
しい。かかる活性化処理としては、公知の処理方法が特
に制限なく採用される。例えば、鉄系の金属基板におい
ては、NH3 の分解ガス中で600℃〜1,300℃で
5〜20分間処理するか、または空気中もしくはN2
ス中にて600℃〜1,200℃で5〜20分間処理す
ることにより、基板表面に活性層を作る等の処理方法が
好ましい。
As the firing temperature, a temperature at which the crystalline glass having the above composition can be crystallized is adopted. Generally 700
A temperature of ˜1,100 ° C. is suitable. In addition, before forming the amorphous glass layer, it is preferable to activate the surface of the metal substrate in order to improve the adhesion of the glass layer to the metal substrate. As this activation treatment, a known treatment method is adopted without particular limitation. For example, an iron-based metal substrate is treated at 600 ° C. to 1,300 ° C. for 5 to 20 minutes in a decomposition gas of NH 3 , or 600 ° C. to 1,200 ° C. in air or N 2 gas. The treatment method is preferably such that an active layer is formed on the surface of the substrate by treating the substrate for 5 to 20 minutes.

【0021】本発明の回路基板への配線パターンの形成
は、公知の手段が特に制限なく採用される。例えば、従
来一般に使用されているスクリーン印刷法の他に、転写
法、蒸着法、スパッタリング法等の配線パターン形成方
法が好ましい。
For forming the wiring pattern on the circuit board of the present invention, known means can be adopted without particular limitation. For example, a wiring pattern forming method such as a transfer method, a vapor deposition method or a sputtering method is preferable in addition to the screen printing method which has been generally used conventionally.

【0022】[0022]

【効果】以上の説明より理解されるように、本発明の回
路基板は耐湿性および導体との密着強度に優れていると
いう特徴を有すると共に、実用的な厚みで結晶質ガラス
層を金属基板上に形成する場合でもクラックあるいはク
ラックによる破損・欠落を防止することができる。従っ
て、極めて高い信頼性で回路基板上に配線パターンを形
成することができる。
[Effect] As can be understood from the above description, the circuit board of the present invention has the characteristics of excellent moisture resistance and adhesion strength with a conductor, and has a practical thickness of a crystalline glass layer on a metal substrate. Even in the case of forming in a crack, it is possible to prevent cracks or damage / loss due to cracks. Therefore, the wiring pattern can be formed on the circuit board with extremely high reliability.

【0023】[0023]

【実施例】以下に、本発明を更に具体的に説明するため
に実施例を示すが、本発明はこれに限定されるものでは
ない。なお、実施例および比較例において、耐クラック
性試験、導体密着強度試験、耐湿性試験は以下の方法に
より実施した。
EXAMPLES Examples will be shown below in order to more specifically describe the present invention, but the present invention is not limited thereto. In the examples and comparative examples, the crack resistance test, conductor adhesion strength test, and moisture resistance test were carried out by the following methods.

【0024】a)耐クラック性試験 同様の方法で作成した10枚の導体パターンを有する回
路基板を、800℃に安定したバッチ炉へ30分間投入
後、室温に放置した水中へ入れる。これを1サイクルと
して、10サイクル行なった後の外観検査を顕微鏡にて
行ない結晶質ガラス層の周縁及び内部でのクラックの発
生および剥離がないか確認し、正常なものの割合で示し
た。
A) Crack resistance test A circuit board having 10 conductor patterns prepared by the same method is placed in a batch furnace stable at 800 ° C. for 30 minutes, and then placed in water left at room temperature. With this as one cycle, the appearance inspection after 10 cycles was carried out by a microscope to confirm whether or not cracks and peeling were generated at the periphery and inside of the crystalline glass layer, and the ratio was shown as normal.

【0025】b)導体接着強度試験 同様の方法で作成した10枚の回路基板の絶縁ガラス層
上に印刷された2×2mmの導体パターンに0.6φS
nメッキ導線を半田付け後、90度の方向に引っ張り、
夫々の回路基板につき、剥離強度を測定した。
B) Conductor Adhesive Strength Test 0.6φS on a 2 × 2 mm conductor pattern printed on the insulating glass layer of 10 circuit boards prepared by the same method.
After soldering the n-plated conductor, pull it in the direction of 90 degrees,
The peel strength was measured for each circuit board.

【0026】尚、上記導体パターンは、回路基板の結晶
質ガラス層上に金属成分比率で銀80%、パラジウム2
0%の比率をもつ厚膜導体パターンをスクリーン印刷
後、150℃で、15分間乾燥後、850℃、10分間
空気中で焼成を行なって形成した。また、剥離強度の測
定は、焼成後の基板を実回路基板と同等なプロセスにシ
ュミレートするため、850℃、10分にて5回焼成を
繰り返した後行なった。
The conductor pattern is formed by depositing 80% silver and 2 palladium on the crystalline glass layer of the circuit board.
A thick film conductor pattern having a ratio of 0% was screen-printed, dried at 150 ° C. for 15 minutes, and then baked at 850 ° C. for 10 minutes in the air to be formed. The peel strength was measured after repeating firing at 850 ° C. for 10 minutes 5 times in order to simulate the firing substrate in a process similar to that of the actual circuit board.

【0027】c)高温高湿負荷試験 導体パターンを形成した回路基板を、85℃、85%R
Hの高湿度にてDC15Vのバイアスをかけ、1,00
0時間投入後の絶縁抵抗を測定した。
C) High-temperature and high-humidity load test A circuit board on which a conductor pattern is formed is subjected to 85 ° C. and 85% R
Apply a bias of DC15V at high humidity of H, and
Insulation resistance was measured after being charged for 0 hours.

【0028】実施例1 アルミニウムを含有する耐熱鋼よりなる金属基板を窒素
中900℃、10分間熱処理後、表1に示す組成を有す
る非晶質のガラスAをスクリーン印刷にて塗付、150
℃、15分間加熱乾燥後、850℃、10分間空気中に
て焼成し、30μmの非晶質ガラス層を形成した。
Example 1 A metal substrate made of heat-resistant steel containing aluminum was heat-treated in nitrogen at 900 ° C. for 10 minutes, and then an amorphous glass A having the composition shown in Table 1 was applied by screen printing.
After heating and drying at 850 ° C. for 15 minutes, it was baked in air at 850 ° C. for 10 minutes to form a 30 μm amorphous glass layer.

【0029】[0029]

【表1】 [Table 1]

【0030】次に、上記非晶質ガラス層上部に表2に示
す組成を有する結晶質ガラスBをガラスAの周縁より内
側に表3に示す距離(d,d′:d=d′)をあけてガ
ラスAと同様な条件にて印刷、乾燥、焼成を実施し、表
3に示す厚さの結晶質ガラス層を形成して回路基板とし
た。得られた回路基板の各種試験結果を表3に示す。非
晶質ガラス周縁から50μm内側に結晶質ガラスを形成
することで、結晶質ガラスの厚さを厚くした場合でも結
晶性ガラス層周縁のクラックを抑えることができた。
Next, a crystalline glass B having the composition shown in Table 2 is placed on the upper portion of the above-mentioned amorphous glass layer at a distance (d, d ': d = d') shown in Table 3 inside the peripheral edge of the glass A. After opening, printing, drying and firing were carried out under the same conditions as for glass A to form a crystalline glass layer having a thickness shown in Table 3 to obtain a circuit board. Table 3 shows various test results of the obtained circuit board. By forming the crystalline glass within 50 μm from the peripheral edge of the amorphous glass, cracks at the peripheral edge of the crystalline glass layer could be suppressed even when the thickness of the crystalline glass was increased.

【0031】また、表3のNo.2〜8の回路基板は、
導体接着強度試験において導体パターンを形成するため
の熱履歴後も結晶性ガラス層の周縁部及び中央部へのク
ラックの発生は認められなかった。
Further, in Table 3, No. 2-8 circuit boards,
In the conductor adhesive strength test, no cracks were found in the peripheral portion and the central portion of the crystalline glass layer even after the heat history for forming the conductor pattern.

【0032】[0032]

【表2】 [Table 2]

【0033】[0033]

【表3】 [Table 3]

【0034】実施例2 実施例1において、使用する非晶質ガラスA及び結晶質
ガラスBを表4及び表5に示す組成のものに代えた以外
は同様にして回路基板を得た。
Example 2 A circuit board was obtained in the same manner as in Example 1 except that the amorphous glass A and the crystalline glass B used had the compositions shown in Tables 4 and 5, respectively.

【0035】[0035]

【表4】 [Table 4]

【0036】[0036]

【表5】 [Table 5]

【0037】得られた回路基板についての各種試験結果
を表6に示す。
Table 6 shows the results of various tests on the obtained circuit board.

【0038】[0038]

【表6】 [Table 6]

【0039】また、上記表6のNo.1〜7の回路基板
は、導体接着強度試験において導体パターンを形成する
ための熱履歴後も結晶性ガラス層の周縁部及び中央部へ
のクラックの発生は認められなかった。
Further, No. 1 in Table 6 above. In the circuit board Nos. 1 to 7, no cracks were observed in the peripheral edge portion and the central portion of the crystalline glass layer even after the heat history for forming the conductor pattern in the conductor adhesive strength test.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明の回路基板の代表的態様を示した
正面図
FIG. 1 is a front view showing a typical embodiment of a circuit board of the present invention.

【図2】図2は図1の側面図FIG. 2 is a side view of FIG.

【符号の説明】[Explanation of symbols]

1 金属基板 2 非晶質ガラス層 3 結晶質ガラス層 d,d′ 非晶質ガラス層周縁から結晶質ガラス層周縁
までの距離
1 Metal Substrate 2 Amorphous Glass Layer 3 Crystalline Glass Layer d, d'Distance from Amorphous Glass Layer Edge to Crystalline Glass Layer Edge

Claims (1)

【特許請求の範囲】[Claims] 金属基板表面に非晶質ガラス層および結晶質ガラス層が
順次積層されてなり、該結晶質ガラス層が非晶質ガラス
層の周縁より内側に形成されたことを特徴とする回路基
板。
A circuit board, characterized in that an amorphous glass layer and a crystalline glass layer are sequentially laminated on a surface of a metal substrate, and the crystalline glass layer is formed inside a peripheral edge of the amorphous glass layer.
JP4409391A 1991-02-18 1991-02-18 Circuit board Pending JPH05251837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4409391A JPH05251837A (en) 1991-02-18 1991-02-18 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4409391A JPH05251837A (en) 1991-02-18 1991-02-18 Circuit board

Publications (1)

Publication Number Publication Date
JPH05251837A true JPH05251837A (en) 1993-09-28

Family

ID=12682008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4409391A Pending JPH05251837A (en) 1991-02-18 1991-02-18 Circuit board

Country Status (1)

Country Link
JP (1) JPH05251837A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010042573A1 (en) * 2008-10-08 2010-04-15 E. I. Du Pont De Nemours And Company Substrate for lighting device and production thereof
WO2023190661A1 (en) * 2022-04-01 2023-10-05 日東電工株式会社 Laminate, heat-dissipating substrate, and laminate production method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010042573A1 (en) * 2008-10-08 2010-04-15 E. I. Du Pont De Nemours And Company Substrate for lighting device and production thereof
WO2023190661A1 (en) * 2022-04-01 2023-10-05 日東電工株式会社 Laminate, heat-dissipating substrate, and laminate production method

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