JPH05250440A - Marking drawing preparation processing system - Google Patents
Marking drawing preparation processing systemInfo
- Publication number
- JPH05250440A JPH05250440A JP4046483A JP4648392A JPH05250440A JP H05250440 A JPH05250440 A JP H05250440A JP 4046483 A JP4046483 A JP 4046483A JP 4648392 A JP4648392 A JP 4648392A JP H05250440 A JPH05250440 A JP H05250440A
- Authority
- JP
- Japan
- Prior art keywords
- marking
- hole
- marking character
- reference position
- character
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はプリント基板上のマーキ
ング図生成処理方式に関し、特にマーキング文字のレイ
アウト処理方式に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a marking diagram generation processing method on a printed circuit board, and more particularly to a marking character layout processing method.
【0002】[0002]
【従来の技術】従来のプリント基板のマーキング図生成
処理方式は、人手によりプリント基板の配線パターン図
を参照しながら、周囲のスルーホールと重ならないよう
マーキング文字のレイアウト位置を決定し、図面作成を
行っていた。2. Description of the Related Art In the conventional marking board generation processing method for a printed circuit board, the layout position of the marking characters is determined so as not to overlap the surrounding through holes while manually referring to the wiring pattern diagram of the printed circuit board to prepare the drawing. I was going.
【0003】[0003]
【発明が解決しようとする課題】上述した従来のプリン
ト基板のマーキング図生成処理方式は、人手によるマー
キング図の作成となっているので設計者の工数が大とな
ることや、作成した図面からプリント基板へマーキング
文字を描いた結果、マーキング文字がスルーホールと重
なり欠落するなど図面作成ミスが起こりやすいという問
題がある。The above-mentioned conventional marking board generation processing method for a printed circuit board requires a large number of man-hours for a designer because a marking drawing is created manually, and printing is performed from the created drawing. As a result of drawing the marking characters on the substrate, there is a problem that drawing errors are likely to occur, such as the marking characters overlapping the through holes and missing.
【0004】[0004]
【課題を解決するための手段】本発明のマーキング図生
成処理方式は、プリント基板のマーキング図生成処理に
おいて、前記プリント基板の配線パターン情報からスル
ーホールデータを抽出するスルーホール抽出手段と、部
品上のマーキング文字の位置を抽出し且つ部品名称の前
記マーキング文字を周囲のスルーホールと干渉しない位
置に自動レイアウトするマーキング文字レイアウト手段
とを含んで構成され、また前記マーキング文字レイアウ
ト手段には、前記スルーホールと干渉しない位置に前記
マーキング文字を配置するための格子が、部品基準位置
の近傍から優先順に配置されている。According to the marking diagram generation processing method of the present invention, there is provided through-hole extracting means for extracting through-hole data from the wiring pattern information of the printed circuit board in the marking diagram generation processing of the printed circuit board, and on the component. And a marking character layout means for automatically laying out the positions of the marking characters of the component name and automatically laying out the marking characters of the part name in a position where they do not interfere with the surrounding through holes. Grids for arranging the marking characters at positions that do not interfere with the holes are arranged in order of priority from the vicinity of the component reference position.
【0005】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【0006】図1は本発明の一実施例の構成を示すブロ
ック図、図2は本実施例のマーキング図生成機構の動作
を示すフローチャート、図3は本実施例によるマーキン
グ文字表示位置決定法及び表示位置優先度及びマーキン
グ文字表示例をそれぞれ(a),(b),(c)に示す
平面図である。FIG. 1 is a block diagram showing the construction of an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the marking diagram generation mechanism of this embodiment, and FIG. 3 is a marking character display position determining method and method according to this embodiment. It is a top view which shows a display position priority and a marking character display example in (a), (b), (c), respectively.
【0007】本実施例におけるマーキング図生成処理方
式は、図1に示すように、入出力装置11と演算処理装
置12とデータ記憶装置13及びマーキング図生成機構
14とにより実現され、マーキング図生成機構14はス
ルーホール抽出手段15及びマーキング文字レイアウト
手段16を含んでいる。As shown in FIG. 1, the marking diagram generation processing system in this embodiment is realized by an input / output unit 11, an arithmetic processing unit 12, a data storage unit 13 and a marking diagram generation mechanism 14, and the marking diagram generation mechanism is used. Reference numeral 14 includes a through hole extracting means 15 and a marking character layout means 16.
【0008】次に、本実施例の動作を図2のフローチャ
ートに従って説明する。但し、必要に応じて図1及び図
3を引用する。また図3(b)において、位置の優先度
は格子の若番順に優先することを示す。入出力装置11
(図1)からあらかじめデータ記憶装置13(図1)に
記憶済みとなっているパターン情報から、スルーホール
抽出手段15によりプリント基板のスルーホールデータ
を抽出する(ステップ21)。次に部品情報から、マー
キング文字と部品ライブラリで登録されるマーキング文
字の部品基準位置を、マーキング文字レイアウト手段1
6により抽出する(ステップ22〜23)。さらにマー
キング文字レイアウト手段16では、図3に示すマーキ
ング文字31をまず部品基準位置32に配置してみて、
既に抽出済みのスルーホール33と干渉していないかチ
ェックする。干渉している場合(図3(a))、部品基
準位置32から図3(b)に示す1から24の優先順に
従い、部品基準位置32の近傍の配置用格子34の順に
マーキング文字31を配置していく。マーキング文字3
1がスルーホール33と干渉しない位置が見つかるまで
処理を繰り返し、図3(c)のように表示位置を決定す
る(ステップ24)。Next, the operation of this embodiment will be described with reference to the flowchart of FIG. However, FIGS. 1 and 3 are cited as needed. In addition, in FIG. 3B, the priority of the position is given priority in the order of the smallest grid number. I / O device 11
Through hole data of the printed circuit board is extracted by the through hole extracting means 15 from the pattern information which is already stored in the data storage device 13 (FIG. 1) from (FIG. 1) (step 21). Next, from the component information, the marking character and the component reference position of the marking character registered in the component library are displayed as the marking character layout means 1
6 to extract (steps 22 to 23). Further, in the marking character layout means 16, first, the marking characters 31 shown in FIG.
It is checked whether or not it interferes with the already extracted through hole 33. When they interfere with each other (FIG. 3A), the marking characters 31 are arranged in order from the component reference position 32 to the placement grid 34 in the vicinity of the component reference position 32 in the order of priority 1 to 24 shown in FIG. 3B. Place it. Marking letter 3
The process is repeated until the position where 1 does not interfere with the through hole 33 is found, and the display position is determined as shown in FIG. 3C (step 24).
【0009】[0009]
【発明の効果】以上説明したように本発明は、マーキン
グ文字をスルーホールと干渉しない位置に自動レイアウ
トし、マーキング図を生成することにより、設計者のマ
ーキング図の作成工数の削減と図面作成ミスを防止でき
る効果がある。As described above, according to the present invention, the marking characters are automatically laid out at the positions not interfering with the through-holes and the marking drawing is generated, thereby reducing the number of man-hours required for the designer to create the marking drawing and making mistakes in drawing creation. There is an effect that can prevent.
【図1】本発明の一実施例の構成を示すブロック図であ
る。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
【図2】マーキング図生成機構の動作を示すフローチャ
ートである。FIG. 2 is a flowchart showing an operation of a marking diagram generation mechanism.
【図3】マーキング文字表示位置決定法及び表示位置優
先度及びマーキング文字表示例をそれぞれ(a),
(b),(c)に示す平面図である。[Fig. 3] Marking character display position determination method, display position priority, and marking character display example (a),
It is a top view shown in (b) and (c).
14 マーキング図生成機構 15 スルーホール抽出手段 16 マーキング文字レイアウト手段 31 マーキング文字 32 部品基準位置 33 スルーホール 34 配置用格子 35 部品 14 Marking Diagram Generation Mechanism 15 Through Hole Extracting Means 16 Marking Character Layout Means 31 Marking Characters 32 Component Reference Positions 33 Through Holes 34 Arrangement Grid 35 Components
Claims (2)
おいて、前記プリント基板の配線パターン情報からスル
ーホールデータを抽出するスルーホール抽出手段と、部
品上のマーキング文字の位置を抽出し且つ部品名称の前
記マーキング文字を周囲のスルーホールと干渉しない位
置に自動レイアウトするマーキング文字レイアウト手段
とを含むことを特徴とするマーキング図生成処理方式。1. In a marking drawing generation process of a printed circuit board, through hole extraction means for extracting through hole data from wiring pattern information of the printed circuit board, and a position of a marking character on a part and the marking of a part name. A marking diagram generation processing method comprising: a marking character layout means for automatically laying out characters at positions that do not interfere with surrounding through holes.
は、前記スルーホールと干渉しない位置に前記マーキン
グ文字を配置するための格子が、部品基準位置の近傍か
ら優先順に配置されていることを特徴とする請求項1記
載のマーキング図生成処理方式。2. The marking character layout means is characterized in that a grid for arranging the marking characters at a position that does not interfere with the through hole is arranged in order of priority from the vicinity of the component reference position. The marking diagram generation processing method according to item 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4046483A JP2821305B2 (en) | 1992-03-04 | 1992-03-04 | Marking diagram generation processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4046483A JP2821305B2 (en) | 1992-03-04 | 1992-03-04 | Marking diagram generation processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05250440A true JPH05250440A (en) | 1993-09-28 |
JP2821305B2 JP2821305B2 (en) | 1998-11-05 |
Family
ID=12748455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4046483A Expired - Fee Related JP2821305B2 (en) | 1992-03-04 | 1992-03-04 | Marking diagram generation processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2821305B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113011125A (en) * | 2019-12-18 | 2021-06-22 | 海信视像科技股份有限公司 | Printed circuit board checking method, device, equipment and computer storage medium |
-
1992
- 1992-03-04 JP JP4046483A patent/JP2821305B2/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113011125A (en) * | 2019-12-18 | 2021-06-22 | 海信视像科技股份有限公司 | Printed circuit board checking method, device, equipment and computer storage medium |
CN113011125B (en) * | 2019-12-18 | 2023-01-10 | 海信视像科技股份有限公司 | Printed circuit board checking method, device, equipment and computer storage medium |
Also Published As
Publication number | Publication date |
---|---|
JP2821305B2 (en) | 1998-11-05 |
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Legal Events
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Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980804 |
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R250 | Receipt of annual fees |
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LAPS | Cancellation because of no payment of annual fees |