JPH0333982A - Generating and processing system for jumper wiring diagram - Google Patents
Generating and processing system for jumper wiring diagramInfo
- Publication number
- JPH0333982A JPH0333982A JP1168507A JP16850789A JPH0333982A JP H0333982 A JPH0333982 A JP H0333982A JP 1168507 A JP1168507 A JP 1168507A JP 16850789 A JP16850789 A JP 16850789A JP H0333982 A JPH0333982 A JP H0333982A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- jumper
- route
- jumper wiring
- wiring diagram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 title claims abstract description 29
- 238000003672 processing method Methods 0.000 claims description 9
- 238000013500 data storage Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はジャンパ配線図生成処理方式に関し、特にプリ
ント基板のパターン設計で未配線となった区間のジャン
パ配線作業指示図面の作成及びプリント基板のジャンパ
線による改造指示図面の作成処理のためのジャンパ配線
図生成処理方式に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a jumper wiring diagram generation processing method, and in particular, to the creation of jumper wiring work instruction drawings for unwired sections in printed circuit board pattern design and to The present invention relates to a jumper wiring diagram generation processing method for creating a modification instruction drawing using jumper wires.
従来のプリント基板のジャンパ布線図生成処理方式は、
人手によりジャンパ配線経路を描くか、あるいは論理的
な配線区間を表わす区間衣のみを生成処理する方式であ
った。The conventional printed circuit board jumper wiring diagram generation processing method is
The method used was to draw the jumper wiring route manually, or to generate only a section line representing a logical wiring section.
上述した従来のジャンパ配線図生成処理方式は、人手に
よるジャンパ配線経路図の作成については、設計者の工
数が大となることや図面作成ミスが起こりやすいという
問題点があう、文区間表のみの表示では、その情報を見
て作業をする布線作業者にミスが発生する要因となると
いう問題点がある。The conventional jumper wiring diagram generation processing method described above has the problem that manual creation of jumper wiring route diagrams requires a large amount of man-hours for the designer and is prone to drawing creation errors. The display has a problem in that it can lead to errors by wiring workers who work while looking at the information.
本発明のジャンパ配線図生成処理方式は、プリント基板
のジャンパ配線図生成処理方式に釦いて、ジャンパ配線
を必要とする部品ビンあるいは回路パターン上の貫通孔
の論理的な区間情報からジャンパ配線経路を自動決定す
る決定手段と、配線図を生成する生成手段とを含む構成
である。The jumper wiring diagram generation processing method of the present invention clicks the jumper wiring diagram generation processing method for a printed circuit board to generate jumper wiring routes from logical section information of through holes on component bins or circuit patterns that require jumper wiring. The configuration includes a determining means for automatically determining and a generating means for generating a wiring diagram.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例の構成を示すブロック図であ
る。本発明のジャンパ配線図生成処理方式は、入出力装
置11と演算処理装置12とデータ記憶装置13及びジ
ャンパ配線図生成機構14とにより実現され、ジヤンパ
配線図生成機構14は配線経路決定手段15及び配線図
生成手段16を含んでいる。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The jumper wiring diagram generation processing method of the present invention is realized by the input/output device 11, the arithmetic processing unit 12, the data storage device 13, and the jumper wiring diagram generation mechanism 14. The jumper wiring diagram generation mechanism 14 includes the wiring route determining means 15 and It includes a wiring diagram generating means 16.
第2図は、第1図のジャンパ配線図生成機構14の動作
を示すフローチャートである。FIG. 2 is a flowchart showing the operation of the jumper wiring diagram generation mechanism 14 of FIG.
第3図は、配線経路の例と経路優先度の例を示すブロッ
ク図である。優先度は若番側が優先することを示す。FIG. 3 is a block diagram showing an example of a wiring route and an example of route priority. The priority indicates that the lower number side has priority.
次に、本発明の動作を第2図のフローチャートに従って
説明する。但し必要に応じて第1図釦よび第3図を引用
する。Next, the operation of the present invention will be explained according to the flowchart shown in FIG. However, the buttons in Figure 1 and Figure 3 will be quoted as necessary.
入出力装置11(第1図)からあらかじめデータ記憶装
置13(第1図)に記憶済のパターン設計情報や設計変
更情報からジャンパ配線区間を抽出する(ステップ21
〜22)。取り出した区間情報から基板上の配線経路を
決定する(ステップ23)。A jumper wiring section is extracted from the pattern design information and design change information stored in advance in the data storage device 13 (FIG. 1) from the input/output device 11 (FIG. 1) (step 21).
~22). The wiring route on the board is determined from the retrieved section information (step 23).
配線経路の決定は、ジャンパ配線の性格上以下の配線ル
ールで行なう。1;ピンから部品外形内方向及びピン並
び方向への引き出しは優先度を落とす(第3図の31.
32 )。2:ホールがジャンパ機付は対象の場合、ピ
ンからホール1でのパターンも出力する(第3図の33
)。3:上述のパターン上は配線経路としない(第3図
の34)。4;部品ピン上は配線経路としない(第3図
の35)。Due to the nature of jumper wiring, the wiring route is determined using the following wiring rules. 1; Priority is lowered for pulling out from the pin in the direction of the component outline and in the direction in which the pins are lined up (31 in Figure 3).
32). 2: If the hole is equipped with a jumper, the pattern from the pin to hole 1 is also output (33 in Figure 3).
). 3: The above pattern is not used as a wiring route (34 in FIG. 3). 4; Do not use the wiring route over the component pins (35 in Figure 3).
5;部品外形上は配線経路としないが、経路が見つから
ない場合、ピン並びを横切らない配線経路は許す($3
図の36)。以上のルールで決定された配線経路をプロ
ッタ出力し、ジャンパ配線図を作成する(ステップ24
)。5; It is not considered a wiring route based on the part outline, but if a route cannot be found, a wiring route that does not cross the pin arrangement is allowed ($3
36) in the figure. The wiring route determined according to the above rules is output on a plotter and a jumper wiring diagram is created (step 24).
).
以上説明したように本発明は、ジャンパ配線経路を自動
的に決定し、ジャンパ配線図を生成することによう、設
計者のジャンパ配線作業指示情報の作成工数の削減と配
線作業指示ミス及び布線作業者の作業ミスを防止できる
効果がある。As explained above, the present invention automatically determines jumper wiring routes and generates jumper wiring diagrams, thereby reducing the number of man-hours required for designers to create jumper wiring work instruction information and preventing mistakes in wiring work instructions. This has the effect of preventing work errors by workers.
第1図は本発明の一実施例の構成を示すブロック図、第
2図は本発明の一実施例を示すフローチャート、第3図
(a)は配線経路図の一例を示すブロック図、第3図(
b)は部品ピンからの経路引き出し方向優先度を示すブ
ロック図である。
11・・・・・・入出力装置、12・・・・・・演算処
理装置、13・・・・・・データ記憶装置、14・・・
・・・ジャンパ配線図生成機構、15・・・・・・配線
経路決定手段、16・・・・・・配線図生成手段。FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a flowchart showing an embodiment of the invention, FIG. 3(a) is a block diagram showing an example of a wiring route diagram, figure(
b) is a block diagram showing the priority in the direction of route extraction from the component pin. 11... Input/output device, 12... Arithmetic processing unit, 13... Data storage device, 14...
. . . Jumper wiring diagram generation mechanism, 15 . . . Wiring route determining means, 16 . . . Wiring diagram generation means.
Claims (1)
ジャンパ配線を必要とする部品ピンあるいは回路パター
ン上の貫通孔の論理的な区間情報からジャンパ配線経路
を自動決定する決定手段と、配線図を生成する生成手段
とを含むことを特徴とするジャパン配線図生成処理方式
。In the printed circuit board jumper wiring diagram generation processing method,
Japan wiring characterized in that it includes a determining means that automatically determines a jumper wiring route from logical section information of component pins that require jumper wiring or through holes on a circuit pattern, and a generating means that generates a wiring diagram. Diagram generation processing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1168507A JPH0333982A (en) | 1989-06-29 | 1989-06-29 | Generating and processing system for jumper wiring diagram |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1168507A JPH0333982A (en) | 1989-06-29 | 1989-06-29 | Generating and processing system for jumper wiring diagram |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0333982A true JPH0333982A (en) | 1991-02-14 |
Family
ID=15869338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1168507A Pending JPH0333982A (en) | 1989-06-29 | 1989-06-29 | Generating and processing system for jumper wiring diagram |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0333982A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6608922B1 (en) | 1998-12-15 | 2003-08-19 | Fujitsu Limited | Method of recognizing connection of reconstructing pattern in printed wiring board |
EP2498586A2 (en) | 2011-03-11 | 2012-09-12 | Funai Electric Co., Ltd. | Flexible Flat Cable and Image Display Device |
-
1989
- 1989-06-29 JP JP1168507A patent/JPH0333982A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6608922B1 (en) | 1998-12-15 | 2003-08-19 | Fujitsu Limited | Method of recognizing connection of reconstructing pattern in printed wiring board |
EP2498586A2 (en) | 2011-03-11 | 2012-09-12 | Funai Electric Co., Ltd. | Flexible Flat Cable and Image Display Device |
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