JPH05250300A - Information processor - Google Patents

Abstract

PURPOSE:To obtain the information processor which can improve the reliability of an entire system by acculately judging the transfer error of status when transferring the status through a bus connector by an input/output controller. CONSTITUTION:When transferring the status to a main storage device 3, first of all, an input/output controller 6 transfers the status to a bus connector 4. When the status is normally received, the bus connector 4 reports the normal end of transfer to the input/output controller 6 and holds the ID number of the input/output controllers 6, which transfers the status, in an input/output information holding part 14. Next, the bus connector 4 transfers the status to the main storage device 3. When transfer error is generated, the bus connector 4 sets data expressing the generation of transfer error to the input/output controller information holding part 41 together with the ID number. Thus, the transfer error of the status can be exactly informed of an operation processor 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to an information processing device in which an input / output control device and an arithmetic processing device and a main storage device are connected via a bus connection device.

[0002]

2. Description of the Related Art In a conventional information processing device, when an input / output control device notifies a state (status) within itself to an arithmetic processing device, the input / output control device stores the status in a main storage device and performs arithmetic operation. An interrupt is issued to the processing device to notify that the status is stored in the main storage device. The arithmetic processing unit recognizes the state in the input / output control unit by reading the status in the main memory.

Therefore, when the input / output control device stores the status in the main memory via the bus connection device, the input / output control device first transfers the status to the bus connection device.
The bus connection device transfers the status to the main storage device when the status is normally transferred from the input / output control device,
Upon completion of this transfer, the bus connection device notifies the input / output control device of the status storage state. Next, when the status is normally transferred from the I / O controller, the bus connecting device notifies the I / O controller that the status has been normally transferred. At this point, the I / O controller normally ends the transfer cycle. Subsequently, the bus connecting device transfers the status to the main memory, but if an error occurs in this bus cycle, the status is not stored in the main memory.

[0004]

In the above-mentioned conventional information processing apparatus, when the status is transferred from the input / output control device to the main memory device, an error occurs in the transfer between the bus connection device and the main memory device. Even so, since the input / output control device determines that the status transfer cycle has ended normally, it is determined that the status is normally stored in the main storage device.
The arithmetic processing unit is notified that the status is stored in the main memory. However, in reality, an error occurs when the status is stored in the main storage device, and since the status is not stored in the main storage device, a contradiction occurs in the system.

In the prior art, in such a case, there is a problem that the bus connection device goes down and the input / output control device under it becomes inoperable.

[0006]

According to an information processing apparatus of the present invention, an arithmetic processing unit, a main storage unit and a bus connecting unit are connected to a system bus, and the bus connecting unit and a plurality of input / output control units are connected to an input / output bus. In an information processing device for connecting to a device, the bus connection device identifies and stores the input / output control device to which the status is transferred via itself to store the status in the main storage device. When the status transfer to the I / O device is completed, the I / O control device information holding unit that stores the information of the storage state of the status together with the information of the I / O control device that has been identified and stored is provided. When the input / output control unit of the above notifies the main storage unit of the storage of the status to the arithmetic processing unit, the information on the storage state of the status stored inside is added to the performance storage unit. A structure having the function of notifying the processor.

[0007]

In the information processing apparatus of the present invention, when the input / output control unit notifies the arithmetic processing unit that the status has been transferred to the main storage unit, the bus connection unit stores the status stored in itself. The state information is added and notified to the arithmetic processing unit. Therefore, the arithmetic processing unit can determine whether the status transfer to the main storage device is normally ended or abnormally ended by the notification of the end of the status transfer from the input / output control unit, and there is no inconsistency in the system. It never happens.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. The information processing apparatus 10 according to the present embodiment is connected to the arithmetic processing unit 2, the main memory 3, the bus connection unit 4, and the input / output bus 5 connected to the system bus 1 via the bus connection unit 4. It is composed of input / output control devices 6 and 7. The bus connection device 4 also includes an input / output control device information holding unit 4 that stores status transfer information for each input / output control device.
Have one.

FIG. 2 is an explanatory diagram showing a storage format of data held in the input / output control device information holding unit.

The bus connection device 4 comprises input / output control devices 6 and 7.
When the status is transferred from the main storage device 4 to the main storage device 4, 8-bit data representing the ID number for identifying the input / output control device that has transferred the status (in this embodiment, the ID number for identifying the input / output control device 21 and 8-bit data representing the storage status of the status in the main memory 4 ("000" at the normal end).
"0" is stored during transfer, "1111" is stored during abnormal transfer, and any data other than "0000" and "1111" is stored during abnormal termination to indicate the status storage status. Depending on the type of error, it can be expressed by a 4-bit code, but it is not expressed in the present embodiment) 22) is held in the input / output control device information holding unit 41 for each input / output control device.

Next, the operation will be described.

When the input / output control device 6 notifies the state (status) within itself to the arithmetic processing device 2, when the input / output control device 6 stores the status in the main storage device 3, it interrupts the arithmetic processing device 2. Is generated to notify that the status is stored in the main storage device 3, and then notify the state within the device itself to the arithmetic processing device 2.

To explain this operation in detail, when transferring the status to the main storage device 3, the input / output control device 6 first transfers the status to the bus connecting device 4 via the input / output bus 5. When the bus connection device 4 receives the status normally, the bus connection device 4 notifies the input / output control device 6 that the status has been normally received, and transfers the status to the input / output control device information holding unit 41 in its own device. The ID number of the control device 6 is held as 8-bit data, and "1111" is stored in 4-bit data indicating the status storage state. Here, the input / output control device 6 determines that the bus cycle for status transfer has ended normally by the notification that the status from the bus connection device 4 has been normally received.

Next, the bus connection device 4 transfers the status transferred from the input / output control device 6 to the main storage device 3 via the system bus 1. Therefore, when the transfer ends normally, the bus connection device 4 converts the 4-bit data indicating the status storage state of the input / output device information holding unit 41 in its own device into
Set "0000". When a transfer error occurs, the bus connection device 4 adds the 4-bit data indicating the status storage state of the input / output control device information holding unit 41 in its own device to the 4-bit data (“0000” indicating that a transfer error has occurred). "And data other than" 1111 ") are set and held. Since the input / output control device 6 also notifies the arithmetic processing device 2 that the status has been written in the main storage device 3 by an interrupt via the bus connection device 4, the input / output control device 6 first performs the bus operation. An interrupt is generated in the connection device 4. The bus connection device 4 which has received the status storage interrupt from the input / output control device 6 determines the status storage state of the input / output control device 6 by the input / output control device information holding unit 41 in its own device.

That is, when the 4-bit data indicating the status storage state is "0000", the bus connection device 4
Adds to the status storage interrupt from the input control device 6 that the status storage has been completed normally, and interrupts the arithmetic processing device 2. In addition, it represents the status storage status 4
When the bit data is “1111”, the bus connection device 4 determines that the storage of the status in the main storage device 3 is not completed yet, and stores the status in the arithmetic processing device 2 until the storage of the status is completed. Hold interrupt. When the 4-bit data representing the status storage state is other than "0000" and "1111", this error information is added to the status storage interrupt from the input / output control device 6 to interrupt the arithmetic processing device 2. Here, if the arithmetic processing unit 2 receives an interrupt accompanied by the information of the status storage error in the main storage unit 3, the recovery process can be executed.

[0017]

As described above, according to the present invention, when the input / output control device transfers the status via the bus connection device, the status transfer error can be accurately judged, so that the performance of the entire system can be improved. There is an effect that the reliability can be improved without dropping.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a storage format of data held in an input / output control device holding unit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 system bus 2 arithmetic processing unit 3 main memory unit 4 bus connection unit 5 input / output bus 6,7 input / output control unit 10 information processing unit 41 input / output control unit information holding unit

Claims (1)

[Claims] 1. An information processing apparatus for connecting an arithmetic processing unit, a main memory unit, and a bus connecting unit to a system bus, and connecting the bus connecting unit and a plurality of input / output control units to an input / output bus, The connection device identifies and stores the input / output control device that has transferred the status via itself to store the status in the main storage device, and stores the status when the status transfer to the main storage device is completed. The information of the input / output control device which is identified and stored together with the information of the input / output control device, and
The input / output control device information holding unit adds information on the storage state of the status internally stored when an arbitrary input / output control device notifies the main processing device of the storage of the status to the arithmetic processing device. An information processing device having a function of notifying the arithmetic processing device.