JPH05249916A - Low electric power driving circuit - Google Patents

Abstract

PURPOSE:To reduce electric power consumption, and downsize an electric power supply circuit by inputting an output pulse of a reactive power recovery circuit formed by using an inductance to one electric power supply terminal. CONSTITUTION:An output 3 of a reactive power recovery circuit 6 is connected to a high electric potential side electric power supply terminal 9 of a driver IC 10 composed of a complementary type MOS transistor. Respective outputs of this drive IC 10 are further connected to a scanning electrode of an XY matrix panel and a data electrode. When the third P type MOS transistor is turned on by controlling an input terminal, an output pulse created in the reactive power recovery circuit 6 is impressed on the electrode of the XY matrix panel. Though there exists a capacitance in the electrode of this panel, a charging/discharging electric power can be recovered by means of the reactive power recovery circuit 6. When the third N type MOS transistor is turned on, the output is fixed in low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power drive circuit for a capacitive load, and more particularly to a drive circuit for a flat panel display such as a plasma display and electroluminescence.

[0002]

2. Description of the Related Art Conventionally, in this type of capacitive load drive circuit, a reactive power recovery circuit using an inductor L as shown in FIG. 4 has been known in order to reduce power consumption. The first capacitor C1 is much larger than the load capacitance CL and is regarded as a low voltage source, and its voltage is automatically set to a voltage V1 / 2 which is half the voltage V1 of the high potential side power source 2 by the switching operation of the circuit. To be done. The output is raised by turning on the second P-type MOS transistor MP2 as shown in FIG. 5 and applying V1 / 2 to the LC circuit including the inductor L and the load capacitance CL. The voltage across CL rises to V1 due to the operation of the LC circuit. When the voltage rises to V1, the first P-type MOS transistor MP1 is turned on and clamped at V1. At the fall, similarly, the second N-type MOS transistor MN2 and the first N-type MOS transistor MN1 are sequentially turned on. Energy of CL (V1) ² flows out from C1 to charge CL at the time of rising, but all of C1 is generated by the operation of the LC circuit at the time of falling.
Returned to (Energy Recovery Sustain Circuit in AC Plasma Display (EnergyR
recovery Sustain Circuit f
or the ACPlasma Display),
L. F. Weber et al; SDI87 DIGE
ST, P92-95, 1987. reference).

When such a reactive power recovery circuit is driven by one electrode on the entire panel like one electrode on the entire panel like the sustain electrode of the AC memory plasma display, the number of recovery circuits is small and the efficiency is high. Good, scan electrodes,
When separately driving X and Y lines of an XY matrix like data electrodes, it is necessary to use a recovery circuit using LC for each electrode, which is difficult to realize.

[0004]

As described above, the scanning electrodes,
Since it is difficult to attach a reactive power recovery circuit to the data electrode, conventionally, a complementary MOS transistor is used to generate and drive a pulse as shown in FIG. In this method, since the reactive power is not recovered, the power consumed by charging / discharging a very large capacity existing in the scan electrode and the data electrode is wasted.

[0005]

The drive circuit according to the present invention comprises a P
A circuit for driving a capacitive load using complementary MOS transistors of a channel MOS transistor and an N channel MOS transistor is characterized in that an output pulse of a reactive power recovery circuit using an inductor is input to one power supply terminal.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of a first embodiment of the present invention. The output 3 of the reactive power recovery circuit 6 is connected to the high-potential-side power supply terminal 9 of the driver IC 10 composed of complementary MOS transistors. In recent years, a driver IC with 32 to 64 outputs and a withstand voltage of about 200 V has been developed.
Of each of the outputs are connected to the scan electrodes and the data electrodes of the XY matrix panel.

FIG. 2 is a diagram showing a specific circuit of the first embodiment. When the input terminal 4 is controlled to turn on the third P-type MOS transistor MP3, the reactive power recovery circuit 6 is used. The output pulse is applied to the electrodes of the XY matrix panel. Although the electrodes of the panel have capacitance, the reactive power recovery circuit 6 recovers the power associated with charging and discharging. When the third N-type MOS transistor MN3 is turned on, the output is fixed to low. In this way, by controlling the input terminal depending on the presence or absence of display, it is possible to apply a pulse to the electrode of the panel or fix it to the row.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, the output 3 of the reactive power recovery circuit 6 is connected to the low potential side power supply terminal 11 of the output circuit 8 of the driver IC.
Are connected. Used when applying a pulse of negative potential to the panel electrode with respect to the reference potential of the logic input signal.

Taking the data side electrode as an example, C per electrode
= About 40 pF of capacitance is about N = 640 electrodes (in the case of 640 dots in the X direction), the frequency f =
Driving at 125 KHz voltage V = 80V, N × f × C
Normally, about 20.5 W of electric power is consumed by × V ² , but about 80% of the electric power is recovered by the present invention. 4.1
Power consumption of about W is sufficient.

[0010]

As described above, according to the present invention, the reactive power recovery circuit can be used even in the driver IC which applies the pulse to different electrodes, and the power due to the charging and discharging of the capacitance existing in the panel electrode can be reduced. It can be recovered and the power consumption can be greatly reduced.

Further, the power supply circuit can be downsized by reducing the power consumption, and the components related to heat radiation can be reduced, so that the cost can be largely reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific circuit of the first exemplary embodiment of the present invention.

FIG. 3 is a specific circuit diagram of the second embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional reactive power recovery circuit.

FIG. 5 is a diagram showing a timing waveform of a conventional reactive power recovery circuit.

FIG. 6 is a circuit diagram of a conventional driver circuit.

[Explanation of symbols]

 6 Reactive power recovery circuit 10 Driver IC

Claims (1)

[Claims] 1. A circuit for driving a capacitive load using complementary MOS transistors of a P-channel type MOS transistor and an N-channel type MOS transistor, wherein a reactive power recovery circuit using an inductor is connected to one power supply terminal. A low power drive circuit characterized by: