JPH05243862A - Fet amplifier circuit - Google Patents
Fet amplifier circuitInfo
- Publication number
- JPH05243862A JPH05243862A JP4073041A JP7304192A JPH05243862A JP H05243862 A JPH05243862 A JP H05243862A JP 4073041 A JP4073041 A JP 4073041A JP 7304192 A JP7304192 A JP 7304192A JP H05243862 A JPH05243862 A JP H05243862A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- fet
- amplifier circuit
- resistors
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＦＥＴ増幅回路に関し、
特にＦＥＴを複数個並列に接続した広帯域かつ低消費電
力のＦＥＴ増幅回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FET amplifier circuit,
In particular, it relates to a wide band and low power consumption FET amplifier circuit in which a plurality of FETs are connected in parallel.
【０００２】[0002]
【従来の技術】ＦＥＴ増幅回路の基本的回路を図３
（ａ）に示す。このような回路では、ＦＥＴの各端子間
には破線で示すようにそれぞれ寄生容量Ｃgs，Ｃgd，Ｃ
dsがある。このため、このＦＥＴ増幅回路の等価回路は
図３（ｂ）に示すようになる。そして、ゲート入力信号
とドレイン出力信号との間には 180゜の位相差があるた
め、Ｃgdによりドレイン出力信号がゲート側に帰還され
ると増幅度が低下され、入力側に大きな容量が存在する
ことと等化になる（ミラー効果と呼ばれている。）。2. Description of the Related Art The basic circuit of an FET amplifier circuit is shown in FIG.
It shows in (a). In such a circuit, the parasitic capacitances C gs , C gd , C are provided between the terminals of the FET as shown by the broken lines .
There is ds . Therefore, the equivalent circuit of this FET amplifier circuit is as shown in FIG. Since there is a phase difference of 180 ° between the gate input signal and the drain output signal, when the drain output signal is fed back to the gate side by C gd , the amplification degree is reduced and a large capacitance exists on the input side. Doing and equalization (called the Miller effect).
【０００３】この場合の入力容量は、 Ｃin＝Ｃgs＋（１−Ａ）Ｃgd…（１） となる。ここで、Ａは低域での電圧利得である。したが
って、ゲート側の等価回路は図３（ｃ）となり、この場
合の３ｄＢ低下の遮断周波数ｆc1は、 ｆc1＝１／２π・１／Ｒg ・１／Ｃin…（２） となる。The input capacitance in this case is C in = C gs + (1-A) C gd (1) Here, A is the voltage gain in the low range. Therefore, the equivalent circuit on the gate side is as shown in FIG. 3 (c), and the cut-off frequency f c1 for 3 dB reduction in this case is f c1 = 1 / 2π · 1 / R g · 1 / C in (2)
【０００４】ここで、図４（ａ）に示すようにゲートと
接地との間に抵抗Ｒを挿入すると、図４（ｂ）の等価回
路となり、３ｄＢ低下の遮断周波数ｆc2は、 ｆc2＝１／２π・１／Ｒg ・（Ｒg ＋１）／Ｒ・１／Ｃin…（３） となる。図４（ｃ）はゲート側の等価回路である。
（２）式と（３）式を比較すると、ｆc2＞ｆc1となり周
波数帯域が広げられることがわかる。If a resistor R is inserted between the gate and ground as shown in FIG. 4A, the equivalent circuit of FIG. 4B is obtained, and the cutoff frequency f c2 of 3 dB lower is f c2 = 1 / 2π · 1 / R g · (R g +1) / R · 1 / C in (3) FIG. 4C is an equivalent circuit on the gate side.
Comparing equations (2) and (3), it can be seen that f c2 > f c1 and the frequency band is widened.
【０００５】[0005]
【発明が解決しようとする課題】ところで、ＦＥＴ増幅
回路のゲートにバイアスを供給する回路として、図５
（ａ）に示すように、バイアス電源＋Ｖの電圧を抵抗Ｒ
１を通してＦＥＴ Ｑのゲートにバイアス電圧を与える
回路がある。又、同図（ｂ）に示すように、バイアス電
源＋Ｖの電圧を抵抗Ｒ１，Ｒ２にて分圧し、ＦＥＴ Ｑ
のゲートにバイアス電圧を与える回路もある。By the way, as a circuit for supplying a bias to the gate of the FET amplifier circuit, as shown in FIG.
As shown in (a), the voltage of the bias power supply + V is applied to the resistor R.
There is a circuit for applying a bias voltage to the gate of the FET Q through 1. Further, as shown in FIG. 3B, the voltage of the bias power source + V is divided by the resistors R1 and R2, and the FET Q
There is also a circuit that applies a bias voltage to the gate of.
【０００６】これらのゲートバイアスを比較した場合、
図５（ａ）の回路では、ＦＥＴ Ｑのゲート電流はほと
んど流れないのでバイアス電源の容量をほとんど必要と
しない。これに対し、同図（ｂ）の回路では、ＦＥＴ
Ｑのゲート電流は殆ど流れないが、抵抗Ｒ１，Ｒ２に電
流が流れるため、バイアス電源は電力を消費することに
なる。Comparing these gate biases,
In the circuit of FIG. 5A, since the gate current of the FET Q hardly flows, the capacity of the bias power supply is hardly needed. On the other hand, in the circuit of FIG.
Although the gate current of Q hardly flows, a current flows through the resistors R1 and R2, so that the bias power source consumes power.
【０００７】したがって、図５（ａ）のゲートバイアス
を使用することが好ましいが、前記したようにＦＥＴ増
幅回路の周波数帯域を広げようとＦＥＴのゲートと接地
との間に抵抗を接続すると、同図（ａ）のゲートバイア
スを採用した場合でも、この接続した抵抗によってゲー
トと接地との間が接続され、結果として同図（ｂ）のゲ
ートバイアスとなり、バイアス電源の消費電力の点で不
利になる。特に、ＦＥＴを多数個並列に接続したＦＥＴ
増幅回路では、電力消費がＦＥＴの個数分だけ増加さ
れ、低消費電力化を進めることが困難になる。本発明の
目的は、広帯域化を図る一方で、低消費電力化を可能に
したＦＥＴ増幅回路を提供することにある。Therefore, although it is preferable to use the gate bias shown in FIG. 5A, if a resistor is connected between the gate of the FET and the ground in order to widen the frequency band of the FET amplifier circuit as described above, the same effect is obtained. Even when the gate bias shown in FIG. 7A is adopted, the gate and the ground are connected by this connected resistor, resulting in the gate bias shown in FIG. 7B, which is disadvantageous in terms of the power consumption of the bias power supply. Become. In particular, an FET with many FETs connected in parallel
In the amplifier circuit, the power consumption is increased by the number of FETs, which makes it difficult to reduce the power consumption. It is an object of the present invention to provide an FET amplifier circuit that enables low power consumption while achieving a wide band.
【０００８】[0008]
【課題を解決するための手段】本発明は、並列に接続さ
れた多数個のＦＥＴの各ゲートにそれぞれ抵抗又はイン
ダクタンスの一端を接続し、これら抵抗又はインダクタ
ンスの他端を一括接続するとともに、この他端をコンデ
ンサを通して接地する。According to the present invention, one end of a resistance or an inductance is connected to each gate of a large number of FETs connected in parallel, and the other ends of these resistances or inductances are collectively connected. Ground the other end through a capacitor.
【０００９】[0009]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明のＦＥＴ増幅回路の一実施例の回路図
であり、ＦＥＴを多数個並列にしたプッシュブル増幅回
路に適用した例を示している。同図のように、多数個の
ＦＥＴ Ｑ１１〜Ｑ１ｎはソース，ドレインがそれぞれ
接続される。同様にＦＥＴ Ｑ２１〜Ｑ２ｎもソース，
ドレインがそれぞれ接続される。そして、各ＦＥＴのソ
ースは接地され、ドレインはトランスＴ２に接続され、
このトランスＴ２を介して電源＋Ｂに接続される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the FET amplifier circuit of the present invention, showing an example applied to a push-bull amplifier circuit in which a large number of FETs are arranged in parallel. As shown in the figure, the sources and drains of the FETs Q11 to Q1n are connected to each other. Similarly, FETs Q21 to Q2n are also sources,
The drains are connected respectively. The source of each FET is grounded, the drain is connected to the transformer T2,
It is connected to the power source + B via this transformer T2.
【００１０】一方、各ＦＥＴのゲートはバイアス抵抗Ｒ
１１〜Ｒ１ｎ，Ｒ２１〜Ｒ２ｎを介してトランスＴ１に
接続され、このトランスＴ１を介してバイアス電源Ｖｇ
に接続される。又、このトランスＴ１を通して入力信号
Ｓ１が入力される。更に、各ＦＥＴのゲートには抵抗Ｒ
１１〜Ｒ１ｎ，Ｒ２１〜Ｒ２ｎの一端がそれぞれ接続さ
れ、これらの各抵抗の他端は共通接続された上でコンデ
ンサＣ１を介して接地される。同様にＦＥＴのゲートに
は抵抗Ｒ３１〜Ｒ３ｎ，Ｒ４１〜Ｒ４ｎの一端がそれぞ
れ接続され、これらの抵抗の他端は共通接続された上で
コンデンサＣ１，Ｃ２を介して接地される。On the other hand, the gate of each FET has a bias resistance R
The bias power source Vg is connected to the transformer T1 via 11 to R1n and R21 to R2n, and via the transformer T1.
Connected to. The input signal S1 is also input through the transformer T1. Furthermore, the resistance R is applied to the gate of each FET.
One end of each of 11 to R1n and R21 to R2n is connected, and the other end of each of these resistors is connected in common and then grounded via a capacitor C1. Similarly, one ends of the resistors R31 to R3n and R41 to R4n are respectively connected to the gate of the FET, and the other ends of these resistors are commonly connected and grounded via the capacitors C1 and C2.
【００１１】この構成においては、図２（ａ）のような
入力信号Ｓ１がトランスＴ１を介して各ＦＥＴに入力さ
れる。又、バイアス電源Ｖｇは図２（ｂ）のように、前
記入力信号Ｓ１に対応してトランスＴ１を通してＦＥＴ
のゲートにバイアス電圧として印加される。そして、こ
のＦＥＴ増幅回路では、高周波的にみれば、各ＦＥＴの
ゲートには接地との間に抵抗が接続されることになるた
め、図４で説明した理由によってＦＥＴの周波数帯域を
広げることが可能となる。In this structure, the input signal S1 as shown in FIG. 2A is input to each FET via the transformer T1. Further, as shown in FIG. 2B, the bias power source Vg is an FET through a transformer T1 corresponding to the input signal S1.
Is applied as a bias voltage to the gate of the. In this FET amplifier circuit, in terms of high frequency, a resistor is connected to the gate of each FET between the gate and the ground, so that the frequency band of the FET can be widened for the reason described in FIG. It will be possible.
【００１２】一方、バイアス電源は抵抗Ｒ１１〜Ｒ１
ｎ，Ｒ２１〜Ｒ２ｎを通して各ＦＥＴのゲートにバイア
ス電圧を与え、このとき接地との間に接続した抵抗Ｒ３
１〜Ｒ３ｎ，Ｒ４１〜Ｒ４ｎを流れるが、これら抵抗の
他端はコンデンサＣ１，Ｃ２を介して接地されているた
め、直流的には遮断されており、したがってバイアス電
力は殆ど消費されなくなる。更に、この実施例では入力
信号としてのパルスが入力されるときのみバイアス電源
を供給しているので、消費電力を更に抑制することがで
きる。On the other hand, the bias power source is composed of resistors R11 to R1.
A bias voltage is applied to the gate of each FET through n, R21 to R2n, and at this time, a resistor R3 connected to the ground
1 to R3n, R41 to R4n, but the other ends of these resistors are grounded via the capacitors C1 and C2, and thus are cut off in terms of direct current, so that the bias power is hardly consumed. Further, in this embodiment, since the bias power supply is supplied only when the pulse as the input signal is input, the power consumption can be further suppressed.
【００１３】したがって、ＦＥＴの周波数帯域を広げる
とともにＦＥＴのゲートバイアス電源容量を殆ど必要と
しないパルス増幅回路が構成される。尚、コンデンサＣ
１，Ｃ２は使用周波数において十分にインピーダンスが
小さいものとする。又、図１に示す抵抗Ｒ３１〜Ｒ３
ｎ，Ｒ４１〜Ｒ４ｎは高周波に対して抵抗として機能す
るインダクタンスに置き換えてもよい。Therefore, a pulse amplifier circuit is constructed which widens the frequency band of the FET and requires almost no gate bias power supply capacity of the FET. The capacitor C
It is assumed that 1 and C2 have sufficiently low impedance at the used frequency. Further, the resistors R31 to R3 shown in FIG.
n and R41 to R4n may be replaced with an inductance that functions as a resistance against a high frequency.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、並列に接
続された多数個のＦＥＴの各ゲートにそれぞれ抵抗又は
インダクタンスの一端を接続し、これら抵抗又はインダ
クタンスの他端を一括接続した上でコンデンサを通して
接地しているので、ＦＥＴ増幅回路の周波数帯域を広げ
る一方で、低消費電力化を実現することができる効果が
ある。As described above, according to the present invention, one end of a resistance or inductance is connected to each gate of a large number of FETs connected in parallel, and the other ends of these resistances or inductances are collectively connected. Since it is grounded through the capacitor, there is an effect that the frequency band of the FET amplifier circuit can be widened and the power consumption can be reduced.
【図１】本発明のＦＥＴ増幅回路の一実施例の回路図で
ある。FIG. 1 is a circuit diagram of an embodiment of an FET amplifier circuit of the present invention.
【図２】入力信号とバイアス電源の信号波形図である。FIG. 2 is a signal waveform diagram of an input signal and a bias power supply.
【図３】ＦＥＴ増幅回路の基本回路及びその等価回路図
である。FIG. 3 is a basic circuit of an FET amplifier circuit and its equivalent circuit diagram.
【図４】ＦＥＴ増幅回路の他の回路及びその等価回路図
である。FIG. 4 is another circuit of the FET amplifier circuit and its equivalent circuit diagram.
【図５】ＦＥＴ増幅回路のバイアス回路の回路図であ
る。FIG. 5 is a circuit diagram of a bias circuit of an FET amplifier circuit.
Ｑ１１〜Ｑ１ｎ，Ｑ２１〜Ｑ２ｎ ＦＥＴ Ｒ１１〜Ｒ１ｎ，Ｒ２１〜Ｒ２ｎ バイアス抵抗 Ｒ３１〜Ｒ３ｎ，Ｒ４１〜Ｒ４ｎ 周波数帯域拡大用の
抵抗 Ｃ１，Ｃ２ コンデンサQ11 to Q1n, Q21 to Q2n FETs R11 to R1n, R21 to R2n Bias resistors R31 to R3n, R41 to R4n Frequency band expansion resistors C1, C2 Capacitors
Claims (1)
ス増幅回路において、各ＦＥＴのゲートにそれぞれ抵抗
又はインダクタンスの一端を接続し、これら抵抗又はイ
ンダクタンスの他端を一括接続するとともに、コンデン
サを通して接地したことを特徴とするＦＥＴ増幅回路。1. In a pulse amplification circuit using a large number of FETs in parallel, one end of a resistance or an inductance is connected to the gate of each FET, the other ends of these resistances or inductances are connected together, and grounded through a capacitor. An FET amplifier circuit characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07304192A JP3148841B2 (en) | 1992-02-26 | 1992-02-26 | FET amplification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07304192A JP3148841B2 (en) | 1992-02-26 | 1992-02-26 | FET amplification circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05243862A true JPH05243862A (en) | 1993-09-21 |
| JP3148841B2 JP3148841B2 (en) | 2001-03-26 |
Family
ID=13506890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07304192A Expired - Fee Related JP3148841B2 (en) | 1992-02-26 | 1992-02-26 | FET amplification circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3148841B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556848B2 (en) | 1998-04-27 | 2003-04-29 | Nec Corporation | Power amplifier |
-
1992
- 1992-02-26 JP JP07304192A patent/JP3148841B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556848B2 (en) | 1998-04-27 | 2003-04-29 | Nec Corporation | Power amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3148841B2 (en) | 2001-03-26 |
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