JPH05243567A - Mis type transistor element - Google Patents

Abstract

PURPOSE:To enhance the transistor characteristics by providing a monocrystal insulation film of cubic system or tetragonal system formed as a gate insulation film by heteroepitaxial growth on a monocrystal silicon substrate and by setting the difference less than 3 % between its lattice constant and that of the monocrystal silicon substrate. CONSTITUTION:A monocrystal insulation layer 102 of cubic system or tetragonal system formed by the heteroepitaxial growth and having a lattice constant coinciding with that of the monocrystal substrate 101 is provided on a silicon monocrystal substrate 101. A gate wiring layer 103 is provided on the monocrystal insulation layer 102. Composition of the monocrystal insulation layer 102 is (Y2O3)m (ZrO2)n (m=0.09, n=1-m) or (CaF2)m (CdF2)n (m=0.58, n=1-m). By doing this, a decrease in degree of movement of the transistor element and deterioration of switching characteristics can be reduced and the characteristics can be enhanced.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to the field of MIS type transistor devices.

[0002]

2. Description of the Related Art As a gate insulating film for forming a MIS transistor on a single crystal semiconductor substrate, an amorphous silicon oxide film, a silicon nitride film, a combination of a silicon oxide film and a silicon nitride film, or a dielectric constant is used. Of PZT [Pb (Zi, Ti) O, which has a higher crystallinity than the silicon oxide film
₃ ], LiNbO ₃ , BaMgF ₄ , SrTiO ₃ , Bi ₄
There is Ti ₃ O _12, TaOx, or the like. Further, an optical modulator provided with a MgAl ₂ O ₄ film or a laminated film of MgAl ₂ O ₄ film and MgO on a single crystal silicon substrate and further provided with a ferroelectric band film having an electro-optical effect (Japanese Patent Laid-Open No. 62- 39825), a substrate for a dielectric thin film device in which an MgAl ₂ O ₄ film and a Pt epitaxial film are formed on a silicon substrate, and a dielectric film having a perovskite structure is further formed (JP-A-63-
55198), CaF ₂ and SrF ₂ were epitaxially grown on a silicon single crystal, and a PbTiO ₃ film was formed thereon with good orientation [JJAP vol, 24 (19
85) Supplement 24-2, pp619-6
21] etc. One of electronic active devices constructed on a single crystal semiconductor substrate is a MIS transistor, and when a silicon oxide film is used for an insulating layer, it is called a MOS transistor. To date, much research has been conducted on the interface between the oxide film and the semiconductor in the history of the development of this MOS transistor. Among them, there are many levels called interfacial levels that adversely affect device characteristics at the interface between the oxide film and the semiconductor, and it is well known that the levels adversely affect the operation of the MOS transistor. ing. Most of the cause of the formation of the interface state is that the silicon oxide film is formed by thermal oxidation of the silicon single crystal substrate in an oxygen atmosphere, but it is an essentially amorphous oxide film, and therefore the single crystal is formed. There are many dangling bonds (dangling bonds) at the interface between the and amorphous, and this is due to the existence thereof. In order to solve this problem, it has been generally practiced to reduce the interface state by terminating the dangling bond with an atom such as hydrogen. However, depending on this method, hydrogen atoms once bonded to dangling bonds are desorbed by heat treatment, or new formation of dangling bonds due to lattice defects in a single crystal substrate newly generated by a heat treatment process that is continuously performed. As a result, it was extremely impossible to significantly reduce the interface state. Further, in recent years, the device size has been greatly reduced, and accordingly, the gate insulating film has been made thinner, and the power supply voltage tends to be reduced as the thickness is reduced. However, when a silicon oxide thin film is used as a gate insulating film, when a voltage required to form a channel of a transistor is applied, gate leakage occurs or dielectric breakdown occurs, and there is a limit to thinning.
This is because the silicon oxide film has a relatively low dielectric constant of 4, and conventionally, in order to solve this problem, a high dielectric constant T
Ferroelectric materials such as aO ₂ and Pb (Zi, Ti) O ₃ have been used for the gate insulating film. However, since the gate insulating film of these ferroelectric materials is also formed by the MOCVD method or the sputtering method, many interface states exist at the interface with the silicon surface.

[0003]

It is an object of the present invention to solve the above-mentioned problems of interface states and to provide a high performance MIS transistor element.

[0004]

According to the present invention, a MIS (Metal Insulator Semiconductor) having a single crystal insulating layer, a gate electrode, a source / drain portion, etc. on a silicon single crystal substrate.
In the transistor type transistor device, the gate insulating film is a single crystal insulating layer formed by heteroepitaxial growth on a single crystal silicon substrate, the single crystal is cubic or tetragonal, and the lattice constant is silicon single crystal. The present invention relates to a MIS type transistor which is the same as that of a crystal substrate.

The structure of the MIS type transistor of the present invention will be described with reference to FIG. FIG. 1 shows the MI of the present invention.
The basic structure of an S-type transistor is shown. The silicon single crystal substrate 101 is a silicon single crystal substrate having a thickness of 350 μm to 850 μm, preferably 400 μm to 600 μm, and a plane orientation of (100) or (111). The plane orientation is determined by the kind of material of the single crystal insulator to be heteroepitaxially grown. On the silicon single crystal substrate, a cubic or tetragonal single crystal insulating layer 102 having a thickness of 50Å to 2000Å, preferably 100Å to 1000Å and a lattice constant of 5.430Å which matches that of the single crystal substrate is provided. The lattice constant of the layer has zero mismatch with the lattice constant of silicon. The single crystal insulating layer is formed by MOCVD, sputtering, MBE.
Method, ALE method, EB vapor deposition method, or a method combining these means. Examples of the material of the single crystal insulating layer include a mixed crystal including a fluoride, an oxide, and the like, and YSZ (Ytria-Stabilized).
Zirconia), (Ca, Cd) F ₂ etc.,
The material is not limited to these, and any mixed crystal having a lattice constant matching that of a silicon single crystal may be used. A gate wiring layer 103 is present on the single crystal insulating layer 102. The gate wiring layer 103 is made of doped poly-silicon, aluminum metal, or other material, and has a thickness of 1000 Å by a vapor deposition method, a CVD method, a sputtering method, or the like.
It is formed in a thickness of 1 μm, preferably 2000 Å to 5000 Å. Source / drain portions 104 of the transistor are present on the gate wiring layer 103. In the N-channel transistor, the source / drain portions are formed by the ion implantation method, the vapor phase diffusion method, the coating diffusion method, or the like with a high concentration of group 5 atoms (P, As, Sb) in the periodic table, and the P channel. In the transistor, a group 3 atom (B, Al, Ga, In) in the periodic table is doped at a high concentration by an ion implantation method, a vapor phase diffusion method, a coating diffusion method, or the like.

Next, a specific structure of the MIS transistor of the present invention and a manufacturing method thereof will be described as an embodiment based on FIGS. 2 and 3. Example 1 will be described with reference to FIG. A silicon single crystal substrate 201 has a p-type plane orientation (100) and a resistivity of 10 to 10.
It is a substrate of 15 Ω · cm. This substrate is separated into elements by the LOCOS method. The thickness of the field oxide film 202 is 5000Å. Next, in order to remove the natural oxide film on the substrate 201, the substrate was treated with an HF solution for 1 minute. The processed substrate 201 is set in the vacuum chamber, and the substrate temperature is set to 800.
(Y ₂ O ₃ ) by electron beam evaporation (EB evaporation) method at ℃
The m (ZrO ₂ ) n (n = 1-m) film was heteroepitaxially grown to a film thickness of 300Å. O during epitaxial growth
₂ at a flow rate of ₂ sccm to make the atmosphere an O ₂ atmosphere.
A single crystal insulating film 203 was obtained by EB vapor-depositing r, YO, or Y in an oxidizing atmosphere. However, the portion 203-1 grown on the field oxide film 202 was polycrystalline. The single crystal insulating film 203 obtained here is (Y
₂ O ₃ ) m (ZrO ₂ ) n, and m = 0.09, n = 1.
When −m, the lattice constant was the same as that of Si. It was evaluated by an X-ray diffractometer whether or not the lattice constants of silicon were the same, and it was confirmed by RHEED that it was a cubic crystal. The growth rate of this single crystal insulating film 203 is 4 nm / mi.
It was n. A single crystal Si substrate 201 and a single crystal insulating film 203 (Y ₂ O ₃ ) m (ZrO ₂ ) heteroepitaxially grown.
₂ ) As a result of measuring Qusi-CV in order to evaluate the interface state with n (m = 0.09, n = 1-m), the interface state density was 5 × 10 ⁹ cm ⁻² · ev ^−1. Met. This value is
2 × 10 ¹⁰ cm of the interface level of the conventional Si-SiO ₂ interface
It was found that the value was better than ^-2 · ev ⁻¹ .
Further, when the dielectric constant is calculated at the same time, a value of 18 is obtained.
A value more than 4 times higher than that of 4 in ₂ was obtained. Next, the doped poly-silicon 204 is deposited by LPCVD at a substrate temperature of 625 ° C. and a pressure of 0.5 Torr for 300 times.
0Å accumulated. After that, patterning was performed using a normal photolithography method, and etching was performed by RIE by self-alignment to form a MIS type transistor structure. After that, 1 × 10 ¹⁷ phosphorus is used by using an ion implantation method.
cm ⁻² implantation to form source / drain regions 205,
Activation annealing was performed at 900 ° C. for 30 minutes. Finally, Al metal wiring 206 was formed and completed. The transistor size is W / L = 40/10 μm. When the completed single device was measured, it was found that the subthreshold characteristic in the Vg-Id characteristic was good, and it was 40 mV / dec.
It was ade. In case of conventional MOS transistor,
Table 1 shows the sub-threshold characteristics and the interface state density when the gate insulator of the MIS transistor of the present invention is used. It should be noted that the lower the subthreshold characteristic value is, the lower the interface state is, and it is understood that the MIS transistor of the present invention has a better subthreshold characteristic as compared with the conventional MOS transistor.

Second Embodiment Another embodiment of the present invention will be described with reference to FIG. The silicon single crystal substrate 301 is a substrate having an n-type plane orientation (111) and a resistivity of 20 to 30 Ωcm. This substrate is separated into elements by the usual LOCOS method. Field oxide film 3
The thickness of 02 is 6000Å. Next, the substrate was treated with an HF solution for 1 minute to remove the native oxide film on the substrate. Set the processed substrate in the vacuum chamber and set the degree of vacuum to 1 × 10.
^{-Evacuate to -11} Torr, and at substrate temperature 600 ℃ (Ca
F ₂ ) m (CdF ₂ ) n (n = 1-m) film with a film thickness of 500Å
Heteroepitaxial growth was performed. CaF ₂ and CdF ₂ were used as raw materials for the epitaxially grown film, and at the same time, electrons from the EB gun were irradiated, and the electron beam emission currents were adjusted to control the composition. As a result, a single crystal insulating film 303 was obtained. However, the portion 303-1 grown on the field oxide film was polycrystalline. The single crystal insulating film 303 obtained here is (CaF ₂ ) m (Cd
F ₂ ) n, and when m = 0.58 and n = 1-m, Si
The lattice constants of and were in agreement. Whether or not the lattice constants of Si match with each other was evaluated by an X-ray diffractometer, and RHEED
It was confirmed to be cubic by. The growth rate of the single crystal insulating film 303 was 50 Å / min. A single crystal insulating film 303 (CaF ₂ ) m (CdF ₂ ) n (m = 0.
58, n = 1-m) to evaluate the interface state
As a result of measuring si-CV, the interface state density was 6 × 10 ^9.
It was cm ^-2 , ev ^-1 . This value is
It was found that the value was better than the interface level of the O ₂ interface of 2 × 10 ¹⁰ cm ^-2 , ev ^-1 . Then doped po
The substrate temperature of ly-silicon 304 was set to 6 by LPCVD.
3500Å was deposited at 25 ° C and a pressure of 0.5 Torr. After that, patterning was performed using a normal photolithography method, and etching was performed by RIE by self-alignment to form a MIS type transistor structure. After that, 1 × 10 ¹⁷ cm ^{−2 of} boron is implanted by using the ion implantation method,
A source / drain region 305 was formed and activation annealing was performed at 900 ° C. for 30 minutes. Finally, Al metal wiring 306
Was completed. Transistor size is W / L = 60
/ 5 μm. When the completed single element was measured, the subthreshold characteristic in the Vg-Id characteristic was good, and it was 53 mV / decade.
Sub-threshold characteristics in the case of the conventional MOS transistor, in the case of using the gate insulator of the MIS type transistor of the present invention, and in sub-threshold characteristics of the case of using the gate single crystal insulator of the MIS type transistor of the present invention Table 2 shows the interface state density. It should be noted that the lower the sub-threshold characteristic, the lower the interface state, and the MIS transistor of the present invention has a better sub-threshold characteristic than the conventional MOS transistor.

[Table 1]

[Table 2]

In the MIS type transistor device of the present invention, the gate insulating layer is a single crystal insulating layer heteroepitaxially grown from the single crystal silicon substrate, and its lattice constant matches the lattice constant of the single crystal silicon substrate. As a result, dangling bonds are significantly reduced, and thus the interface state density is significantly reduced. Therefore,
It is possible to improve transistor characteristics by reducing mobility of transistor elements, deterioration of switching characteristics, and the like.

[Brief description of drawings]

FIG. 1 is a model cross-sectional view showing the basic structure of a MIS transistor of the present invention.

FIG. 2 is a cross-sectional view schematically showing each manufacturing process of the MIS type transistor of one embodiment of the present invention.

FIG. 3 is a model cross-sectional view showing each manufacturing process of the MIS transistor of another embodiment of the present invention.

[Explanation of symbols]

101 Silicon Single Crystal Substrate 102 Single Crystal Insulating Layer 103 Gate Electrode 104 Source / Drain 201 Silicon Single Crystal Substrate 202 Field Oxide Film 203 Single Crystal Insulating Film (Y ₂ O ₃ ) m (ZrO ₂ ) n (m = 0.09 , N = 1-
m) 204 doped poly-silicon gate 205 source / drain region 206 Al metal wiring 301 silicon single crystal substrate 302 field oxide film 303 single crystal insulating film (CaF ₂ ) m (CdF ₂ ) n (m = 0.52, n = 1-
m) 303-1 polycrystalline insulating film _{(CaF 2) m (CdF 2} ) n (m = 0.52, n = 1-
m) 304 doped poly-silicon gate 305 source / drain region 306 Al metal wiring

Claims (4)

[Claims] 1. A MIS using a silicon single crystal substrate as a base material.
(Metal Insulator Semiconductor
In the transistor type transistor device, the gate insulating film is a single crystal insulating layer formed by heteroepitaxial growth on a silicon single crystal substrate, and the single crystal is a cubic crystal or a tetragonal crystal. A MIS type transistor device characterized in that the difference from the lattice constant of the crystal substrate is 3% or less. 2. The MIS transistor element according to claim 1, wherein the single crystal layer insulating layer and the single crystal substrate have the same lattice constant. 3. The composition of the single crystal of the single crystal insulating layer is:
_{(Y 2 O 3) m (} ZrO 2) n (m = 0.09, n = 1-
m) The MIS type transistor device according to claim 1. 4. The composition of the single crystal of the single crystal insulating layer is:
_{(CaF 2) m (CdF 2} ) n (m = 0.58, n = 1-
m) The MIS type transistor device according to claim 1.