JPH05243530A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To provide a non-volatile semiconductor memory which has a small occupied area and makes it possible to realize a device of large capacity. CONSTITUTION:A memory has a cell including a drain diffusion layer, a source diffusion layer, a floating gate, a control gate and a select gate which are formed on an Si monocrystalline substrate. A word line 32 is formed by connecting the control gate crosswise. A select line 33 is formed by connecting the select gate lenghwise. A bit line 37 is formed by connecting the drain diffusion layer common to an adjacent two-bit cell between the lengthwise cells. In a memory cell array, the word line 32 and the select line 33 are mutually crossed. And a current flowing between the source and the drain of a cell flows parallel to the word line 32 and orthogonally to the bit line 37.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory having an erasing select gate.

[0002]

2. Description of the Related Art Conventionally, R is an electrically rewritable data.
As an OM (Read Only Memory), various so-called flash E ² PROMs (Electrical Erasable and Programabl) are used.
e ROM) memory cells have been proposed. Among them, "I
DEM 1989 25.7.1 "p. The side wall type flash E ² PROM cells described in detail in 603 to 606 require an internal voltage boosting circuit, but are a promising method as a memory cell capable of writing and erasing data with an external 5V single power supply. Is.

Such a sidewall flash E
The cross-sectional structure of the ² PROM cell is shown in FIG. In the E ² PROM cell shown in the figure, a floating gate 13 made of polycrystalline silicon is provided on a Si single crystal substrate 11 via a gate oxide film 12 having a film thickness of about 50 to 150 Å, and an insulating film is further formed on the floating gate 13. A control gate 15 made of, for example, polycrystalline silicon, which is capacitively coupled via the film 14, is provided.

The side wall type select gate 18 made of the same polycrystalline silicon as these gate materials is used.
Are provided on the Si single crystal substrate 11 via the insulating film 16. At this time, the select gate 18 is provided only on one side of the floating gate 13 and the control gate 15 with the floating gate 1 interposed via the insulating film 17.
3 and the control gate 15 in a self-aligned manner.

Further, the drain diffusion layer 19 is arranged on the surface of the Si single crystal substrate 11 on the side below the floating gate 13 and the control gate 15 and where the select gate 18 does not exist, and the select gate 18 is formed. The source diffusion layer 20 is arranged on the surface of the existing Si single crystal substrate 11.

An example of electrical operation of the sidewall flash E ² PROM cell having the above structure will be described below in the case of NMOS. In writing data in this structure, the Si single crystal substrate 11 is grounded, the source bias voltage Vs of the source diffusion layer 20 is set to 0 v, and the select bias voltage Vsel of the select gate 18 is set to 1.5 v.
Then, the control bias voltage V _CG of the control gate 15 is set to 17 v, and 5 v is applied to the drain diffusion layer 19 as the drain bias voltage V _D.

Under such a bias, an avalanche phenomenon occurs on the surface of the Si single crystal substrate 11 below the boundary between the select gate 18 and the floating gate 13, and hot electrons 21 are generated and injected into the floating gate 13. Then, the write operation is completed.

To erase data, for example, the V _D is 14 v, the V _CG is 0 v, and the Vsel is 0 v.
Are applied to bring Vs into an open state. Under such a voltage application condition, the floating gate 13
A Fowler-Nordheim tunnel current 22 that flows through the gate oxide film 12 flows between the drain diffusion layer 19 and the drain diffusion layer 19, and electrons stored in the floating gate 13 are extracted, thereby erasing data.

The case where the data write operation is performed by hot electron injection utilizing the avalanche phenomenon has been exemplified, but by applying 22v to V _CG and 0v0 to V _D , the erase The write operation can also be performed by flowing a Fowler-Nordheim tunnel current passing through the gate oxide film 12 in the opposite direction.

The above sidewall flash E ² P
FIG. 6 shows a planar state when a large number of ROM cells are arranged to form an actual memory cell array. In the figure, the control gate 15 is laterally connected to form a word line 32, and the select gate 18 is adjacently connected to the word line 32 in the same direction to form a select line 33.

The drain diffusion layer 19 is shared by two adjacent cells and is connected to a metal wiring such as Al via a contact 35. The metal wiring extends in the vertical direction so as to connect a large number of cells. , Bit lines 31 are formed.
Similarly, the source diffusion layer 20 is also shared by the two cells, and both are connected in the lateral direction.

In the memory cell array thus constructed, the region 40 (the portion indicated by the dotted line in FIG. 6) where the word line 32, the select line 33 and the bit line 31 intersect becomes a 1-bit cell. In FIG. 6, the portion surrounded by the diagonal lines is the floating gate 13, and the portion surrounded by the solid lines 34 is the element isolation region.

The sidewall type flash E ² PROM cell configured as described above has the following advantages in addition to the advantages described above.
Even when the cell V _T becomes negative (depletion) due to over-erasure during data erasing, it is possible to prevent the current from flowing through the bit line 31 by turning off the select gate 18, so that the cell V _T is There is an advantage that the erase operation can be performed without the difficulty of controlling to a narrow range.

However, such a conventional sidewall type flash E ² PROM cell has the technical problems described below, particularly when it is formed into a memory cell array.

[0015]

That is, in the memory cell array shown in FIG. 6, the contact 35 is necessary because the bit line 31 is arranged in parallel to the flow direction of the drain-source current. The area occupied by a 1-bit cell is the area 40 surrounded by the dotted line in the figure, but 1/2 contact 35 is required for each cell.

For this reason, it is necessary to secure a region for 1/2 of the contacts 35 and a margin region for mask matching between the contacts 35 and the word lines 32.
There is a problem that it occupies a large area and is not suitable for constructing a large capacity memory device.

For example, when the 0.5 μm rule is adopted, the 1-bit cell occupation area is, for example, 1.8 ×
2.5 = 4.5 μm ² , which can be realized with a 16 Mbit device, but with a 32 Mbit device, the chip size was 150 mm ² or more, which was impossible to realize.

The present invention has been made in view of the above conventional problems, and the object thereof is to:
An object is to provide a nonvolatile semiconductor memory that occupies a small area and can realize a large-capacity device.

[0019]

In order to achieve the above object, the present invention provides a drain diffusion layer and a source diffusion layer formed on a Si single crystal substrate, and a floating layer formed on the substrate via an insulating film. In a nonvolatile semiconductor memory including a cell including a gate and a control gate, and a select gate formed on the side of the floating gate, the drain diffusion layer includes a drain-
The bit lines of the memory cell array, in which a large number of cells are integrated, are connected to each other by connecting adjacent cells along a direction orthogonal to the flow direction of the source-to-source current.

In the above semiconductor memory, the control gate is connected to adjacent cells along a direction parallel to the flow direction of the drain-source current to form a word line of the memory cell array and the source. The diffusion layers are connected to each other between adjacent cells along a direction orthogonal to the flow direction of the drain-source current to form a source line of the memory cell array, and the select gate is connected to the drain-source current line. The cells are connected to each other adjacent to each other along a direction orthogonal to the flow direction, and are formed as select lines of the memory cell array, and the word lines and the source lines, select lines, and bit lines are orthogonal to each other. be able to.

[0021]

In the nonvolatile semiconductor memory having the above structure,
Since the bit line is formed by connecting the drain diffusion layers to each other between adjacent cells along the direction orthogonal to the direction of the current flowing between the drain and the source, the drain diffusion layer and the metal wiring are connected to each other. No need for contacts.

[0022]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following description, parts that are the same as or correspond to those in the conventional example described above are given the same reference numerals. FIG. 1 is a schematic sectional view of a sidewall flash E ² PROM cell according to the present invention.
The cell shown in the figure has a thickness of 5 on the Si single crystal substrate 11.
Floating gates 13 made of polycrystalline silicon are provided at a predetermined interval with a gate oxide film 12 of about 0 to 150 Å interposed.

Then, a sidewall type select gate 18 made of the same polycrystalline silicon as these gate materials is used.
Are provided on the Si single crystal substrate 11 via the insulating film 16. At this time, the select gate 18 is arranged in one side of the floating gate 13 via the insulating film 17 in a self-aligned manner with the floating gate 13.

A control gate 15 is arranged above the floating gate 13 and the select gate 18 with an insulating film 14 interposed therebetween. Further, a drain diffusion layer 19 is disposed on the surface of the Si single crystal substrate 11 on the side below the floating gate 13 and the control gate 15 and on which the select gate 18 does not exist, and the side on which the select gate 18 exists. The source diffusion layer 20 is arranged on the surface of the Si single crystal substrate 11.

Here, the drain diffusion layer 19 corresponds to the pair of source diffusion layers 20 arranged on both sides. When a memory cell array is composed of sidewall flash E ² PROM cells having such a cross-sectional structure,
A planar shape as shown in FIG. 2 is possible.

In the memory cell array shown in FIG. 2, the word line 32 is formed by connecting a large number of control gates 15 in the horizontal direction in the figure. A select line 33 is formed by connecting a large number of select gates 18 in the vertical direction in FIG. Further, the drain diffusion layer 19 is shared by the two-bit cells that are adjacent to each other in the horizontal direction in FIG. 2 and is connected to a large number of cells that are located in the vertical direction in FIG. )
37 is formed.

Similarly, the source diffusion layer 20 is connected in the vertical direction in parallel with the drain line 37 so that the source line 38 is formed.
Are formed. In the memory cell array thus configured, the region 41 surrounded by the dotted line in FIG. 2 constitutes a 1-bit cell. The hatched portion in FIG. 2 is the floating gate 13, and 34 is an element isolation region. 2 is a sectional view taken along line AA ′ in FIG.
The B ′ cross section is shown in FIG.

In the memory cell array shown in FIG.
In the conventional memory cell array shown in FIG. 1, the word line 32 and the select line 33 are provided in parallel and adjacent to each other, but these are orthogonal to each other. In the case of FIG. 5, the current between the source and drain of the cell is the word line 3
2 flows in a direction orthogonal to 2 but flows in parallel to the word line 32 in the example of FIG.
Flows in a direction orthogonal to.

Next, the electrical operation of the memory cell of the present invention will be described by taking an NMOS as an example. To write data in this structure, the Si single crystal substrate 11 is grounded and the source bias voltage Vs of the source diffusion layer 20 (source line 38) is set to 0.
v, the select bias voltage Vsel of the select gate 18 (select line 33) is 1.5 v, the control bias voltage V _CG of the control gate 15 (word line 32) is 17 v, and the drain diffusion layer 19 (drain line 37) is 5 V is applied as the drain bias voltage V _D.

Under such a bias voltage condition, an avalanche phenomenon occurs on the surface of the Si single crystal substrate 11 below the boundary between the select gate 18 and the floating gate 13, and hot electrons 21 are generated, which causes the floating gate. 13 to complete the write operation.

Data is erased by, for example, 14 V as the V _D , 0 v as the V _CG , and 0 v as the Vsel.
Are applied to bring Vs into an open state. Under such a voltage application condition, the floating gate 13
A Fowler-Nordheim tunnel current 22 that flows through the gate oxide film 12 flows between the drain diffusion layer 19 and the drain diffusion layer 19, and electrons stored in the floating gate 13 are extracted, thereby erasing data.

In this case, also in the present invention, it is possible to write data by the Fowler-Nordheim tunnel current, as in the above-mentioned conventional example. FIG. 4 is an electrically equivalent circuit of the memory cell array shown in FIG.

When a 1-bit memory cell where the word line 32 and the drain line 37 intersect is selected and the information stored in this cell is read out, the word line 32 has 5 bits.
v (V _CG ), drain line 37 1 v (V _D ), source line 38 0 v (Vs), select line 33 5 v (Vse)
The voltage of l) is applied.

At this time, the current flowing between the source line 38 and the drain line 37 changes depending on whether or not electrons are stored in the floating gate 13, so that whether the data is "1" or "0". Can be judged.

In the present invention, as in the conventional example,
Since the sidewall-type select gate 18 is present, it is not necessary to avoid overerasing during the erase operation.

In the memory cell array of the sidewall flash E ² PROM cell having the above structure, the bit line 37 has the drain diffusion layer between the cells adjacent to each other in the direction orthogonal to the flow direction of the drain-source current. 19
Since they are connected to each other, a contact for connecting the drain diffusion layer 19 and the metal wiring is unnecessary.

For this reason, the area of the contact region is reduced, and a spare region for mask alignment between the contact and the word line is not required, and the cell occupying area per bit is very small.

By the way, when the memory cell array is actually constructed according to the 0.5 μm rule, the occupied area of the cell per bit is 1 × 2.5 = 2.5 μm ^2, which is 4.5 as compared with the conventional case.
Approximately half compared to μm ² and 0.5 μm in the conventional method
A 32 Mbit device, which could not be realized by the rule, is sufficiently realized, and if the size is the same, a flash memory having a capacity about twice that of the conventional method can be realized.

[0039]

As described above in detail in the embodiments,
According to the non-volatile semiconductor memory of the present invention, the contact, which is indispensable in the conventional configuration, is unnecessary, so that the occupied area of the contact area and the margin area for mask alignment are unnecessary, and the capacity of the memory cell array can be increased. To be achieved.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a cell of a nonvolatile semiconductor memory according to the present invention.

FIG. 2 is a plan view of a memory cell array in which the same cells are integrated.

3 is a sectional view taken along line B-B ′ of FIG.

FIG. 4 is an electrical equivalent circuit of the memory cell array of FIG.

FIG. 5 is a schematic sectional view of a cell of a conventional nonvolatile semiconductor memory.

6 is a plan view of a memory cell array in which the cells of FIG. 5 are integrated.

[Description of Reference Signs] 11 Si single crystal substrate 12 Gate oxide film 13 Floating gate 15 Control gate 18 Select gate 19 Drain diffusion layer 20 Source diffusion layer 31 Bit line 32 Word line 33 Select line

Claims (2)

[Claims] 1. A drain diffusion layer and a source diffusion layer formed on a Si single crystal substrate, a floating gate and a control gate formed on the substrate via an insulating film, and formed on a side of the floating gate. In the nonvolatile semiconductor memory including a cell including a select gate, the drain diffusion layer is connected to adjacent cells along a direction orthogonal to a flow direction of a drain-source current, and a large number of cells are connected. A non-volatile semiconductor memory comprising: bit lines of a memory cell array in which the above are integrated. 2. The control gate is connected to adjacent cells along a direction parallel to the flow direction of the drain-source current to form a word line of the memory cell array, and the source diffusion layer is formed. Are connected to each other between adjacent cells along a direction orthogonal to the flow direction of the drain-source current to form a source line of the memory cell array, and the select gate is connected to the drain-source current line. The word lines and the source lines, the select lines, and the bit lines are connected to each other along the direction orthogonal to the flow direction to form a select line of the memory cell array and are orthogonal to each other. The non-volatile semiconductor memory according to claim 1, which is characterized in that.