JPH05242778A - Manufacture of semiconductor pressure switch - Google Patents

Manufacture of semiconductor pressure switch

Info

Publication number
JPH05242778A
JPH05242778A JP4165692A JP4165692A JPH05242778A JP H05242778 A JPH05242778 A JP H05242778A JP 4165692 A JP4165692 A JP 4165692A JP 4165692 A JP4165692 A JP 4165692A JP H05242778 A JPH05242778 A JP H05242778A
Authority
JP
Japan
Prior art keywords
silicon substrate
electrode
glass substrate
pressure switch
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4165692A
Other languages
Japanese (ja)
Inventor
Osamu Koseki
修 小関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP4165692A priority Critical patent/JPH05242778A/en
Publication of JPH05242778A publication Critical patent/JPH05242778A/en
Pending legal-status Critical Current

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  • Switches Operated By Changes In Physical Conditions (AREA)

Abstract

PURPOSE:To improve the accuracy and reliability of a pressure switch together with its manufacture at a low cost. CONSTITUTION:A wiring electrode 3 is formed through a process of forming a recessed part 2 by etching and through the diffusion of boron across the inside and the outside of the recessed part 2. A contact electrode 6 and a bonding pad 8 are formed on the inside and the outside of the recessed part 2 respectively. A glass substrate 9 provided with a reference electrode 10 formed on its one face is prepared. After placing, on a heater 15, a silicon substrate, which got through the above machining process, the recessed part 2 of the silicon substrate and the reference electrode 10 formed on the glass substrate 9 are placed thereon in opposition to each other. A diaphagm 11 comprises the glass substrate 9 and the silicon substrate bonded to each other by heating the heater 15 and the recessedly formed face of the silicon substrate etched from the other face thereof.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体圧力スイッチの
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor pressure switch.

【0002】[0002]

【従来の技術】従来の半導体圧力スイッチの製造工程を
図5、図6に沿って説明する。まず、厚み525μm、
N型のシリコン基板1にレジストを塗布し露光、現像を
し、凹部2の形状のレジストが除去されるようにパター
ニングを行う。パターニング終了後、シリコン基板1を
プラズマエッチング装置にいれ、CF4 とO2の混合ガ
スを導入し約70Wの高周波を印加してシリコン基板1
をエッチングし3μmの深さの凹部2を形成する(図5
(a)、(b))。凹部2を形成後、レジストを塗布
し、露光、現像をし、ボロン電極3を形成する部分のレ
ジストが除去されるようにパターニングをし、ボロンの
イオン注入をして、ボロン電極3を形成する(図5
(c)、(d))。
2. Description of the Related Art A manufacturing process of a conventional semiconductor pressure switch will be described with reference to FIGS. First, the thickness is 525 μm,
A resist is applied to the N-type silicon substrate 1, exposed and developed, and patterning is performed so that the resist in the shape of the recess 2 is removed. After the patterning is completed, the silicon substrate 1 is put into a plasma etching apparatus, a mixed gas of CF 4 and O 2 is introduced, and a high frequency of about 70 W is applied to the silicon substrate 1.
Is etched to form a recess 2 having a depth of 3 μm (see FIG. 5).
(A), (b)). After forming the concave portion 2, a resist is applied, exposed and developed, and patterned so that the resist in the portion where the boron electrode 3 is formed is removed, and boron ion implantation is performed to form the boron electrode 3. (Fig. 5
(C), (d)).

【0003】ボロン電極3を形成後、絶縁膜として酸化
膜4を成膜し凹部2に酸化膜4が残るようにパターニン
グをする(図5(e)、(f))。続いて、多結晶シリ
コン5をLPCVDによって成膜し、接点電極6を形成
する部分に多結晶シリコン5が残るようにフッ酸と硝酸
の混合液でエッチングをする(図5(g)、(h))。
After forming the boron electrode 3, an oxide film 4 is formed as an insulating film and patterned so that the oxide film 4 remains in the recess 2 (FIGS. 5E and 5F). Subsequently, the polycrystalline silicon 5 is deposited by LPCVD, and etching is performed with a mixed solution of hydrofluoric acid and nitric acid so that the polycrystalline silicon 5 remains in the portion where the contact electrode 6 is formed (FIGS. 5G and 5H). )).

【0004】次に、接点電極6、配線電極7およびボン
ディングパッド8を形成するためスパッタによってA
u、Crを成膜し、Au、Crをエッチングし接点電極
6、配線電極7およびボンディングパッド8を形成する
(図5(i)、(j))。一方、ガラス基板9にAu、
Crをスパッタし、パターニングして基準電極10を形
成する(図5(k)、(l))。
Next, in order to form the contact electrode 6, the wiring electrode 7 and the bonding pad 8, the sputtering electrode A is used.
u and Cr are deposited and Au and Cr are etched to form the contact electrode 6, the wiring electrode 7 and the bonding pad 8 (FIGS. 5 (i) and 5 (j)). On the other hand, Au on the glass substrate 9
Cr is sputtered and patterned to form the reference electrode 10 (FIGS. 5 (k) and 5 (l)).

【0005】この基準電極10を形成したガラス基板9
とシリコン基板1を接点電極6と基準電極10が向かい
合うようにセットし、ヒータ15上に乗せ(図6
(a))、ヒータ15を約400℃に加熱し、ガラス基
板9に0V、シリコン基板1に約500Vを20分間印
加してシリコン基板1とガラス基板9を陽極接合する。
陽極接合終了後、ガラス基板9と逆側にシリコン窒化膜
12を成膜しダイヤフラムの形状になるように150℃
の燐酸でシリコン窒化膜12をパターニングする(図6
(b))。
Glass substrate 9 on which the reference electrode 10 is formed
And the silicon substrate 1 are set so that the contact electrode 6 and the reference electrode 10 face each other and placed on the heater 15 (see FIG. 6).
(A)), The heater 15 is heated to about 400 ° C., 0 V is applied to the glass substrate 9 and about 500 V is applied to the silicon substrate 1 for 20 minutes to anodic bond the silicon substrate 1 and the glass substrate 9.
After the anodic bonding is completed, a silicon nitride film 12 is formed on the opposite side of the glass substrate 9 to form a diaphragm at 150 ° C.
The silicon nitride film 12 is patterned with phosphoric acid of FIG.
(B)).

【0006】さらに、ボンディングパッド8に耐アルカ
リ性のコーティング剤を塗布し、ダイヤフラム11を形
成するため90℃の水酸化カリウム水溶液(KOH)に
約3.5時間浸漬させシリコン基板1を約500μmエ
ッチングし、厚み22μmのダイヤフラム11を形成
し、さらに、コーティング剤を剥離し圧力スイッチを製
作していた(図6(c))。
Further, an alkali resistant coating agent is applied to the bonding pad 8 and immersed in a potassium hydroxide aqueous solution (KOH) at 90 ° C. for about 3.5 hours to form the diaphragm 11, and the silicon substrate 1 is etched by about 500 μm. Then, the diaphragm 11 having a thickness of 22 μm was formed, and the coating agent was peeled off to manufacture the pressure switch (FIG. 6C).

【0007】[0007]

【発明が解決しようとする課題】しかし、Au−Cr等
の金属によってダイヤフラム上の接点とボロン等の不純
物の拡散による電極の接続をした場合、一応圧力の検出
は可能であるが、ダイヤフラムは大気側の圧力の変化に
伴って随時動くものなので酸化膜4等の膜剥離が発生し
信頼性に課題がある。また、ダイヤフラム上で配線をし
てある部分と配線をしていない部分とでたわみ量に差が
生じ、ダイヤフラムのたわみの均一性が悪く、その結果
精度が悪くなると言う課題があった。
However, when the contact point on the diaphragm and the electrode by diffusion of impurities such as boron are connected by a metal such as Au-Cr, the pressure can be detected for a while, but the diaphragm is in the atmosphere. Since it moves at any time according to the change in the pressure on the side, film peeling of the oxide film 4 and the like occurs and there is a problem in reliability. In addition, there is a problem in that there is a difference in the amount of deflection between a portion on the diaphragm where wiring is provided and a portion where no wiring is provided, the uniformity of the deflection of the diaphragm is poor, and as a result the accuracy is poor.

【0008】[0008]

【課題を解決するための手段】本発明は、上記のような
課題を解決するため、凹部上の接点から大気側への電気
的な接続を金属電極を使わずにボロン等の不純物拡散に
よる電極によって配線するようにしたものである。
In order to solve the above problems, the present invention provides an electrode by diffusion of impurities such as boron for electrical connection from the contact on the recess to the atmosphere side without using a metal electrode. It is designed to be wired by.

【0009】[0009]

【作用】上記のような工程を経て製造することにより、
ダイヤフラム上の配線が金属ではないため膜の剥離の発
生の恐れがなく信頼性が高く、またダイヤフラムのたわ
み量が均一であるため精度のよい半導体圧力スイッチが
提供できる。しかも、金属膜の成膜およびパターニング
等の工程がなくなるため安価にて製作が可能となる。
[Operation] By manufacturing through the above steps,
Since the wiring on the diaphragm is not a metal, there is no risk of peeling of the film and the reliability is high. Further, since the deflection amount of the diaphragm is uniform, an accurate semiconductor pressure switch can be provided. Moreover, since the steps of forming and patterning the metal film are eliminated, the manufacturing can be performed at low cost.

【0010】[0010]

【実施例】本発明に係る半導体圧力スイッチの製造工程
を一実施例として図1、図2に沿って説明する。まず、
厚み525μm、N型のシリコン基板1にレジストを塗
布し露光、現像をし、凹部2の形状のレジストが除去さ
れるようにパターニングを行う。パターニング終了後、
シリコン基板1をプラズマエッチング装置にいれ、CF
4 とO2の混合ガスを導入し約70Wの高周波を印加し
てシリコン基板1をエッチングし3μmの深さの凹部2
を形成する(図1(a)、(b))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a semiconductor pressure switch according to the present invention will be described as an embodiment with reference to FIGS. First,
A resist is applied to the N-type silicon substrate 1 having a thickness of 525 μm, exposed and developed to perform patterning so that the resist having the shape of the recess 2 is removed. After patterning,
Put the silicon substrate 1 in the plasma etching device, and use CF
A mixed gas of 4 and O 2 is introduced, a high frequency of about 70 W is applied, and the silicon substrate 1 is etched to form a recess 2 having a depth of 3 μm.
Are formed (FIGS. 1A and 1B).

【0011】凹部2を形成後、レジストを塗布し、露
光、現像をし、ボロン電極3を形成する部分のレジスト
が除去されるようにパターニングをし、ボロンのイオン
注入をして、ボロン電極3を形成する(図1(c)、
(d))。続いて、接点電極6を形成するためスパッタ
によってAu、Crを成膜し、凹部の中心に接点電極6
が位置するように、また、ボロン電極3の電極取り出し
部に2つのボンディングパッド8が形成されるようにA
u、Crをエッチングする(図1(e)、(f))。一
方、ガラス基板9にAu、Crをスパッタし、パターニ
ングして基準電極10を形成する(図1(g)、
(h))。
After forming the concave portion 2, a resist is applied, exposed and developed, and patterned so that the resist in the portion where the boron electrode 3 is formed is removed, and boron ions are implanted to form the boron electrode 3. (FIG. 1 (c),
(D)). Subsequently, Au and Cr are deposited by sputtering to form the contact electrode 6, and the contact electrode 6 is formed in the center of the recess.
Are positioned so that two bonding pads 8 are formed at the electrode lead-out portion of the boron electrode 3.
u and Cr are etched (FIGS. 1E and 1F). On the other hand, Au and Cr are sputtered on the glass substrate 9 and patterned to form the reference electrode 10 (FIG. 1 (g),
(H)).

【0012】次に、このガラス基板9の基準電極10を
シリコン基板1に形成された接点電極6と向かい合うよ
うにセットし、これらをヒータ15上に乗せ、ヒータ1
5を約400℃に加熱し、ガラス基板9に0V、シリコ
ン基板1に約500Vを20分間印加してシリコン基板
1とガラス基板9を陽極接合する(図2(a))。陽極
接合終了後、シリコン基板1のガラス基板9と接合部の
逆側にシリコン窒化膜12を成膜しダイヤフラムの形状
になるように150℃の燐酸でシリコン窒化膜12をパ
ターニングする(図2(b))。
Next, the reference electrode 10 of the glass substrate 9 is set so as to face the contact electrode 6 formed on the silicon substrate 1, and these are placed on the heater 15 so that the heater 1
5 is heated to about 400 ° C., 0 V is applied to the glass substrate 9 and about 500 V is applied to the silicon substrate 1 for 20 minutes to anodic bond the silicon substrate 1 and the glass substrate 9 (FIG. 2A). After the anodic bonding is completed, a silicon nitride film 12 is formed on the opposite side of the glass substrate 9 and the bonding portion of the silicon substrate 1, and the silicon nitride film 12 is patterned with phosphoric acid at 150 ° C. so as to have a diaphragm shape (see FIG. b)).

【0013】さらに、ボンディングパッド8に耐アルカ
リ性のコーティング剤16を塗布し、90℃の水酸化カ
リウム水溶液(KOH)に約3.5時間浸漬させシリコ
ン基板1を約500μmエッチングし、厚み22μmの
ダイヤフラム11を形成し、コーティング剤を剥離しス
イッチの製作した(図2(c))。このスイッチの平面
図、断面図を図3及び図4に示す。
Further, an alkali resistant coating agent 16 is applied to the bonding pad 8 and immersed in a potassium hydroxide aqueous solution (KOH) at 90 ° C. for about 3.5 hours to etch the silicon substrate 1 by about 500 μm, and a diaphragm with a thickness of 22 μm. 11 was formed and the coating agent was peeled off to manufacture a switch (FIG. 2C). A plan view and a sectional view of this switch are shown in FIGS.

【0014】この製作した半導体圧力スイッチを圧力容
器にいれ、加圧して2つのボンディングパッド8の間の
導通を確認をした結果、2.0kg/cm2で導通が確認でき
た。さらに加圧測定を100回繰り返し、導通する圧力
のばらつきを測定したところ、すべての圧力が±0.0
25kg/cm2以内に入っていた。また、加圧を20万回行
っても破壊等は起こらず、導通する圧力の値の変動はな
かった。
The manufactured semiconductor pressure switch was put in a pressure vessel and pressurized to confirm the conduction between the two bonding pads 8. As a result, the conduction could be confirmed at 2.0 kg / cm 2 . Further, the pressure measurement was repeated 100 times to measure the variation in the conducted pressure, and all the pressures were ± 0.0
It was within 25 kg / cm 2 . Further, even if the pressurization was performed 200,000 times, no breakage or the like occurred, and there was no change in the value of the conducting pressure.

【0015】このように、この発明に係る方法によっ
て、精度が良く耐久性等の信頼性の高い半導体圧力スイ
ッチが製作できる。
As described above, according to the method of the present invention, a semiconductor pressure switch having high accuracy and high reliability such as durability can be manufactured.

【0016】[0016]

【発明の効果】この発明は、凹部上の接点から大気側へ
の電気的な接続をボロン等の不純物拡散による電極で行
い、金属の配線ではないため、電極膜の剥離の発生の恐
れがなく信頼性が高く、また、ダイヤフラムのたわみ量
が均一であるため精度のよい半導体圧力スイッチが提供
できる。しかも、金属膜の成膜およびパターニング等の
工程がなくなるため安価にて製作が可能となる。
According to the present invention, the electrical connection from the contact on the concave portion to the atmosphere side is performed by the electrode by the diffusion of impurities such as boron, and since it is not a metal wiring, there is no risk of peeling of the electrode film. A highly reliable semiconductor pressure switch can be provided because it is highly reliable and the amount of deflection of the diaphragm is uniform. Moreover, since the steps of forming and patterning the metal film are eliminated, the manufacturing can be performed at low cost.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体圧力スイッチの製作手順を示す
工程図である。
FIG. 1 is a process drawing showing a manufacturing procedure of a semiconductor pressure switch of the present invention.

【図2】本発明の半導体圧力スイッチの製作手順を示す
工程図である。
FIG. 2 is a process drawing showing a manufacturing procedure of the semiconductor pressure switch of the present invention.

【図3】本発明の半導体圧力スイッチの平面図である。FIG. 3 is a plan view of the semiconductor pressure switch of the present invention.

【図4】本発明の半導体圧力スイッチの断面図である。FIG. 4 is a sectional view of a semiconductor pressure switch of the present invention.

【図5】従来の半導体圧力スイッチの製作手順を示す工
程図である。
FIG. 5 is a process drawing showing a manufacturing procedure of a conventional semiconductor pressure switch.

【図6】従来の半導体圧力スイッチの製作手順を示す工
程図である。
FIG. 6 is a process diagram showing a manufacturing procedure of a conventional semiconductor pressure switch.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 凹部 3 ボロン電極 6 接点電極 9 ガラス基板 10 基準電極 1 Silicon Substrate 2 Recess 3 Boron Electrode 6 Contact Electrode 9 Glass Substrate 10 Reference Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板の一方の面にエッチングに
より凹部を形成する工程と、該凹部内外にわたって前記
シリコン基板に不純物を拡散させて配線電極を形成する
工程と、前記凹部内に形成された配線電極の上面に接点
電極を形成するとともに前記配線電極の凹部外にボンデ
ィングパッドを形成する工程と、片面に基準電極を形成
したガラス基板を準備する工程と、前記加工工程を経た
シリコン基板をヒータ上に載置した後、該シリコン基板
の凹部とガラス基板に形成された基準電極とを対向させ
て載置する工程と、前記ヒータの加熱によりガラス基板
とシリコン基板とを接合する接合工程と、前記シリコン
基板の凹部形成面をその他方の面よりエッチングしてダ
イヤフラムに加工する工程と、からなる半導体圧力スイ
ッチの製造方法。
1. A step of forming a recess on one surface of a silicon substrate by etching, a step of diffusing impurities into the silicon substrate to form a wiring electrode over the inside and outside of the recess, and a wiring formed in the recess. A step of forming a contact electrode on the upper surface of the electrode and a bonding pad outside the recess of the wiring electrode, a step of preparing a glass substrate having a reference electrode formed on one side, and a silicon substrate that has undergone the processing step above the heater. The step of placing the concave portion of the silicon substrate and the reference electrode formed on the glass substrate so as to face each other, and the step of joining the glass substrate and the silicon substrate by heating the heater, A method of manufacturing a semiconductor pressure switch, comprising the steps of etching a surface of a silicon substrate on which a recess is formed from the other surface to form a diaphragm.
JP4165692A 1992-02-27 1992-02-27 Manufacture of semiconductor pressure switch Pending JPH05242778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4165692A JPH05242778A (en) 1992-02-27 1992-02-27 Manufacture of semiconductor pressure switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4165692A JPH05242778A (en) 1992-02-27 1992-02-27 Manufacture of semiconductor pressure switch

Publications (1)

Publication Number Publication Date
JPH05242778A true JPH05242778A (en) 1993-09-21

Family

ID=12614415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4165692A Pending JPH05242778A (en) 1992-02-27 1992-02-27 Manufacture of semiconductor pressure switch

Country Status (1)

Country Link
JP (1) JPH05242778A (en)

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