JPH05242683A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve integration density by decreasing occupancy area without reducing amplification factor. CONSTITUTION:When a pre-stage control signal 12 is selected, a P channel MOS loading means 1 and a pre-stage N channel MOS differential amplifying means 2 perform amplifying operation with the third complementary signal 4, 5 as an input signal and with the second complementary signal 6B, 7B as an output signal. Further, when a post-stage control signal 13 is selected, the P channel MOS loading means 1 and a post-stage N channel MOS differential amplifying means 3 perform amplifying operation with the second complementary signal 6B, 7B as an input signal and with the fourth complementary signal 10, 11 as an output signal. That is, the P channel MOS loading means 1 and the pre-stage N channel MOS differential amplifying means 2 constitutes the pre-stage sense amplifier, and the P channel MOS loading means 1 and the post-stage N channel MOS differential amplifying means 3 constitutes the post- stage sense amplifier, the P channel MOS loading means 1 is shared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a built-in sense amplifier.

[0002]

2. Description of the Related Art In a read operation, which is a basic operation of a semiconductor memory device, an address signal is first applied to the semiconductor memory device, and then this address signal is decoded to generate a word signal. The stored data is output to the bit line, the bit signal is amplified by the sense amplifier, and finally the output buffer outputs the read data to the outside. Here, the sense amplifier is an amplifier for amplifying a weak read signal from a minute memory cell, that is, a bit signal at high speed, and is an important circuit constituent element of the semiconductor memory device.

In recent years, in semiconductor memory devices that are becoming more and more miniaturized, read signals from memory cells are also becoming weaker, and there is a demand for higher speed of the above-mentioned read operation due to improvement in sense amplifier technology. In response to such a demand, there is a conventional one in which a plurality of independent sense amplifiers are connected in series to obtain a high amplification degree.

[0004]

However, in the conventional semiconductor memory device, each of the sense amplifiers connected in series has an independent CMOS (Complementary Metal Oxide).
Semiconductor) circuit. Each sense amplifier is a P-channel MOS (P-channel Metal Oxide Semicon)
ductor) circuit part and N-channel MOS (N-channel Metal)
Oxide Semiconductor) circuit section and arranged in multiple stages in series, the occupied area becomes very large, which hinders the improvement of the degree of integration of the semiconductor memory device.

In view of the above problems, it is an object of the present invention to provide a semiconductor memory device in which the occupied area is reduced without impairing the amplification degree and the integration degree is improved.

[0006]

A semiconductor memory device according to claim 1 is a P-channel MOS coupled to a first complementary signal.
Front stage N-channel M coupled to the load means, the first complementary signal, the second complementary signal, the third complementary signal and the front stage control signal
An OS differential amplifying means, a second-stage N-channel MOS differential amplifying means coupled to the first complementary signal, the second complementary signal, the fourth complementary signal, and the latter-stage control signal are provided, and the former-stage control is performed. When a signal is selected, the P-channel MOS load means and the preceding-stage N-channel MOS differential amplifying means perform an amplifying operation in which the third complementary signal is input and the second complementary signal is output, and the latter-stage control signal is supplied. When is selected, the P-channel MOS load means and the latter-stage N-channel MOS differential amplifier means perform the amplifying operation in which the second complementary signal is input and the fourth complementary signal is output. is there.

According to another aspect of the semiconductor memory device of the present invention, there is provided P-channel MOS load means coupled to the first complementary signal and the first complementary signal.
First pre-stage N-channel MOS coupled to the complementary signal, the second complementary signal, the third complementary signal, and the first pre-stage control signal
Differential amplifying means, second complementary N-channel MOS differential amplifying means coupled to the first complementary signal, the second complementary signal, the fourth complementary signal, and the second upstream control signal; The second-stage N-channel MOS differential amplifying means coupled to the complementary signal, the second complementary signal, the fifth complementary signal, and the latter-stage control signal is provided, and when the first preceding-stage control signal is selected, ,
P-channel MOS load means and first pre-stage N-channel MO
The S differential amplifying means performs an amplifying operation in which the third complementary signal is input and the second complementary signal is output, and when the second preceding stage control signal is selected, the P channel MOS load means and the The second-stage N-channel MOS differential amplifying means of 2 performs an amplifying operation in which the fourth complementary signal is input and the second complementary signal is output, and when the latter-stage control signal is selected, the P-channel MOS load means is provided. And the latter-stage N-channel MOS differential amplifying means performs an amplifying operation in which the second complementary signal is input and the fifth complementary signal is output.

According to another aspect of the semiconductor memory device of the present invention, each gate and each drain are cross-coupled, each source is connected to a power supply line, and each drain is coupled to a first complementary signal. P-channel MOS load means having a P-channel MOS transistor, first and second N-channel MOS transistors having respective gates coupled to a second complementary signal and respective drains coupled to a first complementary signal, and respective drains Connected to respective sources of the first and second N-channel MOS transistors, and third and fourth N-channel MOS transistors in which respective gates are coupled to the second pre-stage control signal.
A transistor and a fifth N-channel MOS transistor whose drain is connected to each source of the third and fourth N-channel MOS transistors, whose gate is coupled to the first pre-stage control signal, and whose source is connected to the ground line. The preceding stage N-channel MOS differential amplifying means having the same and each gate and each drain are cross-coupled, and each drain is a first
6th and 7th N-channel MO coupled to complementary signals of
S-transistor and drain for sixth N-channel MOS
The eighth N-channel MOS transistor, which is connected to the source of the transistor, whose gate is coupled to the latter-stage control signal, whose source is connected to the ground line, and whose drain is connected to the source of the seventh N-channel MOS transistor, and whose gate is the latter stage. N stage N-channel MOS transistor coupled to control signal and having source connected to ground line
Channel MOS differential amplification means, and when the first and second front stage control signals are selected, the P channel MOS load means and the front stage N channel MOS differential amplification means are the second When the amplification operation is performed with the complementary signal as an input and the first complementary signal as an output, and the latter-stage control signal is selected, the P-channel MOS load means and the latter-stage N-channel M are provided.
The OS differential amplification means is configured to perform an amplification operation using the first complementary signal as an input / output.

According to another aspect of the semiconductor memory device of the present invention, each gate and each drain are cross-coupled, each source is connected to a power supply line, and each drain is coupled to a first complementary signal. P-channel MOS load means having a P-channel MOS transistor, first and second N-channel MOS transistors having respective gates coupled to a second complementary signal and drains coupled to a first complementary signal, and respective gates To a first pre-stage control signal and each drain is connected to each source of the first and second N-channel MOS transistors.
A transistor and a fifth N-channel MOS transistor whose drain is connected to each source of the third and fourth N-channel MOS transistors, whose gate is connected to the third pre-stage control signal, and whose source is connected to the ground line. A first pre-stage N-channel MOS differential amplifying means, a sixth and seventh N-channel MOS transistor having each gate coupled to a third complementary signal and each drain coupled to a first complementary signal; Eighth and ninth N-channel MOS transistors having their gates coupled to the second pre-stage control signal and having their drains connected to the sources of the sixth and seventh N-channel MOS transistors respectively, and the drains to the eighth and ninth N
Second pre-stage N-channel MOS differential amplification means having a tenth N-channel MOS transistor connected to each source of the channel MOS transistor, having its gate coupled to a third pre-stage control signal and having its source connected to the ground line. When,
Eleventh and first gates in which each gate and each drain are cross-coupled and each drain is coupled to a first complementary signal.
2 N-channel MOS transistors and drain first
Connect to the source of N-channel MOS transistor of 1,
A thirteenth N-channel MOS transistor whose gate is coupled to the latter-stage control signal and whose source is connected to the ground line;
A 14th N-channel MOS transistor having a drain connected to the source of the 12th N-channel MOS transistor, a gate coupled to the latter-stage control signal, and a source connected to the ground line; When the first and third front-stage control signals are selected, the P-channel MOS load means and the first front-stage N-channel MOS differential amplification means input the second complementary signal. When the amplifying operation with the first complementary signal as the output is performed and the second and third front stage control signals are selected, the P channel MOS load means and the second front stage N channel MOS differential amplifier means , A third complementary signal is input and a first complementary signal is output, an amplifying operation is performed, and when the second-stage control signal is selected, the P-channel MOS load means and the second-stage N-channel M are connected. And the S differential amplifying means, in which to perform the amplifying operation to output the first complementary signal.

[0010]

According to the structure of claim 1, when the pre-stage control signal is selected, the P-channel MOS load means and the pre-stage N are connected.
When the channel MOS differential amplification means constitutes the preceding stage sense amplifier and the latter stage control signal is selected, P
The channel MOS load means and the latter N-channel MOS differential amplifying means constitute the latter sense amplifier.
That is, since one P-channel MOS load means is shared by a plurality of N-channel MOS differential amplification means connected in series, the area occupied by the P-channel MOS load means is greatly reduced as compared with the conventional independent sense amplifier. be able to. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

According to the structure of claim 2, when the first pre-stage control signal is selected, the P-channel MOS load means and the first pre-stage N-channel MOS differential amplifying means constitute a pre-stage sense amplifier. In addition, when the second preceding control signal is selected, the P-channel MOS load means and the second
When the preceding stage N channel MOS differential amplifying means of the above constitutes a preceding stage sense amplifier and further selects the following stage control signal, the P channel MOS load means and the following stage N channel MO
The S differential amplification means constitutes a sense amplifier in the subsequent stage. That is, since one P-channel MOS load means is shared by a plurality of N-channel MOS differential amplification means connected in series, the area occupied by the P-channel MOS load means is greatly reduced as compared with the conventional independent sense amplifier. be able to. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

According to the third aspect of the invention, when the first and second front stage control signals are selected, the P channel M
The OS load means and the preceding N channel MOS differential amplifying means constitute a preceding sense amplifier, and when the following control signal is selected, the P channel MOS loading means and the following N channel MOS differential amplifying means The latter stage sense amplifier will be configured. That is, a plurality of N channel MOSs in which one P channel MOS load means is connected in series
Since it is shared by the differential amplifying means, the area occupied by the P-channel MOS load means can be greatly reduced as compared with the conventional independent sense amplifier. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

According to the structure of the fourth aspect, when the first and third front stage control signals are selected, the P channel M
When the OS load means and the first front-stage N-channel MOS differential amplification means constitute the front-stage sense amplifier, and when the second and third front-stage control signals are selected, the P-channel MO
When the S load means and the second front N-channel MOS differential amplification means constitute a front-stage sense amplifier and a rear-stage control signal is selected, the P-channel MOS load means and the rear-stage N-channel MOS differential amplification means are connected. Will constitute the sense amplifier in the subsequent stage. That is, a plurality of N channel MOSs in which one P channel MOS load means is connected in series
Since it is shared by the differential amplifying means, the area occupied by the P-channel MOS load means can be greatly reduced as compared with the conventional independent sense amplifier. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First to fourth embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the configuration of a semiconductor memory device according to a first embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device of the first embodiment has a P-channel MOS load means 1 and a preceding N-channel M.
It has an OS differential amplifying means 2 and a post-stage N-channel MOS differential amplifying means 3.

P-channel MOS load means 1 is coupled to first complementary signals 6A and 7A. Previous N channel MOS
The differential amplifier 2 is coupled to the first complementary signals 6A and 7A, the second complementary signals 6B and 7B, the third complementary signals 4 and 5, and the preceding stage control signal 12. Then, the latter N channel MO
The S differential amplification means 3 includes the first complementary signals 6A and 7A and the second complementary signals 6A and 7A.
Are coupled to the complementary signals 6B and 7B, the fourth complementary signals 10 and 11 and the latter-stage control signal 13 to form a two-stage serially coupled sense amplifier.

The amplifying operation of the semiconductor memory device of the first embodiment having the above configuration will be described. First, as an initial state, the third complementary signals 4 and 5 and the second complementary signal 6B,
7B is equalized (equal potential), and both the pre-stage control signal 12 and the post-stage control signal 13 are disabled (non-selected).

In such a state, it is assumed that a minute potential difference from a memory cell (not shown) or the like is applied to the third complementary signals 4 and 5 as an input. After that, the previous stage control signal 1
When 2 is enabled (selected), the P-channel MOS load means 1 and the preceding N-channel MOS differential amplification means 2 cause the third complementary signal 4 and the third complementary signal 4 via the first complementary signals 6A and 7A.
Thus, a pre-stage sense amplifier having 5 as an input and the second complementary signals 6B and 7B as an output is configured. This causes amplification.

Next, when the post-stage control signal 13 is enabled, the P-channel MOS load means 1 and the post-stage N-channel M are provided.
The OS differential amplifier means 3 and the second complementary signal 6 which is the output of the preceding stage sense amplifier via the first complementary signals 6A and 7A.
A second-stage sense amplifier that receives B and 7B as inputs and outputs the fourth complementary signals 10 and 11 is configured. Thereby, amplification is performed.

As described above, in the semiconductor memory device of the first embodiment, one P-channel MOS load means 1 is used as a front-stage sense amplifier including the P-channel MOS load means 1 and the front-stage N-channel MOS differential amplification means 2. , P channel M
Since it is shared by the OS load means 1 and the sense amplifier in the subsequent stage including the N-channel MOS differential amplification means 3 in the subsequent stage, P
The area occupied by the channel MOS load means 1 is small. On the other hand, the amplification degree can be maintained at the same level as in the case of independent sense amplifiers for both the front stage sense amplifier and the rear stage sense amplifier. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

In the first embodiment, the sense amplifiers are connected in series in two stages, but a multi-stage configuration in which the post-stage N-channel MOS differential amplifying means 3 is further added may be adopted.
Further, in the first embodiment, the first complementary signals 6A and 7A, the second complementary signals 6B and 7B and the fourth complementary signals 10 and 11 are treated as separate signals, but they are common. But good.

Next, FIG. 2 is a block diagram showing a structure of a semiconductor memory device according to a second embodiment of the present invention. As shown in FIG. 2, the semiconductor memory device of the second embodiment includes a P-channel MOS load means 1, a first pre-stage N-channel MOS differential amplifying means 2A, and a second pre-stage N-channel MOS differential amplifying means. It has a means 2B and a latter-stage N-channel MOS differential amplifier means 3.

P-channel MOS load means 1 is coupled to the first complementary signals 6A and 7A. In addition, the first front stage N-channel MOS differential amplifying means 2A has the first complementary signal 6
A, 7A and the second complementary signals 6B, 7B, the third complementary signals 4A, 5A and the first front stage control signal 12A. The second front stage N-channel MOS differential amplification means 2B is
First complementary signals 6A, 7A and second complementary signals 6B, 7B
And the fourth complementary signals 4B and 5B and the second front stage control signal 12
Is connected to B. The latter-stage N-channel MOS differential amplifying means 3 is coupled to the first complementary signals 6A and 7A, the second complementary signals 6B and 7B, the fifth complementary signals 10a and 11a, and the latter-stage control signal 13. , As a whole, a two-stage series connected sense amplifier is configured.

The amplifying operation of the semiconductor memory device of the second embodiment having the above configuration will be described. First, as an initial state, the third complementary signals 4A and 5A and the fourth complementary signal 4 are
B and 5B and the second complementary signals 6B and 7B are equalized, respectively, and the first pre-stage control signal 12A, the second pre-stage control signal 12B and the post-stage control signal 13 are both disabled. To do.

In such a state, the minute potential difference from the memory cell or the like is used as an input for the third complementary signals 4A and 5A.
Given to. Then, the first pre-stage control signal 12
When A is enabled, P-channel MOS load means 1
And the first front stage N-channel MOS differential amplification means 2A,
The third complementary signal 4 is transmitted via the first complementary signals 6A and 7A.
A pre-stage sense amplifier having A and 5A as inputs and second complementary signals 6B and 7B as outputs is configured. This causes amplification.

Similarly, when the minute potential difference input is applied to the fourth complementary signals 4B and 5B, when the second front stage control signal 12B is enabled, the P-channel MOS load means 1 and the second complementary control signal 12B are activated. Pre-stage N channel MOS differential amplification means 2
B constitutes a pre-stage sense amplifier which receives the fourth complementary signals 4B and 5B via the first complementary signals 6A and 7A and outputs the second complementary signals 6B and 7B. This causes amplification.

Next, when the post-stage control signal 13 is enabled, the P-channel MOS load means 1 and the post-stage N-channel M are provided.
The OS differential amplifier means 3 and the second complementary signal 6 which is the output of the preceding stage sense amplifier via the first complementary signals 6A and 7A.
B and 7B are input, and the fifth complementary signals 10a and 11a are output to form a post-stage sense amplifier. This causes amplification.

As described above, in the semiconductor memory device of the second embodiment, since one P-channel MOS load means 1 is shared by the preceding sense amplifier and the latter sense amplifier, P
The area occupied by the channel MOS load means 1 is small. On the other hand, the amplification degree can be maintained at the same level as in the case of independent sense amplifiers for both the front stage sense amplifier and the rear stage sense amplifier. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

In the second embodiment, two column control signals are used as selection signals for two input signals, and the column selector of the memory and the sense amplifier are connected. Therefore, it can be applied to higher-performance circuits.
In the second embodiment, the sense amplifiers are connected in series in two stages, but a multi-stage configuration in which the post-stage N-channel MOS differential amplifying means 3 is further added may be adopted. In addition, although the number of signals that can be input is two in the second embodiment, the number of signals that can be input may be increased by increasing the number of preceding N-channel MOS differential amplifying means. Furthermore, in the second embodiment, the first complementary signals 6A, 7A, the second complementary signals 6B, 7B and the fifth complementary signals 10a, 11a are treated as separate signals, but they are made common. It may be configured.

Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIGS. Figure 3
Is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of the semiconductor memory device. As shown in FIG. 3, the semiconductor memory device of the third embodiment has P-channel MOS load means 1, pre-stage N-channel MOS differential amplification means 2, and post-stage N-channel MOS differential amplification means 3. ing.

The P-channel MOS load means 1 has P-channel MOS transistors P1 and P2.
Each of the P-channel MOS transistors P1 and P2 has a structure in which each gate and each drain are cross-coupled, each source is connected to a power supply line, and each drain is coupled to the first complementary signals 6 and 7.

The preceding stage N-channel MOS differential amplifying means 2 includes N-channel MOS transistors N1, N2 and N.
3, N4 and N5. These N-channel MOS transistors N1 and N2 have their drains
Of the complementary signals 6 and 7, and each gate is coupled to the second complementary signals 4C and 5C.

N-channel MOS transistors N3 and N4
Is a circuit in which each gate is coupled to the second pre-stage control signal 12B and each drain is connected to each source of the N-channel MOS transistors N1 and N2. The N-channel MOS transistor N5 has a gate connected to the first front stage control signal 12A and a drain connected to the N-channel MOS transistor N5.
3 and N4, and the sources are connected to the ground line.

Further, the latter-stage N-channel MOS differential amplifying means 3 includes N-channel MOS transistors N6, N7 and N8.
And N9. This N channel MOS
Transistors N6 and N7 are such that each gate and each drain are cross-coupled and further coupled to the first complementary signals 6 and 7. N-channel MOS transistor N
Reference numeral 8 denotes a drain connected to the source of the N-channel MOS transistor N6, a source connected to the ground line, and a gate coupled to the post-stage control signal 13. Similarly,
The N-channel MOS transistor N9 has a drain connected to the source of the N-channel MOS transistor N7, a source connected to the ground line, and a gate connected to the latter-stage control signal 13.
Combined with.

The amplifying operation of the semiconductor memory device of the third embodiment having the above structure will be described. First, as an initial state, the second complementary signals 4C and 5C and the first complementary signals 6 and 7 are equalized, and the first front stage control signal 12A and the second stage control signal 13 are both disabled. It is assumed that the preceding stage control signal 12B of No. 2 is enabled (at the time point indicated by symbol a in FIG. 4).

It is assumed that a minute potential difference from the memory cell or the like is applied as an input to the second complementary signals 4C and 5C (at the time point of the reference numeral B in FIG. 4). After that, when the first front-stage control signal 12A is enabled (at the time point C in FIG. 4), the P-channel MOS load means 1 and the front-stage N-channel M are connected.
The OS differential amplifying means 2 constitutes a pre-stage sense amplifier which receives the second complementary signals 4C and 5C via the first complementary signals 6 and 7 and outputs the first complementary signals 6 and 7. As a result, the amplification operation is performed.

Next, when the latter-stage control signal 13 is enabled and at the same time the second former-stage control signal 12B is disabled (at the point of the reference numeral D in FIG. 4), the P-channel MO
The S load means 1 and the post-stage N-channel MOS differential amplification means 3 constitute a post-stage sense amplifier whose input and output are the first complementary signals 6 and 7, and perform an amplification operation (see the symbol e in FIG. 4). Time point).

As described above, in the semiconductor memory device of the third embodiment, one P-channel MOS load means 1 is shared by the sense amplifier in the preceding stage and the sense amplifier in the succeeding stage.
The area occupied by the P-channel MOS load means 1 is small. On the other hand, the degree of amplification can be maintained at the same level as in the case of independent sense amplifiers for both the front sense amplifier and the rear sense amplifier. Therefore, a high degree of integration can be achieved without impairing the degree of amplification. Further, since the latter stage sense amplifier forms a latch type sense amplifier, a full swing of the output voltage is possible.

In the third embodiment, the sense amplifiers are connected in two stages in series, but a multi-stage configuration in which a post-stage N-channel MOS differential amplifying means is further added may be used. Next, a semiconductor memory device of the fourth embodiment will be described with reference to FIGS. FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention, and FIG. 6 is a waveform diagram for explaining the operation of the semiconductor memory device.

The semiconductor memory device of the fourth embodiment comprises a P-channel MOS load means 1 and a first pre-stage N-channel MOS.
Differential amplification means 2A, second front stage N-channel MOS differential amplification means 2B, and rear stage N-channel MOS differential amplification means 3
And have. The P channel MOS load means 1 has P channel MOS transistors P1 and P2.

This P channel MOS transistor P1,
In P2, each gate and each drain are cross-coupled, each source is connected to the power supply line, and each drain is coupled to the first complementary signals 6 and 7. Also, the first
The preceding stage N-channel MOS differential amplifying means 2A includes N-channel MOS transistors N1, N2, N3, N4 and N.
Have 5.

This N-channel MOS transistor N1,
N2 has each gate coupled to the second complementary signals 4C and 5C and each drain coupled to the first complementary signals 6 and 7. The N-channel MOS transistors N3 and N4 are
Each gate is coupled to the first pre-stage control signal 12A, and each drain is connected to each source of the N-channel MOS transistors N1 and N2.

The N-channel MOS transistor N5 has a drain connected to the sources of the N-channel MOS transistors N3 and N4, a source connected to the ground line, and a gate coupled to the third pre-stage control signal 12C.
In addition, the second front stage N-channel MOS differential amplification means 2B
Are N-channel MOS transistors N6, N7, N8,
N9 and N10.

This N-channel MOS transistor N6
N7 has each gate coupled to the third complementary signals 4A and 5A and each drain coupled to the first complementary signals 6 and 7. The N-channel MOS transistors N8 and N9 are
Each gate is coupled to the second pre-stage control signal 12B, and each drain is connected to each source of the N-channel MOS transistors N6 and N7.

The N-channel MOS transistor N10 is
The drain is connected to the sources of the N-channel MOS transistors N8 and N9, and the gate is the third pre-stage control signal 12C.
The source is connected to the ground line. Further, the latter-stage N-channel MOS differential amplifying means 3 is
It has channel MOS transistors N11, N12, N13 and N14.

This N-channel MOS transistor N1
Reference numerals 1 and N12 are obtained by cross-coupling the respective gates and the respective drains and further coupling them to the first complementary signals 6 and 7. The N-channel MOS transistor N13 has a drain connected to the source of the N-channel MOS transistor N11, a source connected to the ground line, and a gate coupled to the latter-stage control signal 13.

The N-channel MOS transistor N14 is
The drain is connected to the source of the N-channel MOS transistor N12, the source is connected to the ground line, and the gate is coupled to the post-stage control signal 13. The amplifying operation of the semiconductor memory device of the fourth embodiment having the above configuration will be described.

First, as the initial state, the second complementary signal 4
C, 5C, the third complementary signals 4A, 5A and the first complementary signals 6, 7 are equalized, and the second front stage control signal 12B, the third front stage control signal 12C and the rear stage control signal 13 are all It is assumed that the signal is disabled and the first front-stage control signal 12A is enabled (at the time point indicated by symbol a in FIG. 6).

It is assumed that a minute potential difference from a memory cell or the like is applied to the second complementary signals 4C and 5C as an input (at the time point of the reference numeral B in FIG. 6). After that, when the third pre-stage control signal 12C is enabled (at the time of the symbol C in FIG. 6), the P-channel MOS load means 1 and the first pre-stage N-channel MOS differential amplifying means 2A become the first complementary. Signal 6,
The second complementary signals 4C and 5C are input via
A pre-stage sense amplifier that outputs the complementary signals 6 and 7 is constructed, and amplification is performed by this.

Next, when the latter-stage control signal 13 is enabled and at the same time the first former-stage control signal 12A is disabled (at the point of the reference numeral D in FIG. 6), the P-channel MO
The S load means 1 and the post-stage N-channel MOS differential amplifying means 3 constitute a post-stage sense amplifier that inputs and outputs the first complementary signals 6 and 7, and performs amplification (at the time indicated by the symbol E in FIG. 6). ).

Similarly, the case where a minute potential difference is applied as an input to the third complementary signals 4A and 5A will be described. In this case, as the initial state, the second complementary signals 4C and 5C and the third complementary signal 4C
Complementary signals 4A, 5A and the first complementary signals 6, 7 are equalized, and the first pre-stage control signal 12A, the third pre-stage control signal 12C, and the post-stage control signal 13 are both disabled. It is assumed that the second front stage control signal 12B is enabled.

When a minute potential difference is applied as an input to the third complementary signals 4A and 5A and then the third front stage control signal 12C is enabled, the P channel MOS load means 1 and the second front stage N channel MOS are provided. The differential amplifying means 2B and the third complementary signal 4A, via the first complementary signal 6 and 7,
A pre-stage sense amplifier having 5A as an input and the first complementary signals 6 and 7 as an output is configured to perform amplification.

Next, when the latter-stage control signal 13 is enabled and at the same time the second former-stage control signal 12B is disabled, the P-channel MOS load means 1 and the latter-stage N-channel MOS differential amplifying means 3 become the first. Complementary signals 6, 7
A post-stage sense amplifier having the input and output as the input and output is configured to perform amplification. As described above, in the semiconductor memory device of the fourth embodiment, one P-channel MOS load means 1 is shared by the preceding sense amplifier and the subsequent sense amplifier, so that the P-channel MOS load means 1 is occupied as compared with the conventional one. The area will be small. On the other hand, the amplification degree can be maintained at the same level as in the case of independent sense amplifiers for both the front stage sense amplifier and the rear stage sense amplifier. Therefore, a high degree of integration can be achieved without impairing the degree of amplification.

In the fourth embodiment, the two column control signals 12A and 12B are used as selection signals for the two input signals, and the column selector of the memory and the sense amplifier are connected. Therefore, it can be applied to higher-performance circuits. Further, since the latter-stage sense amplifier forms a latch-type sense amplifier, a full swing of the output voltage is possible.

In the fourth embodiment, the number of complementary signals that can be input is two.
The number of S differential amplification means may be increased to increase the number of complementary signals that can be input. In the fourth embodiment, two stages of sense amplifiers are connected in series, but a multi-stage configuration in which a post-stage N-channel MOS differential amplifying means is further added may be used. Further, in the fourth embodiment, both the N-channel MOS transistors N5 and N10 are controlled by the third front stage control signal 12C, but the signals may be controlled separately.

[0055]

According to the semiconductor memory device of the first aspect, one P-channel MOS load means is shared by a plurality of N-channel MOS differential amplifier means connected in series.
The area occupied by the P-channel MOS load means can be significantly reduced as compared with the conventional case. Further, the amplification degree can be maintained at the same level as that of the independent sense amplifier. Therefore, high integration can be achieved without impairing the amplification degree.

According to the semiconductor memory device of the second aspect,
Since one P-channel MOS load means is shared by a plurality of N-channel MOS differential amplifier means connected in series, the area occupied by the P-channel MOS load means can be significantly reduced as compared with the conventional case. Further, the amplification degree can be maintained at the same level as that of the independent sense amplifier. Therefore, high integration can be achieved without impairing the amplification degree. Further, by having a plurality of preceding N-channel MOS differential amplifying means, a plurality of input signals can be selected, and a high-level application in the form of coupling the column selector and the sense amplifier is possible.

According to the semiconductor memory device of the third aspect,
Since one P-channel MOS load means is shared by a plurality of N-channel MOS differential amplifier means connected in series, the area occupied by the P-channel MOS load means can be significantly reduced as compared with the conventional case. Further, the amplification degree can be maintained at the same level as that of the independent sense amplifier. Therefore, high integration can be achieved without impairing the amplification degree. In addition, P-channel MOS
Since the latter-stage sense amplifier formed by the load means and the latter-stage N-channel MOS differential amplifier means forms a latch type sense amplifier, the output voltage can be fully swung. According to the semiconductor memory device of claim 4, a plurality of N-channel MOSs in which one P-channel MOS load means is connected in series.
Since it is shared between the differential amplifying means, the area occupied by the P-channel MOS load means can be greatly reduced as compared with the conventional case. Further, the amplification degree can be maintained at the same level as that of the independent sense amplifier. Therefore, high integration can be achieved without impairing the amplification degree. Further, by having a plurality of preceding N-channel MOS differential amplifying means, a plurality of input signals can be selected, and a high-level application in the form of coupling the column selector and the sense amplifier is possible. Further, since the latter-stage sense amplifier composed of the P-channel MOS load means and the latter-stage N-channel MOS differential amplifying means forms a latch type sense amplifier, a full swing of the output voltage is possible.

[Brief description of drawings]

FIG. 1 is a block diagram (corresponding to claim 1) showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a block diagram (corresponding to claim 2) showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram (corresponding to claim 3) showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a waveform diagram for explaining the operation of the same semiconductor memory device.

FIG. 5 is a circuit diagram (corresponding to claim 4) showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the same semiconductor memory device.

[Explanation of symbols]

 1 P-channel MOS load means 2 Pre-stage N-channel MOS differential amplification means 3 Rear-stage N-channel MOS differential amplification means 6, 7, 6A, 7A First complementary signal 6B, 7B, 4C, 5C Second complementary signal 4, 5,4A, 5A Third complementary signal 10,11,4B, 5B Fourth complementary signal 10a, 11a Fifth complementary signal 12 Pre-stage control signal 13 Post-stage control signal 2A First pre-stage N-channel MOS differential amplifying means 2B Second pre-stage N-channel MOS differential amplifying means P1 First P-channel MOS transistor P2 Second P-channel MOS transistor N1 First N-channel MOS transistor N2 Second N-channel MOS transistor N3 Third N-channel MOS transistor N4 Fourth N-channel MOS transistor N5 Fifth N-channel MOS transistor N6 Sixth N-channel MOS transistor N7 Seventh N-channel MOS transistor Star N8 Eighth N-channel MOS transistor N9 Ninth N-channel MOS transistor N10 Tenth N-channel MOS transistor N11 Eleventh N-channel MOS transistor N12 Twelfth N-channel MOS transistor N13 Thirteenth N-channel MOS transistor N14 Fourteenth N-channel MOS transistor 12A First pre-stage control signal 12B Second pre-stage control signal 12C Third pre-stage control signal

Claims (4)

[Claims] 1. A P-channel M coupled to a first complementary signal.
OS load means, pre-stage N-channel MOS differential amplification means coupled to the first complementary signal, the second complementary signal, the third complementary signal, and the pre-stage control signal, the first complementary signal and the first complementary signal. A second-stage N-channel MOS differential amplifying means coupled to the second complementary signal, the fourth complementary signal, and the second-stage control signal. When the preceding-stage control signal is selected, the P-channel MOS load means and the preceding stage are provided. The N-channel MOS differential amplifying means performs an amplifying operation in which the third complementary signal is input and the second complementary signal is output, and when the latter-stage control signal is selected, the P-channel MOS load is A semiconductor memory device in which the means and the latter-stage N-channel MOS differential amplifier means perform an amplifying operation in which the second complementary signal is input and the fourth complementary signal is output. 2. A P-channel M coupled to the first complementary signal.
OS load means, first pre-stage N-channel MOS differential amplifying means coupled to the first complementary signal, the second complementary signal, the third complementary signal and the first pre-stage control signal, and the first Complementary signal, the second complementary signal, the fourth complementary signal, and the second complementary signal
Second pre-stage N-channel MO coupled to the pre-stage control signal of
S differential amplification means, and second-stage N-channel MOS differential amplification means coupled to the first complementary signal, the second complementary signal, the fifth complementary signal, and the latter-stage control signal, the first differential signal, When the pre-stage control signal is selected, the P-channel MOS load means and the first pre-stage N-channel MO are provided.
The S differential amplifying means performs an amplifying operation in which the third complementary signal is input and the second complementary signal is output, and when the second pre-stage control signal is selected, the P channel MOS Load means and the second front N channel MO
S differential amplifying means performs an amplifying operation in which the fourth complementary signal is input and the second complementary signal is output, and when the latter-stage control signal is selected, the P-channel MOS load means and A semiconductor memory device in which the latter-stage N-channel MOS differential amplifying means performs an amplifying operation in which the second complementary signal is input and the fifth complementary signal is output. 3. A P-channel having first and second P-channel MOS transistors in which each gate and each drain are cross-coupled, each source is connected to a power supply line, and each drain is coupled to a first complementary signal. MOS load means, first and second N-channel MOS transistors each having its gate coupled to a second complementary signal and each drain coupled to said first complementary signal, and each drain having said first and second drains coupled to each other. Of the third and fourth N-channel MOS transistors connected to the respective sources of the N-channel MOS transistors of which respective gates are coupled to the second pre-stage control signal, and the drains of the third and fourth N-channel MOS transistors. A fifth N-channel MOS transistor connected to each source, having its gate coupled to the first pre-control signal and its source connected to the ground line. And a sixth and seventh N-channel MOS transistor in which each gate and each drain are cross-coupled and each drain is coupled to the first complementary signal, and a drain. Is connected to the source of the sixth N-channel MOS transistor, the gate is coupled to the latter-stage control signal, and the source is connected to the ground line, and the drain is the seventh N-channel MOS transistor. A rear N-channel M having a ninth N-channel MOS transistor connected to the source of the transistor, the gate coupled to the rear control signal, and the source connected to the ground line.
OS differential amplifying means, and when the first and second pre-stage control signals are selected, the P-channel MOS load means and the pre-stage N-channel MOS differential amplifying means are the second complementary circuits. When an amplification operation is performed with a signal as an input and the first complementary signal as an output, and the latter-stage control signal is selected, the P-channel MOS load means and the latter-stage N-channel MOS differential amplifier means are A semiconductor memory device configured to perform an amplifying operation using a first complementary signal as an input / output. 4. A P-channel having first and second P-channel MOS transistors in which each gate and each drain are cross-coupled, each source is connected to a power supply line, and each drain is coupled to a first complementary signal. MOS load means, first and second N-channel MOS transistors each having its gate coupled to a second complementary signal and each drain coupled to said first complementary signal, and each gate having a first pre-stage control signal Of the third and fourth N-channel MOS transistors having drains connected to respective sources of the first and second N-channel MOS transistors, and drains of the third and fourth N-channel MOS transistors. Fifth N-channel MOS transistor connected to each source, gate connected to third pre-control signal, source connected to ground line The first front stage N-channel M and a motor
OS differential amplification means, sixth and seventh N-channel MOS transistors having respective gates coupled to a third complementary signal and drains coupled to the first complementary signal, and respective gates to a second front stage. Eighth and ninth N-channel MOS transistors coupled to a control signal and having drains connected to respective sources of the sixth and seventh N-channel MOS transistors, and drains of the eighth and ninth N-channel MOS transistors. A tenth N connected to each source of the transistor, having a gate coupled to the third pre-control signal and a source connected to the ground line.
Second pre-stage N-channel MOS differential amplification means having a channel MOS transistor, and eleventh and twelfth N-channels in which each gate and each drain are cross-coupled and each drain is coupled to the first complementary signal. A thirteenth N-channel MOS transistor having a MOS transistor and a drain connected to the source of the eleventh N-channel MOS transistor, a gate coupled to a post-stage control signal, and a source connected to the ground line, and a drain to the thirteenth N-channel MOS transistor. 12 N-channel MOS
A second stage N-channel MOS differential amplifying means having a fourteenth N-channel MOS transistor connected to a source of the transistor, a gate coupled to the second-stage control signal, and a source connected to the ground line. When the first and third pre-stage control signals are selected, the P channel MOS load means and the first pre-stage N are selected.
When the channel MOS differential amplifying means performs an amplifying operation in which the second complementary signal is input and the first complementary signal is output, and the second and third pre-stage control signals are selected, The P channel MOS load means and the second front stage N
The channel MOS differential amplifying means performs an amplifying operation in which the third complementary signal is input and the first complementary signal is output, and when the latter-stage control signal is selected, the P-channel MOS load means And a semiconductor memory device in which the latter-stage N-channel MOS differential amplifying means performs an amplifying operation using the first complementary signal as an input / output.