JPH05241866A - Firmware device - Google Patents

Abstract

PURPOSE:To obtain a firmware device capable of operating the device by holding the memory data at the time of a fault as it is when the device fault occurs and easily collecting the memory data at the time of fault. CONSTITUTION:The firmware device is composed of a CPU circuit 1 performing the control of a system, a first system memory 3 and a second system memory 4 performing the input/output of data with the CPU circuit 1 and a memory selection circuit 2 alternately outputting the memory selection signal from the CPU circuit 1 every time a system reset signal is inputted to either one of the first system memory 3 and the second system memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a firmware device and, more particularly, to a firmware device provided with measures against a failure.

[0002]

2. Description of the Related Art In a conventional firmware device,
The system reset signal is configured to initialize the system memory, and when trying to collect memory data to maintain the state at the time of failure, perform processing until the maintenance personnel collect the data. A switch that can switch the initialization mode is provided in case the system is stalled due to a failure and data collection becomes impossible as it is, so that the minimum initial Only the conversion process was performed, and the work area of the memory was retained and reset.

[0003]

However, in the above-mentioned conventional example, since the device cannot be used until the maintenance person collects the data, the MTBF (mean failure time) of the system becomes large and the reliability of the system deteriorates. There was an inconvenience to do.

Further, even if the initialization mode is provided, there is a problem that the data content is updated when a new process is performed.

[0005]

SUMMARY OF THE INVENTION The object of the present invention is to improve the inconvenience of the conventional example, and in particular, when a device failure occurs, the apparatus can be operated while retaining the memory data at the time of the failure, and at the time of the failure. It is an object of the present invention to provide a firmware device capable of easily collecting the memory data of the above.

[0006]

Therefore, in the present invention, a CPU circuit for controlling the system, and a first system memory and a second system memory for inputting / outputting data between the CPU circuit and the CPU circuit.
System memory and a memory selection circuit that alternately outputs a memory selection signal from the CPU circuit to either the first system memory or the second system memory each time a system reset signal is input. The composition is adopted. This aims to achieve the above-mentioned object.

[0007]

The CPU circuit sequentially performs the predetermined processing. Since the memory selection circuit is set to send the memory selection signal from the CPU circuit to the first system memory, the CPU circuit stores the processing result in the first system memory and stores the data necessary for the processing. Read from the first system memory. Here, if the CPU circuit cannot continue normal processing due to a device failure or abnormal program stop or abnormal runaway, the operator presses the reset switch. When the system reset signal is output to the memory selection circuit, the memory selection circuit sets the memory selection signal to be sent to the second system memory.

The CPU circuit starts a predetermined process from the beginning by the system reset signal. Then, the CPU circuit stores the processing result in the second system memory and reads the data required for the processing from the second system memory. That is, the data immediately before the operator presses the reset switch is stored in the first system memory as it is. When the data stored in the first system memory is required, when the memory device switching command is sent from the CPU circuit, the system reset signal is output to the memory selection circuit, so that the first system memory is accessible. Become.

[0009]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIG.

The embodiment shown in FIG. 1 is a C for controlling the system.
A first system memory 3 and a second system memory 4 for inputting / outputting data between the PU circuit 1 and the CPU circuit 1, and a CPU each time a system reset signal is input.
The memory selection signal from the circuit 1 is sent to the first system memory 3
And a memory selection circuit 2 for alternately outputting to either one of the second system memory 4 and the second system memory 4.

Here, the CPU circuit 1 includes an address bus 9
It is composed of a CPU 1A that outputs an address signal to and outputs data via the data bus 10, and a program memory 1B that stores the operating procedure of the CPU 1A.

Next, the operation of this embodiment will be described.

.. The CPU 1A sequentially outputs address signals to the program memory 1B via the address bus 9, sequentially inputs the program data stored in the position designated by the address signal via the data bus 10, and uses the program data. The instructed processing is sequentially performed.

.. The memory selection circuit 2 is the CPU 1
Since the memory selection signal 5 from A is set to be sent to the first system memory 3, the CPU 1A designates an address, stores the processing result in the first system memory 3, and stores the data necessary for processing. Is read from a predetermined address position of the first system memory 3.

.. Here, if the CPU 1A cannot continue normal processing due to a device failure or abnormal program stop or abnormal runaway, the operator presses the reset switch.

.. The system reset signal 8 is output to the memory selection circuit 2.

.. Upon receiving the system reset signal 8, the memory selection circuit 2 sets the memory selection signal 5 to be sent to the second system memory 4.

.. CPU1A is system reset signal 8
When the address is received, a new address signal is sequentially output to the program memory 1B from the beginning through the address bus 9, and the program data stored in the position designated by the address signal is sequentially input through the data bus 10. , Starts the processing instructed by the program data.

.. And this time, the memory selection circuit 2 is C
Since the memory selection signal 5 from the PU 1A is set to be sent to the second system memory 4, the CPU 1A specifies the address, stores the processing result in the second system memory 4, and stores the data necessary for the processing. The second system memory 4
Is read from a predetermined address position of. That is, the data immediately before the operator depresses the reset switch is stored in the first system memory 3 as it is.

[0020]. When the data stored in the first system memory 3 is required, when the memory device switching command is sent from the CPU 1A, the system reset signal 8 is output to the memory selection circuit 2. It becomes accessible.

As described above, the memory data at the time of failure is retained even after the system reset, and the device can be operated while retaining the memory data.

[0022]

Since the present invention is constructed and functions as described above, according to this, it is possible to switch the memory to be accessed each time a system reset is performed, which causes a failure when a device failure occurs. It is possible to operate the device while holding the memory data at the time, and not to be able to use the device until the maintenance person collects the failure data. Also, if the device stalls due to the failure, the system can be reset. It is possible to provide an unprecedented excellent firmware device in which the stall condition is resolved and the memory data can be collected thereafter.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1: CPU circuit 1A: CPU 1B: Program memory 2: Memory selection circuit 3: First system memory 4: Second system memory 5: Memory selection signal 6: First system memory selection signal 7: Second system Memory selection signal 8: System reset signal 9: Address bus 10: Data bus

Claims (1)

[Claims] 1. A CPU circuit for controlling the system, and a first system memory and a second system memory for inputting / outputting data to / from the CPU circuit, each time a system reset signal is input. And a memory selection circuit that alternately outputs a memory selection signal from the CPU circuit to one of the first system memory and the second system memory.