JPH05235990A - Cell composing equipment - Google Patents

Abstract

PURPOSE:To provide the cell composition equipment in which a cell processing delay time is shortened with respect to the cell composition equipment composing cells being information transfer blocks in the asynchronous transfer mode that takes priority into account. CONSTITUTION:After an analog transmission signal is divided into plural bands by a band division coding means 31, the signal is coded and a block processing means 32 blocks the coded signal for each bit number being a multiple of N (integer being 2 or over) of a minimum quantization bit number and a cell composition means 33 composes cells for each block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell assembling apparatus for assembling cells which are information transfer blocks in an asynchronous transfer mode in consideration of priority order.

In recent years, in the field of communication, an asynchronous transfer mode (hereinafter referred to as "ATM") has been attracting attention as an information transfer mode in response to a transfer request for an image signal and an audio signal.

In this ATM, information is transferred in fixed length information transfer blocks called cells. Therefore, when transferring image signals and audio signals by ATM,
It is necessary to assemble cells from these signals.

[0004]

2. Description of the Related Art FIG. 13 is a block diagram showing the structure of a cell assembling / disassembling apparatus in a transmitting / receiving apparatus for audio signals such as voice signals.

The device shown in the drawing has left and right two channels Lch and R.
It is composed of a cell assembling / transmitting device 10 for converting ch audio signals into cells and transferring them to an ATM network, and a cell disassembling device 20 for disassembling cells sent from the ATM network and reproducing left and right two-channel Lch and Rch audio signals. To be done.

The cell assembling apparatus 10 encodes an analog audio signal and then converts it into cells.
That is, in this cell assembling apparatus 10, an analog input audio signal is first converted into an analog / digital conversion section (hereinafter referred to as “A / D conversion circuit”) 11L, 1
It is sampled and quantized by 1R and converted into a digital signal.

This digital signal is transmitted to the encoding unit 12L,
It is compressed and encoded by 12R and converted into a pulse code modulation (hereinafter referred to as "PCM") signal. This PCM
The signals are assembled into cells by the cell assembling unit 13 and then sent to the ATM network.

On the other hand, the cell disassembling device 20 is adapted to disassemble the cell received from the ATM network and then decode it to reproduce an analog audio signal. That is, in the cell disassembling device 20, first, a cell destined to the own station is detected from the cells transmitted by the ATM network. This cell is decomposed by the cell decomposition unit 21 into PCM signals of the left and right channels Lch and Rch.

This PCM signal is decoded by the decoding units 22L and 22L.
It is decoded and decompressed by R and converted back into a digital signal.
This digital signal is returned to an analog audio signal by digital / analog converters (hereinafter referred to as “D / A converters”) 23L and 23R.

The above-mentioned various processes are executed on the basis of a cell head signal indicating the cell transmission timing and a data clock defining the timing of various signal processes.

FIG. 14 is a timing chart showing the relationship between the cell head signal, the data clock and the cell.

Here, the cell length is 72 bytes (header 8
Byte, information field 64 bytes), and the cell is assumed to be handled in 8-bit parallel. The frequency of the cell head signal is 270 KHz and the frequency of the data clock is 19.44 MHz.

FIG. 15 shows the above-mentioned coding units 12L and 12L.
It is a block diagram which shows the concrete structure of R. The encoding units 12L and 12R shown in the figure adopt a band division encoding method as an encoding method.

In this case, the input digital signal is
Low range L (0-6KHz), middle low range ML (6-12KH)
z), mid-high range MH (12-18 KHz), high range H (18
.About.24 KHz) and then encoded for each band.

The band division is performed by a quadrature mirror filter (hereinafter referred to as "QMF") 121 capable of canceling the aliasing component.
122 and 123. In addition, this QMF12
1, 122 and 123 have a downsampling function, and are adapted to perform low frequency conversion of an input signal.

The coding is an adaptive difference PCM (hereinafter, referred to as "ADPC" which predicts a current input signal from a past input signal and encodes a difference between the current input signal and the current input signal with a plurality of bits.
M ”) circuits 124L, 124ML, 124MH,
124H.

In this case, the number of quantization bits of each band L, ML, MH, H is set to 8 bits, 4 bits, 2 bits and 2 bits, respectively. This is because by allocating a larger number of quantization bits to a band where energy is concentrated, that is, a band having a high contribution to the coding quality SNR _seg , the total coding quality SNR _{se g}
Is to improve.

An embedded ADPCM is adopted as the ADPCM for the low frequency L and the low and middle frequency band ML. In this case, the core bits are 4 bits and 2 bits, respectively, and the embedded bits are also 4 bits and 2 bits, respectively.

FIG. 16 shows 8-bit low frequency band L and middle low frequency band ML.
The 16 bits of the PCM signal are divided into eight blocks B1 to B8 by dividing each of the four bits from the most significant bit into two bits (minimum quantization bit number).

In this case, the blocks B1 and B2 of the low frequency band L and the block B5 of the middle low frequency band ML correspond to core bits, and the blocks B3 and B4 of the low frequency band L and the block B6 of the middle low frequency band ML.
Corresponds to the embedded bit.

When assembling a cell from such a PCM signal, a constant delay time (hereinafter referred to as "cellization delay time") occurs due to the need to store samples for one cell. This cellization delay time differs depending on whether the cell priority order is considered or not.

The cellization delay time when the priority order is not considered is as follows. First, the number of samples required to assemble one cell is 64 for 1 cell and 4 for 1 sample (Lch: 2 bytes, Rch: 2
Since it is a byte, it becomes 16 as shown in the following expression (1).

64/4 = 16 (1)

On the other hand, the sampling frequency after downsampling is 12 KHz if the sampling frequency before downsampling is 48 KHz and the downsampling rate is 1/4.

As a result, the cellization delay time in this case becomes 1.3 msec as shown in the following equation (2).

{1 / (12 × 10 ⁻³ )} × 16 = 1.3 (2)

The frequency of the cell head signal is 270 KH.
Since it is z, the number of cells transmitted per sampling period is 22.5 as shown in the following equation (3). This state is shown in FIG.

1 / (12 × 10 ³ ) ÷ 1 / (270 × 10 ³ ) = 22.5 (3)

As a result, the number of cells transmitted per 1.3 msec becomes 360 as shown in the following equation (4).

22.5 × 16 = 360 (4)

FIG. 18 is a diagram showing the structure of the information field of a cell when the priority order of cells is not considered. As shown in the figure, in this case, the cells are the channels Lch and Rc.
It is assembled so that the PCM signal of h is alternately multiplexed for each sample.

FIG. 19 is a diagram showing cell transmission timing in this case. As shown in the figure, in this case, since the cellization delay time is 1.3 msec (360 cells), each cell is sequentially output at a cycle of 1.3 msec (360 cells).

Next, the cell formation delay time in the case of considering the priority order of cells will be described. In this case, conventionally, for each block Bm (m = 1, 2, ..., 8) described above,
It was supposed to assemble cells. That is, cells have been assembled for each minimum number of quantized bits in the band division coding method.

In the case of such an assembling method, 128 samples of PCM signals are required to assemble one cell. As a result, the cellization delay time becomes 10.4 msec, which is eight times that when the cell priority order is not considered.

FIG. 20 shows the structure of the information field of the cell in this case. Here, ~ indicates the priority order of the cells, corresponds to the highest priority order, and corresponds to the lowest priority order. As shown in the figure, each cell is constructed by blocks that have a higher degree of contribution to the coding quality SNR _seg for cells having a higher priority.

FIG. 21 shows the cell transmission timing in this case. As shown, the cells of each block Bm are 1.
All blocks B1 to B8 are sent every 3 msec.
It takes 10.4 msec to send the cell.

As described above, the cellization delay time when the priority order of cells is not taken into consideration is as small as 1.3 msec, but it is 10.4 msec when it is taken into consideration.
It will be a big thing. Therefore, for real-time transfer of audio signals, it is preferable to assemble cells without considering the priority order.

However, if the priority order of cells is not considered,
When some cells are discarded due to cell discard, a part of the audio signal is discarded over the entire band, resulting in loss of reproduced sound. Therefore, in order to prevent loss of reproduced sound, it is necessary to assemble cells in consideration of the priority order.

However, in consideration of the priority order of cells, the realization of real-time transfer becomes difficult because the cell formation delay time becomes long as described above. Therefore, when the audio signal is converted into cells and transferred, a device capable of assembling the cells in a short time is required even in consideration of the priority order.

[0040]

As described above, in the case of assembling cells in consideration of the priority order, conventionally, there has been a problem that realization of real-time transfer is difficult due to a long celling delay time.

Therefore, an object of the present invention is to provide a cell assembling apparatus capable of shortening the cell assembly delay time when the priority order is taken into consideration.

[0042]

FIG. 1 is a block diagram showing the configuration of the invention according to claim 4. As shown in FIG. Cell assembly shown
The disassembly device includes a cell assembly device 30 and a cell disassembly device 40.

In the cell assembling apparatus 30, the analog transmission signal is divided into a plurality of bands by the band division encoding means 31 and then encoded. This encoded signal is
The blocking unit 32 sets the minimum quantization bit number N (2
After being divided into a plurality of blocks for each number of bits that is (the above integer) times, the cell assembling means 33 assembles each block into cells.

In the cell disassembly device 40, the received cells are disassembled for each book by the cell disassembly means 41. This block is combined by the encoded signal reproducing means 42 for one sample. The coded signal for one sample thus obtained is decoded by the decoding means 43.

[0045]

According to the above construction, the cells are assembled for each block divided by the number of bits N times the minimum quantization bit number.
It is sufficient if there are N samples. As a result, the cellization delay time can be shortened to 1 / N of the conventional one.

[0046]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the main part of the first embodiment of the present invention.

Before describing the configuration and operation of FIG. 2, an outline of this embodiment will be described with reference to FIGS. 7 to 9. In the following description, a case of assembling cells from band-coded audio signals as shown in FIG. 15 will be described as a representative example.

Conventionally, the left and right 16-bit PCM signals obtained at each sampling timing are divided into eight blocks B1 for each minimum quantization bit number (2 bits).
The case has been described in which the cells are divided into B8 to B8 and cells are assembled for each block Bm.

On the other hand, in this embodiment, the 16-bit PCM signal is divided into four blocks every 4 bits which is twice the minimum quantization bit number, and a cell is divided for each block. It was designed to be assembled.

FIG. 7 shows four blocks of this embodiment and eight conventional blocks B1 to B8 in one channel.
It is a figure which shows the relationship with. In the figure, b1 to b4 are blocks of this embodiment.

As shown in the figure, in this embodiment, the conventional blocks B1 to B8 are grouped in groups of two in descending order of contribution to the coding quality SNR _seg to set four blocks b1 to b4. Is becoming

FIG. 8 shows each block bn (n = 1, 2,
FIG. 3 is a diagram showing the structure of the information field of the cells of this embodiment, which are assembled for each 3 and 4).

As shown in the figure, in this embodiment, the cell with the highest priority order is constructed by the block b1 having the highest contribution to the coding quality SNR _seg , and the cell with the next highest priority order (of the cells). Cell) is assembled by the block b2, which has the second highest contribution to the coding quality SNR _seg after the block b1.

Similarly, the cells with the priority order are assembled by blocks b3 and b4.

As described above, according to the configuration in which the PCM signal is divided into blocks of 4 bits and the blocks bn are formed into cells, it is possible to assemble cells with half the number of samples in the conventional case. As a result, the cell delay time can be halved as compared with the conventional one.

Specifically, conventionally, 128 cells were required to assemble one cell, but in this embodiment, half the number of samples, that is, 64 samples can be assembled. As a result, it takes 10.4 msec to assemble one cell in the related art, whereas it can be assembled in half of 5.2 msec in this embodiment.

FIG. 9 is a diagram showing the cell transmission timing of this embodiment. As shown in the figure, in this embodiment, the cells of each block bn are transmitted at a cycle of 1.3 msec.
When 2 msec has elapsed, all blocks b1 to b4
The transmission of the cell is ended.

The above is the outline of this embodiment. next,
The configuration and operation of the cell assembling / separating apparatus for realizing such processing will be described.

First, the cell assembling apparatus will be described. 2 shows a cell assembling unit 13 (see FIG.
3) is a block diagram showing the configuration of FIG.

In the figure, reference numeral 131 denotes a buffer memory 131 for temporarily storing the PCM signal supplied from the coding units 12L and 12R (see FIG. 13) for each sampling period. 132 is this buffer memory 131
It is a central processing unit (hereinafter referred to as "CPU") that assembles cells from PCM signals stored in the.

Reference numeral 133 is a random access memory (hereinafter referred to as "RAM") used as a working memory when the CPU 132 assembles cells. 134 is R
This is a first-in first-out circuit (hereinafter, "FIFO") for temporarily storing the data of 4 cells assembled on the AM 133.

Reference numeral 135 is a register that holds the data output from the FIFO 134 for each one byte and sends the data to the ATM network in synchronization with the cell sending timing. 136
Is a header information generator that generates header information to be inserted in the header of a cell.

The RAM 133 has four regions R1 to R4 as shown in FIG. Each region Rn has a capacity of one cell and corresponds to the block bn.

The cell assembling process in the above configuration will be described. Encoding units 12L and 12R for each sampling period
The PCM signal supplied from (see the figure) is temporarily stored in the buffer memory 131, and then provided to the cell assembling process by the CPU 132.

In the cell assembling process by the CPU 132, as shown in FIG. 4, the device is first reset to the initial state (step S11). This reset is executed, for example, when the power of the device is set to the ON state.

Next, the data for one sample stored in the buffer memory 131 is sequentially read out for each channel Lch and Rch in accordance with the operation timing of the CPU 132, and held in the internal register of the CPU 132 ( Steps S12, S13).

Next, the data of each channel Lch and Rch held in the internal register of the CPU 132 are sequentially read out for each block bn and stored in the corresponding area Rn of the RAM 133 (steps S14 and S15). ..

As a result, the data held in the internal register of the CPU 132 is divided into blocks and cells. In this cell conversion, the header information generation unit 13
A process of inserting the header information output from 6 into the header is also performed.

After this, it is judged whether or not the assembly of four cells is completed (step S16). If the assembly has not been completed, the process returns to step S12 and the above-described processing is repeated again.

By repeating this process 64 times, the assembly of 4 cells is completed. When this assembling is completed, the cells are stored in the RAM 13 in order from the cell having the highest priority.
The data is read from the data No. 3 and stored in the FIFO 17 (step S17).

When this storage is completed, it is determined whether or not the power supply is set to the off state (step S18). If it is not set to the off state, the process returns to step S12 and the assembly of the next four cells is executed. On the other hand, if it is set to the off state, the cell assembling process of the CPU 132 ends.

The cells stored in the FIFO 134 are sequentially read out one byte at a time and stored in the register 135. The data held in the register 135 is sent to the ATM network in synchronization with the cell sending timing.

The above is the configuration and operation of the cell assembling apparatus 10. Next, the configuration and operation of the cell disassembly device will be described. FIG. 5 is a block diagram showing the configuration of the cell disassembly unit 21 in the cell disassembly device 20 shown in FIG.

In the figure, reference numeral 211 is a register for holding cell data sent from the ATM network for each one byte. Reference numeral 212 is a FIFO that stores the data held in the register 211 for four cells.

Reference numeral 213 is a header information detecting section for detecting header information from the data held in the register 211 and judging whether or not the cell is addressed to the own station. When the header information detection unit 213 determines that the cell is addressed to the own station, the data held in the register 211 is transferred to the FIFO 212.

Reference numeral 214 is a CPU for executing cell disassembly processing.
Is. A RAM 215 is used as a work memory when the CPU 214 executes the cell disassembly process. Two
16 is 1 obtained by the cell disassembly processing of the CPU 214.
The data for the sample is temporarily held, and the decoding unit 22
It is a buffer memory that supplies L and 22R (see FIG. 13).

The RAM 215 also has four regions R1 to R4, like the RAM 133 in the cell assembly section 13.

The cell disassembly process in the above configuration will be described. The cells sent via the ATM network are sequentially held in the register 211 one byte at a time. The held data is supplied to the FIFO in synchronization with the operation timing of the CPU 214 and the like only when it is addressed to its own station.

As a result, when the data for four cells is stored in the FIFO 212, this data is provided to the cell disassembly processing by the CPU 214. In this cell disassembly process, as shown in FIG. 6, first, as the power is turned on,
The device is set to the initial state (step S21).

Next, 1 stored in the FIFO 212
The data for cells are sequentially stored in the RAM 215 one byte at a time.
Are stored in the corresponding area Rn (step S22).
Next, by this processing, the data of 4 cells is stored in the RAM 21.
5 is determined (step S2).
3).

If it is not stored, the process returns to step S22 and the storing process is executed again. When this storage process is repeated four times, data for four cells is stored in the RAM 215.

When this storage is completed, the data of each block bn of the left channel Lch is sequentially read from each area Rn of the RAM 215 and stored in the internal register of the CPU 214 (step S24). Next, similarly, the data of each block bn of the right channel Lch is sequentially read and held in the internal register of the CPU 214 (step S25).

These processes correspond to the process of reconstructing the PCM signal for one sample by decomposing cells for each block and combining the blocks obtained by this decomposing for one sample.

After this, 1 stored in the internal register
The data for the sample is transferred to the buffer memory 216 for each channel Lch and Rch and held in the buffer memory 216 (S26, S27).

Next, it is judged whether or not 64 samples of data have been transferred to the buffer memory 216 (step S
28) If the transfer is not completed, the process returns to step S24, and the above-described processing is repeated.

On the other hand, if the transfer is completed, it is judged whether or not the power supply is set to the off state (step S2).
9), if it is not set to the off state, step S2
Returning to step 2, the disassembling process for the next 4 cells is executed. On the other hand, if the power is off, the CPU 2
The cell disassembly processing of 14 ends.

The sample data held in the buffer memory 216 is transferred to the coding units 22L and 22R in accordance with the operation timing of the decoding units 22L and 22R.

According to this embodiment described in detail above, the following effects can be obtained.

(1) First, the PCM signal is divided into blocks with a bit number twice the minimum quantization bit number, and each block b
Since cells are formed for every n, the cell formation delay time can be reduced to half of the conventional one. This can contribute to real-time transfer of the audio signal.

(2) Since the PCM signal is divided into blocks based on the contribution to the coding quality SNR _{seg and} cells having higher priorities are assembled into blocks having higher contribution, the coding quality SNR _seg due to cell discarding Can be suppressed.

That is, in this embodiment, when the cell discard occurs, the cell assembled by the block b4 is most likely to be discarded. However, even if this cell is discarded, as shown in FIG. 10, the coding quality SNR is
_Seg hardly deteriorates.

Next, a second embodiment of the present invention will be described. FIG. 11 is a diagram showing the structure of the information field of the cell of this embodiment.

In the above embodiment, the case where all the areas of the information field of the cell are assembled by the block bn has been described. On the other hand, in this embodiment, as shown in FIG. 11, an area R1 for 32 bytes in the first half of the information field is provided.
Reference numeral 1 is an assembly of blocks bn, and an area R12 of 32 bytes for the latter half is an empty area.

According to such a configuration, one cell can assemble a PCM signal for 32 samples, which is half that in the previous embodiment. As a result, as shown in FIG.
The cellization delay time can be set to 2.6 msec, which is half of that in the previous embodiment.

According to the processing of the CPU 132 of the cell assembling section 13, this is step S12 to step S shown in FIG.
This means that 16 processes can be completed 32 times as shown in parentheses. Similarly, the CPU 214 of the cell disassembly unit 21
It means that the processing of steps S24 to S28 in FIG.

In this case, although the frequency of use of cells is twice as high as that of the previous embodiment, it can be said that this is an effective method when the number of cells allocated for audio signal transfer is large.

Although two embodiments of the present invention have been described above, the present invention is not limited to such embodiments.

(1) For example, in the above first and second embodiments, the case where the number of bits of each block bn is set to twice the minimum quantization bit number has been described, but it is set to three times or more. You may do it. In this case, the cellization delay time is reduced to 1/3, 1/4, ...

(2) In the second embodiment, the half of the information field of the cell is set as the empty area. However, an area larger than half or a small area may be set as the empty area. Good.

(3) In the above embodiment, the case where cells having a higher priority order are assembled in blocks having a higher contribution to the coding quality SNR _seg has been described.
It is not necessary to perform such assembly.

(4) Further, in the above embodiment, the case where the present invention is applied to cell conversion of an audio signal has been described.
It may be applied to the cell conversion of other signals such as image signals.

(5) In addition to the above, the present invention can of course be variously modified without departing from the scope of the invention.

[0103]

As described above in detail, the present invention can shorten the cell formation delay time when the priority order of cells is taken into consideration, and can contribute to the real-time transfer of information.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an invention according to claim 4;

FIG. 2 is a block diagram showing a configuration of a cell assembling unit according to the first embodiment.

FIG. 3 is a diagram showing a configuration of a RAM according to a first embodiment.

FIG. 4 is a flowchart showing a cell assembling process of the first embodiment.

FIG. 5 is a block diagram showing a configuration of a cell disassembly unit of the first embodiment.

FIG. 6 is a flowchart showing a cell disassembly process of the first embodiment.

FIG. 7 is a diagram for explaining blocks of the first embodiment.

FIG. 8 is a diagram showing a configuration of a cell of the first embodiment.

FIG. 9 is a timing chart showing cell transmission timing of the first embodiment.

FIG. 10 is a characteristic diagram for explaining the effect of the first embodiment.

FIG. 11 is a diagram showing a configuration of a cell according to a second embodiment.

FIG. 12 is a timing chart showing cell transmission timing of the second embodiment.

FIG. 13 is a block diagram showing a configuration of a cell assembling / disassembling apparatus.

FIG. 14 is a timing chart showing the relationship between cell head signals, data clocks, and cells.

FIG. 15 is a block diagram showing a configuration of an encoding unit.

FIG. 16 is a diagram for explaining the structure of a PCM signal.

FIG. 17 is a timing chart for explaining the number of cells transmitted per sampling cycle.

FIG. 18 is a diagram showing the configuration of a cell when priority order is not considered.

FIG. 19 is a timing chart showing cell transmission timing when priority order is not considered.

FIG. 20 is a diagram showing a configuration of a conventional cell in the case of considering a priority order.

FIG. 21 is a timing chart showing a conventional cell transmission timing in the case of considering the priority order.

[Explanation of symbols]

 30 Cell Assembling Device 31 Band Division Coding Means 32 Blocking Means 33 Cell Assembling Means 40 Cell Disassembling Means 41 Cell Disassembling Means 42 Coded Signal Reproducing Means 43 Decoding Means

Claims (4)

[Claims] 1. In a cell assembling apparatus for assembling a cell which is an information transfer block in an asynchronous transfer mode in consideration of a priority order, a transmission signal is divided into a plurality of bands, and band division encoding is performed for each band. The means (31) and the transmission signal encoded by the band division encoding means (31) are divided into a plurality of blocks for each bit number N (integer of 2 or more) times the minimum quantization bit number. A cell assembling apparatus comprising: blocking means (32); and cell assembling means (33) for assembling the cell for each block obtained by the blocking means (32). 2. The cell assembling means (33) is constructed such that only a partial area of the cell is assembled by the block and the remaining area is an empty area. Cell assembly equipment. 3. A signal obtained by dividing a transmission signal into a plurality of bands, encoding the divided signal, and dividing the coded signal for each bit number N (integer of 2 or more) times the minimum quantization bit number. In a cell disassembling device for disassembling cells assembled in blocks, cell disassembling means (41) for disassembling the cells in each block, and one block obtained by the disassembling process of the cell disassembling means (41). A coded signal reproducing means (42) for dividing and reproducing the coded signal, and a decoding means (43) for decoding the coded signal reproduced by the coded signal reproducing means (42) are provided. A cell disassembling device characterized in that 4. A cell assembling / disassembling apparatus for assembling and disassembling a cell, which is an information transfer block in an asynchronous transfer mode, in consideration of priority order, divides a transmission signal into a plurality of bands, and for each band. The band division encoding means (31) for encoding, and the transmission signal encoded by the band division encoding means (31) for each bit number N (integer of 2 or more) times the minimum quantization bit number. Blocking means (32) for dividing into a plurality of blocks, cell assembling means (33) for assembling the cell for each block obtained by the dividing processing of the blocking means 32, and this cell assembling means (33). The cell disassembling means (41) for disassembling the cells assembled by (4) and the blocks obtained by the disassembling process of the cell disassembling means (41) are combined for one sample. The encoding signal reproducing means (42) for reproducing the encoded signal and the decoding means (43) for decoding the encoded signal reproduced by the encoding signal reproducing means (42) are provided. Cell assembling / disassembling device.