JP3388683B2 - Signal multiplexing device - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to, for example, an ATM.
(Asynchronous transfer mode) In communication, it is applied to a cell assembling device that generates cells that store low bit rate audio signals, and it is possible to multiplex the audio signals of multiple lines to shorten the cellization delay time. The present invention relates to a signal multiplexer.

[0002]

2. Description of the Related Art In an ATM network, a signal processing circuit before cell assembly is carried out for the purpose of transmitting voice signals of as many lines as possible within a predetermined transmission capacity (cell transmission rate) range. (Voice CODEC) is used to perform processing such as high-efficiency coding / silence compression. The cell assembling circuit multiplexes the voice signal processed for each line by a plurality of CODECs in units of one block (CODEC frame) of the output signal and stores it in the cell. Since the bit rate of the audio signal after being processed by the CODEC is low, it takes time to accumulate a signal that can be stored in one cell if only one line of the audio signal is converted into cells. In order to suppress this increase in delay, the voice signals of a plurality of lines are multiplexed into cells.

FIG. 4 shows the overall structure of the cell assembling apparatus. Audio signals S1, S from the channels ch1, ch2 ... chn
, ..., Sn are compressed and encoded by audio CODECs (signal processing circuits) CD1, CD2, ..., CDn, respectively, and these compressed audios Cs1, Cs2 ,. And cell assembly circuit 12
Is supplied to. There are various processing algorithms in voice CODEC, but in this example, μ-law voice to CS-AC are used.
The input / output timing will be described by taking an example of converting to ELP compressed voice.

Μ-law is 1 Byte in a cycle of 125 μs.
It is an encoding algorithm for transmitting and receiving the signal of. CS-A
CELP takes 10 Bytes (1 CODEC at 10 ms cycle)
This is an encoding algorithm for transmitting and receiving a frame signal. Cycle of the signal processing of the CODEC so 10 ms, is input to the periodic of 125μs, as shown in FIG. 5A 80B
The y-μ-law signal is processed and a 10-byte compressed audio signal is output. The output timing of the CODEC is determined by the 10 ms interval (one frame period). CO for each line chi (i = 1, 2, ..., N)
When multiple DEC CDi operate in parallel, all C
Since the frame cycle of ODEC CDi does not necessarily need to be synchronized, the frame cycle can be set so that a desired output timing can be obtained as shown in FIG. When the output bit rate of CDi is 2.048 Mbps, 39.06 is required to serially output 10 Byte.
Since it takes only 25 μs, it is possible to perform a maximum of 256 multiplexing within 10 ms (one frame period) (since the signal amount on the input side is 8 times, the bit rate is 16.382 M).
bps). A signal thus multiplexed is
The cell assembling circuit 12 is stored in the TM cell. The cell format is 5 bytes as shown in FIG.
The standard cell header H at the beginning, 1Byte Oite 3 B
The packet header h of yte and the set of the packet are sequentially packed. Each packet is 10 bytes, that is, the output data for one frame of CODEC.
The total length of the cell is 53 Bytes, and when the cell becomes full in the middle of one packet, the rest is stored in the next cell.

The cell assembly delay time is the shortest when the stored signal to the cell is provided without interruption. Further, when the number of ATM cells generated in this way and the number of cells sent to the transmission line are balanced, there is almost no possibility that the ATM cells will be stuck in the buffer and cause a delay or overflow from the buffer and be discarded. Therefore, high call quality can be realized, and there is no vacancy in the transmission line capacity, so that cells can be transmitted most efficiently.

When the number of lines is less than 256, the signal multiplex processing device 13, that is, CODEC CD1 to CD
Depending on the configuration of n and the multiplexing circuit 11, a difference occurs in call quality and cell transmission efficiency. Taking the case of multiplexing 32 lines as an example, conventionally, as shown in FIG. 2C, 32 CODECs are used.
The processed signals are output from the CD1 to CD32 at the justified timing (for example, the 1st to 32nd slots: 1 slot is 10 Bytes), and no data is output at the subsequent 224 CODEC output timings (33 to No. 256 slot). Moreover, it is difficult to perform multiplexing so as to output signals except for a specific output timing.

[0007]

When the time-biased multiplex processing is performed in this manner, a large number of ATs are continuously connected when data is continuously input to the cell assembling apparatus.
M cells are generated (slots 1 to 32). But,
Since no data is input in slots 33 to 256, no cell is generated until the data in the next slot 1 is input (7 times as long as 32 slots). When the cell generation timing is biased in this way, the ATM
In the network, it is necessary to secure the transmission line capacity equal to the cell generation rate and immediately transmit the cells, or it is necessary to temporarily store the cells generated before the transmission and then sequentially transmit the cells.

If a high transmission line speed is ensured, there is a problem that the transmission line capacity is wasted while cells are not generated. In addition, it is necessary to increase the capacity of the transmission buffer in order to store the cells generated in a concentrated manner. If a sufficient buffer is provided, the scale of the device becomes large, and a large cell transmission delay is added as cells are generated and the number of stored cells increases, so that there is a problem that speech quality deteriorates. An ATM that cannot be stored if the buffer size is reduced and the increase in device size is suppressed.
There is a problem that the quality of voice is deteriorated because the cell is discarded and the number of voice signals to be transmitted is reduced. If the number of signals is less than one cell even after storing the last input signal, the cell generation is not completed and the next signal is input (10 ms-39.06 μs × 32 = 8. 749
I had to wait ungenerated for more than 44 ms. That is, a large cell generation delay time is generated, fluctuation of the delay time of the voice signal becomes large, and there is a problem that the communication quality deteriorates.

Further, when a specific slot is not used, such as when it is necessary to stop a part of the audio processing circuit, there is a problem that it is not possible to exclude only that slot for multiplexing. Further, not only the ATM cell assembling apparatus, but when each compressed signal is processed after multiplexing, there is a problem that the processing cannot be performed properly depending on the interval between the compressed signals.

[0010]

The signal multiplexing apparatus of the present invention is provided with output timing means for controlling the output timing of the CODEC so that the processed audio signal is output at an arbitrary time interval, and the audio after the CODEC processing is processed. It is possible to multiplex signals at arbitrary time intervals without delay. If multiple processing is performed at equal time intervals, it is possible to solve the above-mentioned problems caused by concentrated generation of cells, and it is possible to perform multiplexing except for a specific slot.

[0011]

FIG. 1 shows a first embodiment of the present invention. This is an example when the maximum number of lines is 256. Line ch
1 to ch256 via the line selection circuit 21,
It can be connected to any one of the signal processing circuits (CODEC) CD1 to CD256. The control circuit 16 controls the selection of the line selection circuit 21 and the signal processing circuits CD 1 to CD 256.
Perform, such as the control. The multiplex output clock of the multiplex circuit 11 is divided into 1/80 in this example, and the divided output is counted by the 256-ary ring counter 24, and the 1st to 256th output terminals of the ring counter 24 are counted. Is a signal processing circuit CD through switches SW1 to SW256, respectively.
1 to CD256. On the other hand, the number of used lines n is set in the arithmetic circuit 25, and the line selection circuit 21 and the switches SW1 to SW256 are controlled according to the arithmetic result of the arithmetic circuit 25.

The output bit rate of the multiplexing circuit 11 is 2.0.
At 48 Mbps, it takes 39.0625 μs to output 10 Bytes (80 bits), so 10
The number of output lines that can be multiplexed within ms is 256. On the other hand, the input signal to the signal processing circuit CDi is given by 1 Byte every 125 μs (in the case of μ-law input). When a signal of 256 lines is input, since the number of input lines is equal to the maximum value of the number of output lines, there is no vacancy in the multiplex output, and the cell assembling circuit 12 receiving this is given a signal without interruption. The delay time is the shortest and there is no fluctuation in the delay time. The example circuit provides an output bit rate of 2.048 MHz.
Divide the clock by 1/80 in the frequency dividing circuit 23 to 2
Generate a 5.6 kHz reference signal and
The hexadecimal ring counter 24 is operated to operate 256 CODs.
The 256 timing control signals for sequentially outputting the EC CD1 to CD 256 are generated. These control signals are switches SW1 and SW2 that are opened and closed by the arithmetic circuit 25.
56 to CODEC CD1-CD256. If the number of input lines is 256, all switches SW1
~ By closing SW256, all code from No. 1 CODEC CD1 to No. 256 CODEC CD256
C operates and outputs in order.

When multiplexing at equal time intervals, the arithmetic circuit 2
In step 5, the following calculation is performed. m = [(k−1) × 256 / n] +1 (1) [x] is the maximum integer not exceeding x, n is the number of lines, and k is n.
The following integer. A signal for closing the m-th switch is output based on the calculation result. If n = 256, m = 1,
2, ... 256, all switches SW1 to SW
256 are sequentially closed every 80 / 2.048 × 10 ⁻⁶ .
Therefore, the output of the multiplexing circuit 11 at this time is given data to each slot as shown in FIG. 2A.

If the number of lines is 32, n = 32, and from the equation (1), m = 1, 9, 17, ... 241, 249
And switches SW1, SW9, SW17, ... S
W241, SW249, that is, every 8 pieces 32 at equal intervals
Close the switches in sequence. If there is a constraint on the used slot number, the constraint can be satisfied by closing another (for example, adjacent) switch instead of the switch of the unused slot.

In this way, the control circuit 16 has the CODEC.
At the same time as outputting the control signal, it outputs a line selection signal to the line selection circuit 21, and the line selection circuit 21 outputs the above m (= 1,
9,17, ... 241,249) th CODEC
The signals of 32 lines input to are selected so as to have a one-to-one correspondence. When the numbers of the control signal and the selection signal (that is, the operating CODEC numbers) are evenly spaced, the output signals are output at equal time intervals as shown in FIG. 2B. In the multiplexing circuit 11, if the processed audio signal output from the CODEC is time-division-multiplexed, the multiplexed signal can be transferred to the cell assembly circuit 12 at equal time intervals.

Further, the value of m can be arbitrarily determined without being bound by the equation (1), so that a signal multiplexed at an arbitrary time interval can be easily obtained. FIG. 3 shows a second embodiment of the present invention, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals. In this example, the voice line is a case where signals of a plurality of lines are input to the line selection circuit 21 which is time-division multiplexed. While the line selection circuit 21 of the first embodiment is a space switch, the line selection circuit 2 of the second embodiment is used.
1 is a time switch. That is, the line selection circuit 21 selects the time slot of a specific line by the line selection signal provided from the control circuit 16 for each CODEC, and the CODEC captures and processes this signal. C running
By setting the ODEC number to any value (including equal intervals), the output signal is output at any time interval, and the signal multiplexed at any time interval can be transferred to the cell assembly circuit 12. Is the same as in the first embodiment.

[0017]

The following effects can be obtained by using the signal multiplexing device of the present invention. 1. By the control signal and the line selection signal output from the control circuit 16, there is an effect that a signal time-division multiplexed at an arbitrary time interval can be easily obtained. In the case of multiplexing at equal time intervals, the following effects are obtained in particular.

2. Since the number of cells generated in the cell assembling circuit 12 is averaged over time, if the transmission line speed corresponding to the average value of the cell generation speed is secured, most of the transmission line capacity is constantly used. Therefore, there is no waste of bandwidth. 3. Since the cells are generated at almost constant time intervals and are not concentrated at one time, it is not necessary to increase the capacity of the transmission buffer. That is, even if a sufficient buffer is provided, the scale of the device does not become larger than the conventional one, and the cell transmission delay becomes small, so that high communication quality can be maintained.

4. Since it becomes less likely that ATM cells cannot be stored due to insufficient buffer capacity, the cell discard rate is reduced and high speech quality can be maintained. 5. Since the output interval of signals after multiplexing is constant, even when the number of signals is less than 1 cell after storing the signals, the maximum value of the time until the next signal is input is higher than that of the conventional method. Averaged in a short time. Therefore, there is almost no fluctuation in the delay time of the voice signal, and high communication quality can be maintained.

6. Furthermore, the present invention can solve the same problem as in the above-mentioned cell forming process when the multiplexed signal is processed for each compressed signal, not limited to the ATM cell forming device. In the line selection circuit 21, any line is connected to any CO
Since the order of the output of the CODEC is fixed because it can be selectively connected to the DEC, the order in the multiplexed output can be changed without delay.

In the above embodiment, an example of the maximum multiplexing number of 256 lines is shown, but it is conversely small when the number of cells is larger than 256 lines depending on the size of the cellizing device to be applied and the output bit rate of the multiplexing circuit. Needless to say, similar effects can be obtained by adopting the configuration of the present invention. In addition, the processing algorithm of the signal processing circuit is μ-la.
Although the w: CS-ACELP conversion is taken as an example, it goes without saying that the same effect can be obtained by controlling the output timing as in the present invention even with other processing algorithms.

In the above embodiment, an example in which the arithmetic circuit 25 is included in the control circuit 16 has been shown, but the same calculation as in the above embodiment is performed outside the control circuit 16, and the switch is closed according to the result. It goes without saying that the same effect can be obtained with. It is needless to say that when the number of lines is constant, the calculation result is fixedly given in advance and a specific switch is closed to obtain the same effect. In this case, the arithmetic circuit 25 and the unused CODEC can be omitted.

In the above-mentioned embodiment, an example in which the frequency dividing circuit 23 is included in the control circuit 16 has been shown. However, by dividing the multiple output clock outside the control circuit 16 and giving it to the ring counter 24, the same operation is performed. It goes without saying that the effect can be obtained. In the above-mentioned embodiment, the control signals are equal to the number of lines (256 lines).
As shown in the figure, an encoder is arranged on the control circuit 16 side, and C
It is possible to reduce the number of control signal lines (for example, eight) by disposing a decoder in both or either of the ODEC and the line selection circuit 21.

The output of the ring counter 24 is CODEC
It may be applied to any of CD1 to CD256, and the output timing of each CODEC may be freely changed, whereby the interval of compressed signals may be controlled.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of a signal multiplexing apparatus of the present invention.

FIG. 2A is a diagram showing 256 multiple outputs of the signal multiplexer of the present invention, B is a diagram showing 32 multiple outputs of the signal multiplexer of the present invention, and C is 32 multiple outputs of the conventional signal multiplexer. FIG.

FIG. 3 is a diagram showing a second embodiment of the signal multiplexing apparatus of the present invention.

FIG. 4 is a diagram showing an overall configuration of a cell assembly device.

FIG. 5 is a diagram showing an example of output timing setting.

FIG. 6 is a diagram showing a cell format.

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Claims (2)

(57) [Claims] 1. A processing input signals from any of a plurality of lines at a predetermined number of selected CODEC in the CODEC,
In a signal multiplexer for outputting the processed signal in a time shorter than the output time interval and time-division-multiplexing the processed signals from these CODECs with a multiplexing circuit, the above-mentioned arbitrary plurality of lines are connected. It provided between the predetermined number of CODEC, the line selection circuit for selecting connecting the line and the CODEC, based on the result calculated in accordance with the number of used lines, the plants
If you select the CODEC to use from the constant CODEC
A control signal for outputting a processed signal is given to the CODECs which are sequentially selected together , and a selection signal for selecting a line corresponding to the CODEC to which the control signal is given is given to the line selection circuit. A signal multiplexing apparatus comprising: a control unit. 2. The control means, according to the number of lines used,
From the predetermined number of CODEC so that the distance signal after processing the adjacent at the output of the multiplex circuits is substantially the same
The CODEC to be used is selected and the CO is sequentially selected.
2. The signal multiplexing apparatus according to claim 1, wherein a control signal for outputting a processed signal is given to the DEC .