JPH1141286A - Audio packet generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an audio packet generating circuit which can deal with plural compression coding systems through a common buffer memory or packet generating part and eliminates the interruption or fluctuation of audio signals at the time of switching. SOLUTION: At a 16k code decoding part 30A, a digital audio signal DAS on a data highway is converted to a 16kbps compression code CCA of 40 bits for a frame length. At an 8k code decoding part 30B, on the other hand, the digital audio signal DAS is converted to an 8kbps compression code CCB of 80 bits for the frame length. Both the compression codes CCA and CCB are divided to the audio data AD having the common multiple of their frame lengths such as 80 bits, for example, by a packet generating part 70 and an audio packet AP is generated by adding header information or the like. Besides, a timing setting part 90 supplies synchronized frame synchronizing pulses FP16 and FP8 to the respective code decoding parts 30A and 30B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice packet generating circuit for generating voice packets for performing voice communication using a packet communication network such as a local area network (hereinafter, "LAN"). It is.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional voice packet generation circuit. This voice packet generation circuit, for example,
It has a demultiplexing unit 1 connected to a digital exchange or the like via a 2 Mbps data highway. The demultiplexing unit 1 converts a multiplexed signal transmitted on the data highway from a 64 kbps PCM (Pulse Code Modulat
ion: a pulse code modulation) signal, which separates the digital audio signal of the individual audio channel into 64 kbp
s digital audio signals are multiplexed and transmitted to the data highway. The 16k code decoder 2A is connected to the demultiplexer 1. 16k code decoder 2A
Generates a 16 kbps compression code by compressing the bit rate of a 64 kbps PCM signal,
A digital audio signal is generated from a 64 kbps PCM signal from a ps compression code.

[0003] A buffer memory 4A is connected to the 16k code decoder 2A via a serial / parallel converter (hereinafter referred to as "SP converter") 3A. The SP conversion unit 3A
The compression code provided in the serial data format from the 16k code decoder 2A is converted into 8-bit parallel data and provided to the buffer memory 4A, and the parallel data provided in 8-bit parallel from the buffer memory 4A is converted into serial data. And outputs it to the 16k code decoder 2A. The packet generator 5A is connected to the buffer memory 4A. The packet generation unit 5A reads the compressed code stored in the buffer memory 4A, divides the read compressed code into audio data of a fixed length, and stores header information including a destination address and the like in each of the divided audio data. A voice packet is generated by adding an error detection code or the like for detecting a transmission error. The packet generator 5A has a function of extracting audio data from a given audio packet and writing the extracted audio data into the buffer memory 4A.
A LAN control unit 6 is connected to the packet generation unit 5A, and is connected to a LAN via the LAN control unit 6.

[0004] The demultiplexing section 1 is further connected to an 8k code decoding section 2B. The 8k code decoding unit 2B is 64k
8 kbps by compressing the bit rate of bps PCM signal
And generates a 64 kbps digital audio signal from an 8 kbps compression code. The 8k code decoder 2B includes the SP converter 3
A, a buffer memory 4A, and an SP converter 3B, a buffer memory 4B, and a packet generator 5B having substantially the same functions as those of the packet generator 5A are sequentially connected.
The SP conversion unit 3B, the buffer memory 4B, and the packet generation unit 5B convert an 8 kbps compression code into an audio packet and also convert an audio packet into an 8 kbps compression code. A LAN control unit 6 is connected to the packet generation unit 5B, and is connected to a LAN via the LAN control unit. In such a voice packet generation circuit, when traffic on the LAN is small, the 16k code decoder 2A, the SP converter 3A, the buffer memory 4A, and the packet generator 5A
A high-quality call using a compression code of 16 kbps is performed.
When traffic on the AN becomes congested, the 8k code decoding unit 2B, SP conversion unit 3B, buffer memory 4B, and packet generation unit 5B make it possible to make a call at a data rate of 8 kbps. .

[0005]

However, the conventional voice packet generation circuit has the following problems.
The 16k code decoding section 2A and the 8k code decoding section 2B use different compression coding schemes, and the low-speed side (1
Data types such as a frame length of 6 kbps or 8 kbps are different. Therefore, there is a problem that the buffer memories 4A and 4B and the packet generators 5A and 5B must be provided in accordance with these data types. Further, since the 16k code decoder 2A and the 8k code decoder 2B operate in accordance with the timing of the digital audio signal provided from the demultiplexer 1, respectively, the 16k code decoder 2A and the 8k code decoder 2B When switching is performed, there is a problem that the synchronization is lost and the audio signal is temporarily interrupted. The present invention solves the problems of the prior art, and can cope with a plurality of compression coding schemes without requiring a duplicate buffer memory and a packet generation unit, and can cut off an audio signal at the time of switching. The present invention is to provide a voice packet generating circuit without the above.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a voice packet generating circuit for separating a signal multiplexed and transmitted on a data highway into a digital voice signal of a voice channel. And the digital audio signal separated by the separation means
A first encoding unit that compresses the data based on the frame synchronization pulse in the first encoding method, converts the compressed signal into a first compressed code having a frame length of m bits, and outputs the first compressed code. The digital audio signal is compressed by a second encoding method different from the first encoding method based on the second frame synchronization pulse, and the second audio signal having a frame length of n bits (where n ≠ m) is compressed. Second encoding means for converting the data into a compressed code and outputting the converted code. The audio packet generation circuit further includes a timing setting unit that generates the first and second frame synchronization pulses based on the digital audio signal and supplies the first and second frame synchronization pulses to the first and second encoding units, respectively. Selecting means for selecting the first or second encoding means based on the selection signal and outputting the first or second compressed code outputted from the selected encoding means; Storage means for sequentially storing the first or second compressed codes thus obtained and sequentially reading out the first or second compressed codes in the stored order; and The first or second compression code is divided into audio data having a length that is a multiple of m and n, and header information including a destination address of the audio channel in the audio data and transmission error detection. By adding an error detection code, and packet generation means for generating a voice packet to be outputted to the data transmission path is provided.

According to the present invention, since the voice packet generation circuit is configured as described above, the following operation is performed. The digital audio signal on the data highway separated by the separating means is converted into a first or second compressed code by the first or second coding means selected by the selecting means, and output through the selecting means. .
The first or second compression code output from the selection means is:
After being temporarily stored in the storage means, it is sequentially read out by the packet generation means, and the frame length of the first compression code m
The audio data is divided into audio data having a length that is a common multiple of bits and n bits, which is the frame length of the second compression code. Then, header information and an error detection code are added to the audio data to generate an audio packet.

[0008]

FIG. 1 is a configuration diagram of a voice packet generation circuit showing an embodiment of the present invention. This voice packet generation circuit has a demultiplexing unit (for example, a demultiplexing unit) 10 connected to a digital exchange or the like via a 2 Mbps data highway, for example. Demultiplexing unit 10
Separates a digital audio signal DAS of an individual audio channel by a 64 kbps PCM signal from a multiplexed signal transmitted on the data highway,
A digital audio signal DAS of an individual audio channel of 64 kbps is multiplexed and transmitted to the data highway. A selection unit (for example, a selector) 20 is connected to the demultiplexing unit 10. Further, the selector 20 includes
First encoding unit (for example, a 16k code decoding unit) 30A
And second encoding means (for example, an 8k code decoding unit) 30B
And are connected. The selector 20 outputs the selection signal SEL
According to the above, the 16k code decoding unit 30A or the 8k code decoding unit 30B is selected and connected to the demultiplexing unit 10.

[0009] The 16k code decoder 30A complies with the first encoding method, for example, the recommendation G.104 of the International Telecommunication Union-Telecommunication Standardization Division (hereinafter referred to as "ITU-T"). 728
LD-CELP (Low-delay Code Excit) standardized by
ed Linear Prediction: a low-delay code excitation type linear prediction) coding system code decoder. LD-CELP is 64
Developed in consideration of videophone voice using a kbps channel and application to a high-efficiency line multiplexing device, etc., a voice band signal sampled at 8 kHz is converted to a frame length of 40 bits and a frame period of 2 .5ms 16kbps
This is represented by a compression code. 16k code decoder 1
2A is 64 by this LD-CELP coding scheme.
The digital audio signal DAS of the kbps PCM signal is compressed to generate a compression code CCA of 16 kbps, and the digital audio signal DAS of 64 kbps is generated from the compression code CCA of 16 kbps. 8k
The codec 30B is provided with a second encoding method, for example, IT
Recommendation G. UT CS-AC standardized in 728
ELP (Conjugate Structure-AlgebraicCode Excited
Linear Prediction is a code decoder of a conjugate structure algebra excitation type linear prediction) coding method. CS-ACELP is developed in consideration of application to mobile communication and simultaneous communication of data and voice, and compresses a voice band signal sampled at 8 kHz into 8 kbps with a frame length of 80 bits and a frame period of 10 ms. It is represented by a code. The 8k code decoding unit 30B compresses the 64 kbps digital audio signal DAS of the PCM signal to generate an 8 kbps compression code CCB by this CS-ACELP coding method, and also converts the 8 kbps compression code CCB to 64k.
A digital audio signal DAS of bps is generated.

The compression code side of the 16k code decoder 30A and the 8k code decoder 30B is provided with a selecting means (for example, a selector)
40, and the selector 40 further includes an SP
The conversion unit 50 is connected. The selector 40 determines whether the 16k code decoder 30A or 8k
The code decoder 30B is selected and connected to the SP converter 50. The SP conversion unit 50 converts the serial data of 16 kbps or 8 kbps supplied from the selector 40 into parallel data of 8 bits and supplies the parallel data of 8 bits to a storage unit (for example, a buffer memory) 60. The parallel data provided in parallel is converted into serial data and output to the selector 40. The buffer memory 60 temporarily stores the compression codes CCA and CCB output from the SP conversion unit 50 in a parallel data format. This buffer memory 60
Is the compressed code C output from the 16k code decoder 30A.
A common multiple (for example, 80 bits = 10 bits) of 40 bits that is the frame length of CA and 80 bits that is the frame length of the compressed code CCB output from the 8k code decoding unit 30B
Bytes) or more. The buffer memory 60 is a so-called first-in-first-out (FIFO) buffer, and data written therein is sequentially read in the order in which the data was written. The buffer memory 60 is connected to a packet generator (for example, a packet generator) 70.

[0011] The packet generation unit 70 includes a buffer memory 6
The compression codes CCA and CCB stored in 0 are the 40-bit frame length of the compression code CCA output from the 16k code decoding unit 30A and the frame length of the compression code CCB output from the 8k code decoding unit 30B. It has a function of dividing and reading audio data AD having a length of a common multiple (for example, 80 bits) of 80 bits. The packet generation unit 70 generates a voice packet AP by adding header information including a destination address and the like to the beginning of each divided audio data AD and adding an error detection code and the like for transmission error detection to the end. Is what you do. Furthermore, the packet generation unit 70 converts the audio data A
It has a function of extracting D and writing it into the buffer memory 60. A LAN control unit 80 is connected to the packet generation unit 70, and is connected to a LAN via the LAN control unit 80. This voice packet generation circuit has timing setting means (for example, a timing setting unit) 90. Based on the 16 kHz clock signal CLK of the digital audio signal DAS supplied from the demultiplexing unit 10, the timing setting unit 90 outputs 16k code decoding units 30A and 30A.
Frame synchronization pulse FP1 for k code decoding section 30B
6, FP8, and a 16k code decoder 30A and an 8k code decoder 30B are connected to the output side, respectively.

FIG. 3 is a circuit diagram showing an example of the timing setting section 90 in FIG. This timing setting unit 90
Has a flip-flop (hereinafter referred to as “FF”) 91, and a clock signal C of 16 kHz is supplied from the demultiplexing unit 10 to a clock terminal C of the FF 91. The inverted output terminal / Q (where "/" means inverted) of the FF91 is connected to the input terminal D to form a 1/2 frequency dividing circuit. The output terminal Q is a 7-digit binary counter. 92 are connected to the clock terminal C. Output terminals Q <b> 0 to Q <b> 6 of the counter 92 are connected to seven input terminals of an OR gate 93 (hereinafter, referred to as “NOR”). When the count value of the counter 92 is “0”, the frame synchronization pulse FP8 for the 8k code decoding unit 30B is output to the output side of the NOR 93. Further, on the output side of the counter 92,
Inverters 94a to 94e and an AND gate (hereinafter, referred to as an AND gate)
A decoder 94 composed of an “AND” 94f is connected, and the count value of the counter 92 is “8”.
At the moment when the value becomes "0", the decoder 94
The reset signal is supplied to the reset terminal R of the second.

Further, the clock signal CLK is supplied to a clock terminal C of a 6-digit binary counter 95. Output terminals Q0 to Q5 of the counter 95 are connected to six input terminals of the NOR 96. When the count value of the counter 95 is “0”, 16 bits are output to the output side of the NOR 96.
Frame synchronization pulse FP1 for k code decoder 30A
6 is output. Further, the counter 95
Are connected to inverters 97a to 97d and AND9.
7e is connected, and the output side of the decoder 97 is connected to one input terminal of a two-input OR gate (hereinafter referred to as "OR") 98. A decoder 94 is connected to the other input terminal of OR98.
The output terminal of the OR 98 is connected to the reset terminal R of the counter 95. Thus, the counter 95 sets the count value to “40”.
At the moment, the reset signal is supplied from the decoder 97 and reset, and the decoder 94 resets the counter 92 simultaneously.

Next, the operation of FIGS. 1 and 3 will be described. For example, it is assumed that the 16k code decoding unit 30A is selected by the selection signal SEL given to the selectors 20 and 40 in FIG. The multiplexed signal of 2 Mbps on the data highway is separated into a digital audio signal DAS of an audio channel of 64 kbps by the demultiplexer 10, and is input to the 16k code decoder 30A via the selector 20. The clock signal CLK extracted from the digital audio signal DAS by the demultiplexer 10 is provided to the timing setting unit 90. Timing setting section 9
At 0, the clock signal CLK of 16 kHz is frequency-divided by 1/40 by the counter 95 and the decoder 97 in FIG. 3, and the frame synchronization pulse FP16 is output from the NOR 96 once every 2.5 ms. Further, the clock signal CLK is frequency-divided by FF91 to て, and
, And further divided by the counter 92 and the decoder 94 into 1/80.
A frame synchronization pulse FP8 is output from R93. Since the counter 95 is reset simultaneously with the counter 92 by the output signal of the decoder 94,
The two frame synchronization pulses FP16 and FP8 are always synchronized pulses. Then, these frame synchronization pulses FP16 and FP8 are respectively 16 k of FIG.
It is provided as a timing signal for the code decoder 30A and the 8k code decoder 30B.

The digital audio signal DAS given to the 16k code decoding section 30A is a frame synchronization pulse FP16.
, And is encoded into a 16 kbps compression code CCA in synchronization with. The compression code CCA for one frame (40 bits) is
The data is converted into a parallel code of 8 bits × 5 bytes by the SP conversion unit 50 and is sequentially written into the buffer memory 60 as 5-byte data. The data written in the buffer memory 60 is read by the packet generator 70 as audio data AD in units of 10 bytes. Further, the packet generator 70 adds the header information including the destination address and the transmission source address to the head of the 10-byte audio data AD, and adds the error detection code to the tail thereof to generate the audio packet AP. The voice packet AP is L
The data is transmitted to the LAN via the AN control unit 80. On the other hand, L
The voice packet AP transmitted on the AN is received by the LAN control unit 80, and only the packet whose destination address in the header information is addressed to itself is extracted.
Given to 0. In the packet generator 70, only the audio data AD in the received audio packet AP is extracted and written into the buffer memory 60.

The audio data AD based on the compression code CCA written in the buffer memory 60 is read out by the SP conversion unit 50, converted into 16 kbps serial data, and supplied to the 16k code decoding unit 30A via the selector 40. In the 16k code decoder 30A, the compressed code CCA
Is converted into a digital audio signal DAS based on a 64 kbps PCM signal,
Output to 0. In the demultiplexing unit 10, 64 kbp
s digital audio signal DAS is multiplexed to 2 MHz
Sent on the data highway. Here, the selectors 20 and 40 are switched by the selection signal SEL, and
When the k-code decoder 30B is selected, the digital audio signal DAS on the data highway separated by the demultiplexer 10 is sent to the 8k-code decoder 3 via the selector 20.
0B. At this time, a frame synchronization pulse FP8 synchronized with the frame synchronization pulse FP16 is given to the 8k code decoding unit 30B. For this reason, the digital audio signal DAS is encoded into a compression code CCB of 8 kbps by the 8k code decoding unit 30B without synchronization loss, and is output to the SP conversion unit 50 via the selector 40. Compression code CC for one frame (80 bits)
B is converted into a parallel code of 8 bits × 10 bytes by the SP conversion unit 50 and is sequentially written into the buffer memory 60 as 5-byte data.

The compression code CCB written in the buffer memory 60 is read out by the packet generator 70 as audio data AD in units of 10 bytes. Further, the packet generation unit 70 generates a voice packet AP by adding header information including a destination address and a transmission source address to the head of the 10-byte voice data AD and adding an error detection code to the tail thereof. The voice packet AP is transmitted to the LAN via the LAN control unit 80. As for the voice packet AP transmitted on the LAN, only the packet addressed to itself is extracted by the LAN control unit 80, and the packet generation unit 70
Given to. In the packet generator 70, only the audio data AD in the received audio packet AP is taken out,
The data is written into the buffer memory 60. Buffer memory 60
The audio data AD with the compression code CCB written in
The data is read out by the SP conversion unit 50, converted into 8 kbps serial data, and provided to the 8k code decoding unit 30B via the selector 40. In the 8k code decoder 30B,
The compression code CCB is a digital audio signal D of 64 kbps.
AS is converted to AS, and is passed through the selector 20 to the multiplex / demultiplex unit 10.
Are multiplexed in the demultiplexer 10 and transmitted on a 2 MHz data highway. As described above, the voice packet generation circuit according to the present embodiment has the following (1)
(3).

(1) A frame synchronization pulse FP1 synchronized with the 16k code decoder 30A and the 8k code decoder 30B
6, since the timing setting unit 90 for supplying the FP8 is provided, the switching of the 16k code decoding unit 30A and the 8k code decoding unit 30B does not interrupt the voice signal during the call. (2) The length of the audio data AD of the audio packet AP generated by the packet generation unit 70 is determined by the frame length (40 bits) generated by the 16k code decoding unit 30A and the frame length generated by the 8k code decoding unit 30B ( 80 bits)
Is set to be a common multiple of. As a result, the packet generation unit 70 outputs the audio data A regardless of the encoding method.
Since D can always be treated as a fixed-length voice packet AP, the common packet generator 70 can support different encoding schemes, and the circuit configuration is simplified. (3) The length of the audio data AD is always the compression code CC.
It is an integral multiple of the frame length of A and CCB. Thereby, the 16k code decoder 30A and the 8k code decoder 30B
In this case, the process of converting the compression codes CCA and CCB into a 64 kbps PCM signal is performed smoothly, and the cause of the "fluctuation" of the audio signal caused by the packet communication can be eliminated.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (e). (A) LD-CE as the code decoders 30A and 30B
Although the LP and CS-ACELP coding schemes are used, other coding schemes can be similarly applied. (B) Two types of code decoding units 30 by the selectors 20 and 40
A, 30B, one is selected, but three or more types of code decoding units 30A, 30B,.
One may be selected. (C) The configuration of the timing setting circuit 90 is not limited to the circuit configuration of FIG. 3, and any configuration may be used as long as it can supply synchronized frame synchronization pulses FP16 and FP8 to the codec units 30A and 30B. Such a circuit configuration may be used. (D) The buffer memory 60 is not limited to the FIFO,
Any configuration can be applied as long as it can temporarily store the compression codes CCA and CCB. (E) If the compression codes CCA and CCB input and output to the code decoders 30A and 30B are in the parallel data format, the SP converter 50 is unnecessary.

[0020]

As described above in detail, according to the present invention, an audio packet is generated by audio data having a length which is a common multiple of the frame lengths of the first and second encoding schemes. In addition, the packet generation means can be commonly used regardless of the encoding method, and the apparatus can be simplified. In addition, since the length of the audio data is always an integral multiple of the frame length, the conversion process for restoring the compressed code to a digital audio signal by the encoding means is performed smoothly, and the audio signal due to packet communication is converted. "Fluctuation" can be prevented. Further, since the first and second encoding means have timing setting means for supplying synchronized first and second frame synchronization pulses, there is no interruption of speech during switching of the encoding method. There is.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a voice packet generation circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional voice packet generation circuit.

FIG. 3 is a circuit diagram showing an example of a timing setting unit 90 in FIG.

[Explanation of symbols]

 Reference Signs List 10 demultiplexing unit 20, 40 selector 30A 16k code decoding unit 30B 8k code decoding unit 50 SP conversion unit 60 buffer memory 70 packet generation unit 80 LAN control unit 90 timing setting unit

Claims (1)

[Claims] 1. Separating means for separating a signal multiplexed and transmitted on a data highway into a digital audio signal of an audio channel, and separating the digital audio signal separated by the separating means.
A first encoding unit that compresses the data based on the first frame synchronization pulse using a first encoding method, converts the compressed data into a first compressed code having a frame length of m bits, and outputs the first compressed code; Said digital audio signal
Based on the second frame synchronization pulse, the data is compressed by a second coding method different from the first coding method, and is converted into a second compressed code having a frame length of n bits (however, n ≠ m). Second encoding means for generating and outputting the first and second frame synchronization pulses based on the digital audio signal, and supplying the first and second frame synchronization pulses to the first and second encoding means, respectively. Selecting the first or second encoding means based on the selection signal, and selecting the first or second encoding means output from the selected encoding means.
Or selecting means for outputting a second compressed code, and sequentially storing the first or second compressed code output from the selecting means, and storing the first or second compressed code in the stored order. A storage unit that can be sequentially read, and the first or second compressed code that is sequentially read from the storage unit is divided into audio data having a length that is a common multiple of m and n, and the audio data is divided into the audio data. Packet generating means for generating a voice packet to be output to a data transmission path by adding header information including a destination address of a channel and an error detection code for detecting a transmission error. Generation circuit.