JPH05235986A - Monitor system for switch error - Google Patents

Abstract

PURPOSE:To provide the switch error monitor system in which all components forming unit information are used as generating components to generate and add an error check code and to send an input port number with respect to the system monitoring a transmission error of a path share switch for unit information of a fixed length. CONSTITUTION:An error check code generating addition circuit 12 uses all components forming unit information for a generating component to generate an error check code and adds the code to the unit information. An error check circuit 13 has only to compare an error check code in the unit information shared by a switch 11 to check an error of unit information without implementing calculation for error check.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch error monitoring system, and more particularly to a system for monitoring a transmission error of a route distribution switch for fixed length unit information.

Packet switching systems and ATM (Asynchronous
In the Transfer Mode (asynchronous transfer mode) method, identification information included in a fixed-length information unit, which is called a packet or a cell and is composed of a pair of transmission information and identification information, is referred to,
Routes of fixed-length information units are distributed by switches.

Therefore, in the packet switching system and the ATM system, it is indispensable to monitor a transmission error of a switch for routing a packet or a cell, and it is important that the error monitoring can be performed accurately and easily.

[0004]

2. Description of the Related Art In the ATM system, cells CE ₁ , CE ₂ and CE ₃ are combined in time series and transferred as shown in FIG. Each of the cells CE _{1 to} CE ₃ has k bytes (for example, 5
It has a fixed length of 4 bytes, and has a configuration in which a header that is identification information indicating an outgoing route and the like and data that is transmission information are paired. Further, the cells CE _{1 to} CE ₃ are not always adjacently time-division multiplexed, but empty cells (invalid information) as indicated by O ₁ and O ₂ in FIG. 10 are appropriately inserted.

In the ATM system, as shown in FIG.
For example, an n × n switch 1 having n input ports and n output ports is used to perform routing of input cells of input ports. That is, the n × n switch 1 is a space switch in the speech path of the ATM switch, and refers to the header of the cell input to each input port in the form shown in FIG. 10, and outputs the cell to the output port to be output. The output switching is autonomously performed by hardware.

As a result, for example, the cells CE input to the input ports # 1, # 3, and #n of the switch 1 shown in FIG.
_If the output routes of ₁₁ , CE ₃₂ , CE _n3 are the output ports #n of the switch 1, the cells CE ₁₁ , CE ₃₂ , C are output.
E _n3 is time-sequentially combined and taken out from the output port #n as shown in FIG.

In the ATM system for performing such switching, in order to monitor the occurrence of a transmission error in the switch 1, conventionally, as shown in FIG. 12, a parity calculation circuit 2 is provided corresponding to each input port of the switch 1. _{1 to} 2 _n are provided, and parity check circuits 3 _{1 to} 3 _n are provided corresponding to the output ports of the switch 1, respectively.

Each of the parity calculation circuits 2 ₁ to 2 _n has, for example, a _{1 to} a _n , b _{1 to} b _n , ..., As shown in FIG.
For cells having 53 bytes of valid information consisting of h _{1 to} h _n , horizontal parity bits A to H of bit interleaving are calculated by the following formula and added to the valid information as shown in FIG.

[0009]

[Equation 1]

When odd parity is used, n bits are used.
Generating element a₁~ A_nIf there is an odd number of "1" s in Paris
When tibit A is set to "0" and even parity is set
Is a ₁~ A_nIf there is an even number of "1" s, set A to "0"
(The same applies to the other parity bits B to H).

As shown in FIG. 13, each of the parity calculation circuits 2 ₁ to 2 _n adds the 8-bit parity bits A to H calculated as described above to the 53-byte effective information and sends it to the switch 1. Output. Therefore, as shown in FIG. 14, the transfer format of the signals output from the parity calculation circuits 2 _{1 to} 2 _{n in} parallel is as follows. As shown in FIG. 14, cells CE composed of valid information 5 and additional parity bits 6 are combined, and empty cells are also used. It is a format in which O is appropriately inserted.

The parity check circuits 3 _{1 to} 3 _n shown in FIG.
Of the parity bits A to H and their generating elements a ₁ to.
An exclusive OR operation (operation modulo 2) with a _n , ..., h _{1 to} h _n is performed (that is, (n + 1) -bit exclusion consisting of 1-bit parity bit and n-bit generator) When the operation result is odd parity, it is determined to be normal, and when it is even parity, it is determined to be normal, and otherwise it is determined to be abnormal.

[0013]

However, the above-mentioned prior art
In the switch monitoring system, the parity calculation circuit 2₁~ 2
_nIn each of the above, for 8 × n bits of effective information for each cell
To get 8 parity bits, and therefore a parity check
Circuit 3₁~ 3_nFor each of the
Since it is necessary to check the
It is relatively troublesome. Also, which input port of switch 1
It is difficult to detect whether there is an error in the cell entered in
Poor ability.

The present invention has been made in view of the above points,
An object of the present invention is to provide an error monitoring system for a switch that solves the above-mentioned problems by generating and adding an error detection code using all the constituent elements that constitute unit information as generating elements and transmitting an input port number. And

[0015]

FIG. 1 shows a block diagram of the principle of the invention according to claim 1. The present invention relates to an error monitoring system for a switch 11 that performs route allocation by referring to identification information of fixed-length unit information consisting of a pair of transmission information and identification information. Error detection code generation / addition means 12 for generating a single error detection code by using all the constituent elements of the above as generation elements, adding the single error detection code to the unit information, and inputting to the switch 11. And an error detection circuit 13 for detecting an error, to which the unit information added with the error detection code extracted from the switch 11 is input.

The unit information input to and output from the switch 11 is transmitted in a plurality of bits in parallel, and the same single error detection code is added to each of the plurality of bits. It may be transmitted.

FIG. 2 shows a block diagram of the principle of the invention according to claim 3. The present invention provides an additional bit addition in the error monitoring system of the switch 21 in which a plurality of fixed-length unit information consisting of a pair of transmission information and identification information is input in parallel, and routes are distributed with reference to each identification information. A means 22 and an error detecting means 23 are provided.

The additional bit adding means 22 is a switch 21.
For each transmission period of a plurality of unit information input in parallel, the additional bits are added to the plurality of unit information according to a predetermined rule.

The error detecting means 23 detects an error in the unit information to which the additional bit extracted from the switch 21 is added, based on the additional bit.

FIG. 3 is a block diagram showing the principle of the invention according to claims 6 and 7. According to the present invention, fixed-length unit information consisting of a pair of transmission information and identification information is sequentially input to an input port, and a switch 31 for distributing routes to an output port by referring to the identification information is output. In the error monitoring system, error detection code generation means 32 for generating an error detection code for each output port of the switch 31 for the unit information.
And an input means 33 and an error detection means 34.

Here, the input means 33 according to claim 6 transmits the error detection code together with the input port number assigned to the input port of the switch 31 to which the unit information of the generating element is input, in the idle transmission of the unit information. It is inserted in the period and input to the input port of the switch 31.

Further, the input means 33 according to a seventh aspect of the invention, instead of the idle transmission period of the unit information, periodically or aperiodically, the information including the error detection code and the input port number is used as the unit information. It is inserted in between and input to the input port of the switch 31.

Further, the error detecting means 34 includes a switch 31.
The unit information, the input port number, and the error detection code extracted from the output port are input, and an operation using the error detection code is performed for each input port number to obtain an error detection result of the unit information.

[0024]

In the invention of FIG. 1, the error detection code generating / adding means 12 generates an error detection code by using all the constituent elements of the unit information as generating elements and adds it to the unit information. Therefore, the unit information is the switch 11
When a plurality of bits are input in parallel, the same error detection code is added to each of the plurality of bits.

Therefore, the error detection circuit 13 can detect the presence / absence of an error only by whether or not the error detection code has the same value for each of a plurality of bits, and it is not necessary to perform the error detection calculation.

In the invention of FIG. 2, the additional bit adding means 22
With this, the additional bits are added according to a predetermined rule for each transmission period of a plurality of unit information input in parallel to the switch 21. Therefore, every time a plurality of unit information is taken out from the switch 21 in parallel, whether or not the values of the plurality of additional bits that are subsequently taken out in parallel are the same value, and whether or not the above-mentioned predetermined rule is satisfied. Thus, the presence or absence of an error can be detected, and the error detection calculation can be omitted.

In the invention of FIG. 3, the error detecting code generating means 32 is provided.
Generates an error detection code for the unit information corresponding to the output port of the switch 31. That is, the input unit information is transferred in the format as shown in FIG. 10, and the unit in which the input ports between adjacent empty transmission periods are output to the same i-th output port among the same unit information. Generate an error detection code for the information.

The input means 33 transmits this error detection code together with the input port number by inserting it between the transfer unit information in the idle transmission period or periodically or aperiodically. As a result, the error detecting means 34 can detect which input port the unit information has an error by performing an operation using the error detecting code for each input port number.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 is a block diagram of an embodiment of the present invention. This embodiment is an example applied to the ATM system, and a bit slice type switch 40 is used as an ATM switch.
The bit slice type switch 40 is provided on the input side of the space switches 41 to 44 so that the output timings to the same output port do not overlap with the space switches 41 to 44 containing two 4 × 4 space switches. Buffer, and a control circuit (not shown) that identifies the contents of the header and controls the switching of the space switches 41 to 44 accordingly. Here, it is assumed that a fixed-length 53-byte cell is transferred in parallel for 8 bits.

Further, parity generation / addition circuits 51 to 54
Is a circuit for generating and adding a parity bit as an error detection code for each of four parallel input cell groups, and a circuit for realizing the error detection code generation / addition means 12 or the error detection code generation means 32 and the input means 33. Is.

Further, the parity check circuits 61 to 64 are circuits for respectively performing a parity check on four parallel output cell groups from the ATM switch 40, and circuits for realizing the error detection circuit 13 and the error detection means 34. is there.

Next, to explain the operation of this embodiment,
The cell groups transferred in the format as shown in FIG. 10 are input to the parity generation / addition circuits 51, 52, 53 and 54 separately and simultaneously. The parity generation / addition circuits 51 to 54 add a parity bit generated based on an input cell to the input cell as described later and add the input cell and the parity bit to the ATM via an 8-bit parallel transmission path.
Input to the switch 40.

Here, the above-mentioned parity generation / addition circuit 5
In 1 to 54, among the 8-bit parallel outputs, the upper 2 bits are the space switch 41 and the next 2 bits are the space switch 42.
The next 2 bits are sent to the space switch 43 and the last 2 bits.
The bits are input to the space switch 44.

The switch 40 controls the switching of the space switches 41 to 44 based on the header of the input cell. The space switches 41 to 44 respectively select and output the above-mentioned four inputs of 2 bits to the four 2-bit output ports and input them to any of the parity check circuits 61 to 64.

The parity check circuit 61 receives 2-bit signals from the space switches 41, 42, 43 and 44, respectively. These are the upper 2 bits of the same cell and the next 2 bits.
Bit, the next 2 bits, and the lower 2 bits. Therefore, 8 bits of the same cell are input, and the switch 4
Monitor the transfer error at 0. Parity check circuit 6
Similarly, for 2, 63 and 64, an 8-bit cell divided into 2 bits is input and a parity operation is performed to
The transfer error in the TM switch 40 is monitored.

Next, the error monitoring method of the first embodiment of the present invention will be described. In the first embodiment, as shown in FIG. 5, the parity generation / addition circuits 51 to 54 each generate a 1-bit parity bit using the entire 53-byte effective information 101 as a generation element (either odd parity or even parity). Or apply).

Then, the 1-bit parity bit thus generated is parallel-developed into 8-bit data, which is shown in FIG.
It is added as an additional bit as indicated by 01. Therefore, all the 8 additional bits have the same value (the value of the 1-bit parity bit). This 53-byte effective information 1
54 consisting of 01 and 1-byte parity bit 201
A cell 301 is composed of bytes.

Similarly, the next 53 bytes of valid information 1
A cell 302 is composed of 54 bytes consisting of 02 and 1 byte (however, 8 bits of 1 bit of parity bit) of parity bit 202.

When cells are transferred in such a format, the parity check circuits 61 to 64 detect whether or not the additional bits such as 201 and 202 of the input 8-bit data have the same value. When the values are the same, it is determined that there is no error, and when the values are not the same, it is determined that there is an error.

Therefore, in this embodiment, the parity check circuits 61 to 64 do not need to perform the parity operation, and the parity check can be performed very easily. Further, since the parity bit can be generated by one calculation, it can be calculated more easily than the conventional horizontal parity and vertical parity.

Next, an error monitoring method according to the second embodiment of the present invention will be described. In the second embodiment, an additional bit adding circuit is provided in place of the parity generating / adding circuits 51 to 54, and an additional bit ("1" or "0") is provided according to a certain rule at each time counted in cell units. ) Is given.

That is, the effective information of the cell has a fixed length.
To the input port of the switch 40 as shown in FIG.
Transmission period t of each valid information input₁, T₂, T₃Is one
It is fixed. Therefore, the additional bit adding circuit is used for the cell transmission period.
Is counted and cell t₁, T ₂, T₃Add bit immediately after
Is given as shown by hatching in FIG.

As the method of adding the additional bits, a method of adding the same value to the cells of the input port of the switch 40 at the same time (that is, the time immediately after the end of the transmission of the cell valid information) and the input port of the switch 40 are used. There is a method of giving an independent value to each cell at the same time for each input port.

In any of the above-described methods (1) and (2), the additional bits are added according to a certain rule. As a certain rule, for example, (a) "1" and "0" are given to the police box. (B) Bits may be added according to a PN (Pseudo random noise) pattern.

Therefore, in this embodiment, an additional bit check circuit is provided on the output port side of the switch 40 instead of the parity check circuits 61 to 64 to check the additional bit. The valid information of the cells extracted from the output port of the switch 40 is also synchronized with the valid information of the cells input to the switch 40, and is also extracted at a constant cycle as indicated by t ₁ ', t ₂ ' and t ₃ 'in FIG. , Additional bits (shown with hatching in FIG. 6) are also taken out every cell transmission period.

Therefore, assuming that the additional bit is expanded in parallel to 8 bits, the additional bit check circuit determines that there is no error when the additional 8 bits have the same value, If even a part of does not match, it is determined that there is an error.

Therefore, in the present embodiment, like the first embodiment, the transfer error of the switch can be detected very easily without performing the parity check calculation. This is particularly suitable when applied to the bit slice type switch 40 in which cells are transmitted through different spatial switches 41 to 44 as shown in FIG.

Next, an error monitoring method according to the third embodiment of the present invention will be described. In the third embodiment, each of the parity generation / addition circuits 51 to 54 in FIG. 4 performs the following operation. As shown in FIG. 7, cells with valid information (valid cells) 71 to 73, 75, 76, 78 and cells without valid information (empty cells) 74, 77 are input in time series, and each cell Is output to the output port having the number shown in the lower side of FIG.

Here, # 1, # 2, # 3 and # 4 in FIG.
Is an output port number to be output to the parity check circuits 61, 62, 63 and 64 in the case of the bit slice type switch 40 of FIG. The outputs of the parity generation / addition circuits 51, 52, 53, and 54 are divided and input to the space switches 41 to 44 of the switch 40. However, for convenience, here, the input port to which the output of the parity generation / addition circuit 51 is input. Is set as the input port number # 1, and similarly, the input ports to which the outputs of the parity generation / addition circuits 52 to 54 are input are set to the input port numbers # 2 to # 4.

In this embodiment, the parity generation / addition circuit 5
1 to 54 are for performing a parity calculation (for example, the horizontal parity calculation described above) corresponding to the output port, and then inserting and adding the parity calculation result obtained thereby together with the input port number in an appropriate empty cell period. Is.

For example, assuming that a cell sequence as shown in FIG. 7 is input to the parity generation / addition circuit 51, the parity generation / addition circuit 51 is output to the same # 1 output port until just before the input of the empty cell 74. The parity calculation result obtained by calculating the parity of the input cell is inserted together with its own input port number (# 1) during the transmission period of the empty cell 74. Similarly in the next transmission period of the empty cell 77, the parity calculation result obtained by calculating the parity of the input cell output to the output port of # 2 is inserted together with the input port number (# 1).

On the other hand, the parity check circuits 61 to 64 judge from the header of the input cell whether or not the parity bit is transmitted, and when the parity bit is transmitted, the parity is associated with the input port. Calculate. That is, the result of the parity calculation for valid cells of the same input port number between adjacent empty cells of the same input port number and the parity calculation result loaded in the empty cell of the same input port number are compared. Check for any mistakes.

As a result, it is possible to determine from which input port the cell from which the cell is erroneous based on the result of the parity calculation, and the monitoring capability can be further improved as compared with the conventional case.

Next, an error monitoring method according to the fourth embodiment of the present invention will be described. In the fourth embodiment, as in the third embodiment, the parity generation / addition circuits 51 to 54 perform the parity calculation corresponding to the output ports, but unlike the third embodiment, the parity obtained thereby is obtained. Bits and input port numbers are inserted between valid cells periodically or aperiodically.

For example, assume that cells are input to the parity generation / addition circuit 51 as schematically shown in FIG. In the figure (A), a ₁ and a ₂ are empty cells output to the output port of the output port number # 4, b _{1 to} b ₆ are valid cells, and the valid cells are output from # 1 to # 4. Indicates the output port number to be output.

In this case, the parity generation / addition circuit 51 calculates the parity for the cells b ₂ and b ₄ having the output port number # 4 in the cells from the previously output empty cell a _{1 to the} next empty cell a _2. The parity bit thus obtained is generated together with the input port number # 1 to generate a monitoring cell as shown in FIG. 9, and the monitoring cell is inserted between valid cells periodically or aperiodically.

In FIG. 9, the monitoring cell 90 is a header 9
1, an input port number 92, a parity bit 93 and the like. The header 91 is identification information for identifying that the cell 90 is for monitoring. The input port number is a number previously assigned to the input port of the switch 40, and is a number unique to each of the parity generation / addition circuits 51 to 54.

The parity bit 93 is a horizontal parity or a parity calculation result obtained by performing a parity calculation using the entire effective cells between empty cells output to the same output port as a generation element.

As a result, the cells input from the # 4 output port of the switch 40 to the parity check circuit 64 are combined in time series as schematically shown in FIG. 8 (B). In FIG. 8B, a ₁ and a ₂ are empty cells, b ₂ and
b ₄ is a valid cell, all of which are cells transferred from the input port of input port number # 1 to the output port of # 4 shown in FIG. 8A, and c ₁ , c ₂ and c ₃ are It is a valid cell transferred from an input port other than the input port number # 1 to the output port of # 4, and d ₁ is the above-mentioned monitoring cell.

[0060] Parity check circuit 64 has the same input port and the input port number # 1 of the monitor cell d _1, performs a parity calculation of the monitoring cell d ₁ previous valid cell, the calculation result with the monitoring cell The parity bit (93 in FIG. 9) in d ₁ is compared and collated to determine whether or not there is an error in the switch.

Therefore, this embodiment is similar to the third embodiment,
Since it is possible to monitor the error of the switch corresponding to the input port, the monitoring capability can be improved as compared with the conventional case.

The present invention is not limited to the above embodiments, and is not limited to the parity bit, for example, the CRC.
(Cyclic Redundancy Check Code)
Other error detection codes, such as, may be used. Also, ATM
The present invention can be applied not only to the system but also to the packet switching system.

[0063]

As described above, according to the first to third aspects of the present invention, the presence or absence of an error can be detected only by whether or not the error detection code or the additional bit has the same value, and the error detection calculation is unnecessary. Therefore, the error monitoring of the switch can be performed more easily than before. Further, according to the invention described in claims 4 to 7, since it is possible to monitor the error corresponding to the input port of the switch, it is possible to carry out the error monitoring of the switch with higher reliability than the conventional one.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the invention according to claim 1.

FIG. 2 is a principle block diagram of the invention according to claim 3;

3 is a principle block diagram of the invention according to claims 6 and 7. FIG.

FIG. 4 is a configuration diagram of an embodiment of the present invention.

FIG. 5 is a diagram illustrating a transfer format according to the first embodiment of this invention.

FIG. 6 is a diagram illustrating a transfer format according to a second embodiment of this invention.

FIG. 7 is an explanatory diagram of a third embodiment of the present invention.

FIG. 8 is a diagram showing a cell transfer format on an input side and an output side of a switch according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a structure of a cell according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing an example of ATM cell transfer.

FIG. 11 is an explanatory diagram of ATM-based method road distribution.

FIG. 12 is a configuration diagram of an example of a conventional method.

FIG. 13 is an explanatory diagram of parity calculation by a conventional method.

FIG. 14 is a diagram showing an example of cell transfer of the conventional system of FIG.

[Explanation of symbols]

 11, 21, 31 switch 12 error detection code generation / addition circuit 13 error detection circuit 22 additional bit addition means 23, 24 error detection means 32 error detection code generation means 33 input means 40 bit slice type switch 41-44 spatial switch 51- 54 parity generation / addition circuit 61-64 parity check circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H04Q 3/52 101 Z 9076-5K 11/04 9076-5K H04Q 11/04 L (72) Inventor Ryuichi Kondo 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited (72) Inventor Takaaki Wakisaka, Kanagawa Prefecture Nakazaki-ku, Nakahara-ku, Kanagawa Prefecture 1015 Kamiodanaka, Fujitsu Limited (72) Inventor Kenji Akutsu 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Hiromi Ueda 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo No. Japan Telegraph and Telephone Corporation

Claims (7)

[Claims] 1. An error monitoring system of a switch (11) for allocating a route to fixed-length unit information consisting of a pair of transmission information and identification information, by referring to the identification information. Error detection for generating a single error detection code using all the constituent elements of the unit information as generation elements, adding the single error detection code to the unit information, and inputting to the switch (11) Code generation / addition means (1
2) and an error detection circuit (13) for inputting unit information to which the error detection code added, which is extracted from the switch (11), is input, and an error detection circuit for a switch, which is characterized in that .. 2. The unit information input to and output from the switch (11) is transmitted in parallel in a plurality of bits, and the single error detection code is the same for each of the plurality of bits. 2. The error monitoring system for a switch according to claim 1, wherein the error monitoring system is added and transmitted. 3. An error monitoring system of a switch (21), wherein a plurality of fixed-length unit information consisting of a pair of transmission information and identification information is input in parallel, and a route is distributed by referring to each identification information. Additional bit adding means (22) for adding an additional bit to the plurality of unit information in accordance with a predetermined rule for each transmission period of the plurality of unit information input in parallel to the switch (21), and the switch (21 Error detection means (23) for detecting an error on the basis of the additional bit with respect to the unit information to which the additional bit is extracted from (1). 4. The additional bit assigning means (22) assigns the additional bit of the same value to each of the plurality of unit information in the same transmission period. Switch error monitoring method. 5. The additional bit assigning means (22) assigns the additional bits independently of each other to the plurality of unit information in the same transmission period. Switch error monitoring method. 6. A switch for sequentially inputting fixed-length unit information consisting of a pair of transmission information and identification information to an input port, allocating a route with reference to the identification information, and outputting to an output port ( 31) In the error monitoring method of 31), an error detection code generating means (32) for generating an error detection code for each output port of the switch (31) with respect to the unit information, and the error detection code is a unit of a generation element thereof. An input means (33) for inserting the information into the input port of the switch (31) and inputting it into the input port of the switch (31) together with the input port number assigned to the input port of the switch (31); The unit information, the input port number, and the error detection code extracted from the output port of the switch (31) are input, and the error detection code is classified by the input port number. And an error detecting means (34) for obtaining an error detection result of the unit information by performing an operation using a signal. 7. The input means (33) periodically or aperiodically replaces the information including the error detection code and the input port number between the unit information instead of the idle transmission period of the unit information. 7. The switch error monitoring system according to claim 6, wherein the error monitoring system is inserted and input to an input port of the switch (31).