JPH05235895A - Spread spectrum signal receiver - Google Patents

Abstract

PURPOSE:To restore the receiver quickly to a normal reception state when a reception wave is tentatively interrupted and then restored in the receiver which receives a spread spectrum signal resulting from multiplying a pseudo random code with an original signal to be sent. CONSTITUTION:The receiver is devised such that a variable oscillator 6 is driven in phase locking with a spread spectrum signal received by a delay lock loop circuit and its output drives a PN code generator 7, and an interrupted reception radio wave is detected and a sample-and-hold circuit 13 is used to hold an oscillating phase of the variable oscillator 6 to a phase at the detection of the interruption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication receiver, and more particularly, when the received radio wave is temporarily interrupted and restored again due to movement of the receiver in a receiving state. It is configured so that a normal reception state is quickly obtained.

[0002]

2. Description of the Related Art Among spread spectrum (SS) communication techniques, a so-called direct spread system broadens a signal by multiplying an original signal by a PN (pseudo random) signal having a wider bandwidth. In this technology, the original signal is extracted by spreading the signal within the spectrum band and transmitting it, and canceling the PN signal component on the receiving side.

In order to cancel the PN signal component, the same PN signal as that multiplied by the transmitting side may be generated in the same phase and multiplied by the received signal. If the PN codes on the transmitting side and the receiving side are in phase, all the PN signals are canceled out, and the signal power spread in the wide spectrum band is despread in the band of the original signal, but the phase is If it does not match at all, the signal power remains spread over a wide spectrum band, and little power appears in the band of the original signal.

When the PN code generated on the receiving side is multiplied by the received signal by the multiplier and the root mean square voltage of the output filtered by the filter of the same band as the original signal is called the correlation output, the phase difference is the PN signal. The correlation output when it is within 1 bit has a property of being inversely proportional to the shift amount. A DLL (Delay Lock Loop) circuit controls the phase of the PN code by utilizing this property, and is configured as shown in FIG.

The PN code 20 is output from the PN code generator 7, and is delayed by the delay unit 8 to form a signal 21, and the signal 21 is further delayed by the delay unit 9 to obtain a signal 22, and the signal 21 is used as a reference. The signal 20 is called a phase lead signal and the signal 22 is called a phase delay signal. The delay amount is set within 1 bit of the PN signal. In the multiplier 1 and the multiplier 2, the phase lead signal 20 and the phase lag signal 22 and the reception PN are received, respectively.
Multiply with signal 23. When this is passed through LPFs (low pass filters) 3 and 4, respectively, correlation outputs 26 and 27 corresponding to the phase difference between the reception PN signal 23 and the phase advance signal 20 and the phase delay signal 22 are obtained. The difference between the correlation output 26 and the correlation output 27 in the subtractor 5 is taken as the phase difference detection signal 28, and the VCO (voltage controlled oscillator) 6
A feedback loop is formed by controlling the clock signal 29 of the PN code generator 7 which is generated so that the phase difference between the received PN signal 23 and the generated PN signal 21 becomes zero.

[0006]

Problems to be Solved by the Invention In SS communication, a PN signal having a long period is used. As described above, the correlation output inversely proportional to the phase difference is obtained because the phase difference is one clock of the PN code. Since it is only within the time, in other cases,
The DLL is in an uncontrolled state without feedback according to the phase difference.
If the free-running frequency of the VCO in this state is close to the clock frequency of the PN code generator on the transmission side, the phase of the PN code slowly changes due to the clock frequency difference, and at the time when the phases approach each other. Feedback is applied to synchronize the phase of the PN code. This operation until the phases are synchronized is called a synchronization capturing operation, and the operation thereafter that keeps the phase synchronization is called a synchronization holding operation.

When the electric wave is temporarily cut off due to the movement of the transmitter or the receiver, D during the synchronization holding operation is performed.
LL returns to the uncontrolled state, the synchronous capture operation starts, and PN
The phase of the code shifts from the phase of the PN code on the transmission side,
If the phase shifts by 2 bits or more before the reception status is restored, the PN code synchronized with the transmission side cannot be obtained until the phase of the PN code changes by less than one cycle, so normal reception is resumed. Can not.

It is an object of the present invention to prevent loss of synchronization due to jamming, thereby minimizing the interruption time of normal reception.

[0009]

In order to achieve this object, the spread spectrum signal receiving apparatus of the present invention has a means for receiving a spread spectrum signal obtained by multiplying an original signal by a predetermined pseudo random code, and an input clock. A PN code generator for generating a first output equal to the pseudo-random code to the signal, a first delay output and a second delay output sequentially delayed by a predetermined time from the first output thereof. And means for creating the spread spectrum signal and PN
Means for producing a first phase correlation signal from the product of the output of the code generator and a second phase correlation signal from the product of the spread spectrum signal and the second delay output; The first synchronization detection signal from the phase correlation signal difference of
A means for creating a second synchronization detection signal from the sum of the first and second phase correlation signals, and an output signal whose oscillation frequency changes according to an input control signal, and the output is used as the clock signal. A variable oscillator applied to the PN code generator, a comparison means for detecting that the second synchronization detection signal has dropped below a predetermined voltage value, and outputting a detection signal, and usually the first A synchronization detection signal is input to the variable oscillator as the input control signal, the generation period of the detection signal holds the value of the first synchronization detection signal at the time of generation, and the held value is the input control signal. And a holding circuit for inputting to the variable oscillator, and the original signal is demodulated from the product of the received spread spectrum signal and the first delay output.

[0010]

During the synchronous holding operation, the control voltage of the VCO is maintained so that the clock having the same speed as the clock of the PN code generator on the transmitting side is generated. Therefore, when the interruption of the signal is detected from the synchronization detection signal, the same clock speed as that during the synchronization holding operation is maintained by holding the control voltage of the VCO during the synchronization holding operation as it is,
The generation of the PN code having the same phase as the PN code generator on the transmitting side can be continued.

[0011]

Embodiments of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram of a synchronous capture / hold circuit that holds (holds) the control voltage of the VCO when the synchronous detection is below a certain value.

The PN code 20 is output from the PN code generator 7. This signal is delayed by the delay device 8 to obtain a signal 21,
The signal 21 further delayed by the delay device 9 is the signal 2
2. The delay amount is 0.5 bits of the PN signal. When the PN signal 21 is used as a reference, 20 is a phase advance signal having a phase advance of 0.5 bit, and 22 is a phase delay signal having a phase delay of 0.5 bit. The phase lead signal 20, the phase delay signal 22, and the reception PN signal 23 are respectively applied to the multiplier 1 and the multiplier 2.
Multiply with. Multiplier output 24 and multiplier output 25
Are passed through LPFs (low-pass filters) 3 and 4, respectively, a correlation output 26 and a correlation output 27 are obtained according to the phase difference between the reception PN signal 23, the phase advance signal 20, and the phase delay signal 22. ..

FIGS. 2A and 2B show the relationship between the phase difference between the PN signal 21 and the input PN signal 23 and the correlation outputs 26 and 27. When the difference between the correlation output 26 and the correlation output 27 in the subtracter 5 is taken as the phase difference detection signal 28, the phase difference detection signal 28 is reversed in the region where the phase difference is around zero as shown in FIG. Since the characteristics are proportional, the phase difference can be controlled to be zero by giving the phase difference detection signal 28 to the VCO 6 in this region. Phase difference detection signal 2
8 enters the analog input of the sample hold circuit 13.
On the other hand, assuming that the sum of the correlation output 26 and the correlation output 27 in the adder 10 is the synchronization detection signal 30, the synchronization detection signal is a constant voltage source 11 having a trapezoidal characteristic as shown in FIG. A comparator output signal 31 obtained by comparing the synchronization detection signal with the comparator 12 is obtained, and its characteristic is as shown in FIG. The signal 31 enters the control input of the sample and hold circuit 13, and the sample and hold circuit 13 gives the phase difference detection signal 28 to the VCO 6 as the control voltage 32 as it is while the signal 31 is HI level, and while the signal 31 is LO level, The control voltage 32 at that time is held so as not to change.

Generally, in the initial state, the DLL is out of code phase synchronization, and a constant voltage value determined by the leak characteristic of the sample hold circuit 13 determines the oscillation frequency of the VCO 6.

Considering the case where the phase difference approaches zero from the negative side, the locus drawn by the phase difference, the phase difference detection signal 28 and the control voltage 32 of the VCO 6 is shown in FIG. From the initial state, until the phase difference becomes small and the sync detection signal 30 exceeds the control voltage 32, the output of the comparator 12 becomes LO.
Since it is at the level, the sample and hold circuit 13 maintains the voltage in the initial state, and the phase difference decreases at a constant speed. When the synchronization detection signal 30 exceeds the threshold value of the constant voltage source 11, the output of the comparator 12 becomes HI level, and the sample hold circuit 13 changes to sample operation. While the output of the comparator 12 is HI, the phase difference detection signal 28 becomes the VCO control voltage 32 as it is, so that the changing speed of the phase difference changes according to the phase difference detection signal 28. If the oscillation frequency of the VCO 6 is the same as the clock frequency of the PN code generator on the transmission side when the control voltage has a certain value, the phase difference is −
Within the range of 0.5 to 0.5 bits, the change of the phase difference stops when the control voltage 29 reaches that value, and thereafter, the phase-synchronized PN code is generated by the clock of the same frequency. It becomes a state. This state is the phase holding state.

Next, considering the operation from the interruption to the resumption of the received signal in the synchronous holding state, the locus drawn by the phase difference, the phase difference detection signal 28 and the VCO control voltage 32 is shown in FIG.
Shown in. When the received signal is interrupted, the correlation outputs 26 and 27 become small at the same time, and the sum of the synchronous detection signal 30 also becomes small. The sample hold circuit 13 starts the hold operation. The phase difference detection signal 28 also changes at the same time as the synchronization detection signal 30, but the amount of change until being held is constant voltage source 11 near the upper side of the trapezoidal characteristic of the synchronization detection signal as shown in FIG. It can be made small enough by setting the value of. During the signal interruption, P at a speed according to the control voltage 32 held by the sample and hold circuit 13.
Although the N code 21 is generated, the phase difference between the N code 21 and the PN code on the transmission side increases at a very slow speed if the change in the control voltage 32 caused by the signal interruption is sufficiently small.

When the received signal is restored when the phase difference is within 0.5 clock minutes. As shown in FIG. 2D, the synchronization detection signal takes a constant value within this section, so that it immediately exceeds the threshold value determined by the constant voltage source 11, and the comparator 12 operates to cause the sample hold circuit 13 to perform the sampling operation. enter. The phase difference detection signal 28 returns to a value according to the phase difference shown in FIG. 2C, the feedback operation is restored, and the phase difference converges to the previous value.

On the other hand, according to the present invention, if the sample hold circuit is not provided, the phase difference detection signal 28 at the time of interruption of the reception signal generally has a value greatly different from the synchronization holding state, so that the phase difference with the transmission side is different. Rapidly increases, exceeding 0.5 clocks in a short time, and no feedback is applied even if the received signal is restored.

In this embodiment, when the reception signal is interrupted, the time until the phase difference with the transmission side exceeds 0.5 clocks becomes long, and if the reception signal is restored within this time, the synchronization holding state is achieved in a short time. There is an advantage of putting in. However, when the reception signal is restored after the phase difference from the transmitting side exceeds 0.5 clocks, the synchronization detection signal does not exceed the threshold value as shown in FIG. Since the sample operation is not released, the change speed of the phase difference remains very slow, and there is a problem that the phase changes for one cycle of the PN code and the time until the synchronization is made again becomes long. The leak characteristic of the sample and hold circuit is gradually VCO.
Since the control voltage 32 is changed to act in the direction of accelerating the change of the phase, this drawback can be improved, but not enough.

FIG. 5 is a block diagram of the second embodiment.
The hold operation is canceled after a fixed time after the reception signal is interrupted, and the synchronization capture operation similar to the normal DLL is performed, so that the time until resynchronization occurs in the first embodiment is long. Is improved. The difference from the first embodiment is that a timer circuit 14 having a function of limiting the length of the hold time is provided between the comparator 12 and the sample hold circuit 13.

FIG. 6 shows an internal circuit of the timer circuit 14. The timer circuit 14 clears to zero when the comparator output 31 is HI, and counts up in synchronization with the clock input 34 when the comparator output 31 is LO. However, the counter 16 having the function of setting the carry output 35 to HI when it reaches a constant value, the oscillator 15 for driving it, and the comparator output 31
Is HI, the Q output 36 is changed to LO, the carry 35 from the counter changes the Q output 36 to HI when the carry 35 is HI, and the Q output 36 is not changed otherwise.
When the comparator output 31 is LO and the RS latch output 36 is LO, the timer circuit output 33 is set to LO.
It comprises an R circuit 18.

Since the comparator output 31 is HI during the synchronous holding operation, the counter 16 and the RS latch 17 are reset,
HI is output from the OR circuit 18, and the sample hold circuit 13 performs a sampling operation. When the reception signal is interrupted and the comparator output 31 becomes LO, the counter 16 is released from reset and starts counting up in synchronization with the oscillator 15. The RS latch 17 is also released from the reset, but the RS latch Q output 36 remains until the carry signal 35 becomes HI.
Keeps LO. Since the input signals 31 and 36 of the OR circuit 18 are both LO, the output 33 of the timer circuit becomes LO,
The sample hold circuit 13 performs a hold operation to
Holds the code generation rate. When the reception signal is interrupted and a certain time has passed, the value of the counter 16 becomes a certain value and the carry output 35 becomes HI, the Q output 36 of the RS latch 17 becomes HI, and the timer circuit 1 operates by the operation of the OR circuit 18.
The output of 4 returns to HI, and the hold operation of the sample hold circuit 13 is released. Since the synchronous capture operation from this point is the same as the normal DLL circuit without the sample hold circuit 13, if the phase difference with the transmitting side exceeds 0.5 clocks when the received signal is interrupted, it is restarted from the interrupted received signal. The extra time required for synchronization is only the duration of the hold operation. During this time, the phase difference with the transmitting side is 0.
By setting the time required to shift by 5 clocks,
The extra resynchronization time due to the addition of the sample hold circuit can be minimized.

If reception resumes before the hold operation is terminated by the action of the counter circuit and the comparator output 31 returns to HI, the counter 16 and the RS latch 17 are immediately reset and the output 33 of the timer circuit HI. Then, the hold operation can be canceled and the synchronous capture operation can be started, so that the phase difference with the transmitting side is 0.
The time required to exceed 5 clocks becomes long, and the advantage of entering the synchronization holding state in a short time if the received signal recovers within this time is not diminished by the addition of the timer circuit.

[0024]

During the synchronization holding operation, the control voltage of the VCO is maintained so that the clock having the same speed as the clock of the PN code generator on the transmission side is generated, so that the signal is interrupted from the synchronization detection signal. If detected, the VCO control voltage during the synchronous holding operation is held as it is, so that the same clock speed as that during the synchronous holding operation is maintained, and the PN code of the same phase as that of the PN code generator on the transmitting side is maintained. Can continue to occur, due to the movement of the receiver in the receiving state,
When the received radio wave is temporarily interrupted and restored again,
Can move to a normal reception state more quickly

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of a spread spectrum signal receiving apparatus according to the present invention.

FIG. 2 is a waveform diagram showing the relationship between the phase difference detection signal and the phase of the correlation detection signal in the embodiment.

FIG. 3 is a time waveform diagram showing a synchronous capture operation according to the present invention.

FIG. 4 is a time waveform diagram showing a synchronization holding operation according to the present invention.

FIG. 5 is a block diagram of a second embodiment of the spread spectrum signal receiving apparatus of the present invention.

FIG. 6 is a circuit diagram of a timer circuit in the embodiment.

FIG. 7 is a block diagram of a conventional spread spectrum signal receiving device.

[Explanation of symbols]

 1 multiplier 2 multiplier 3 LPF (low-pass filter) 4 LPF (low-pass filter) 5 subtractor 6 VCO (voltage controlled oscillator) 7 PN code generator 8 delay device 9 delay device 10 adder 11 constant voltage source 12 comparator 13 sample and hold circuit 14 timer circuit

Claims (2)

[Claims] 1. A means for receiving a spread spectrum signal obtained by multiplying an original signal by a predetermined pseudo random code, and a PN code generator for generating a first output equal to the pseudo random code in synchronization with an input clock signal. And means for creating a first delay output and a second delay output that are sequentially delayed from the first output by a predetermined time, and a product of the spread spectrum signal and the output of the PN code generator. A first phase correlation signal, a means for creating a second phase correlation signal from the product of the spread spectrum signal and a second delay output, and a first phase correlation signal from the difference between the first and second phase correlation signals. The synchronization detection signal of, means for creating a second synchronization detection signal from the sum of the first and second phase correlation signals, respectively, and outputs an output signal whose oscillation frequency changes according to the input control signal, Output before A variable oscillator applied to the PN code generator as a clock signal, a comparison means for detecting that the second synchronization detection signal has dropped below a predetermined voltage value, and outputting a detection signal, and usually the above-mentioned A first synchronization detection signal is input to the variable oscillator as the input control signal, the generation period of the detection signal holds the value of the first synchronization detection signal at the time of generation, and the held value is A spread spectrum signal having a holding circuit for inputting to the variable oscillator as an input control signal, wherein the original signal is demodulated from a product of the received spread spectrum signal and the first delay output. Receiver. 2. A means for receiving a spread spectrum signal obtained by multiplying an original signal by a predetermined pseudo random code, and a PN code generator for generating a first output equal to the pseudo random code in synchronization with an input clock signal. And means for creating a first delay output and a second delay output that are sequentially delayed from the first output by a predetermined time, and a product of the spread spectrum signal and the output of the PN code generator. A first phase correlation signal, a means for creating a second phase correlation signal from the product of the spread spectrum signal and a second delay output, and a first phase correlation signal from the difference between the first and second phase correlation signals. The synchronization detection signal of, means for creating a second synchronization detection signal from the sum of the first and second phase correlation signals, respectively, and outputs an output signal whose oscillation frequency changes according to the input control signal, Output before A variable oscillator applied to the PN code generator as a clock signal, a comparison means for detecting that the second synchronization detection signal has dropped below a predetermined voltage value, and outputting a detection signal, and usually the above-mentioned A first synchronization detection signal is input to the variable oscillator as the input control signal, and a predetermined period after the generation of the detection signal holds the value of the first synchronization detection signal at the time of generation, A holding circuit for inputting the held value to the variable oscillator as the input control signal, and demodulating the original signal from a product of the received spread spectrum signal and the first delay output. Spread spectrum signal receiver.