JPH05235360A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH05235360A JPH05235360A JP3523692A JP3523692A JPH05235360A JP H05235360 A JPH05235360 A JP H05235360A JP 3523692 A JP3523692 A JP 3523692A JP 3523692 A JP3523692 A JP 3523692A JP H05235360 A JPH05235360 A JP H05235360A
- Authority
- JP
- Japan
- Prior art keywords
- data line
- electrode layer
- stacked electrode
- layer
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は液晶表示装置に関し、特
に、その表示品質の向上技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique for improving its display quality.
【０００２】[0002]
【従来の技術】液晶表示装置においては、画素信号を供
給するデ−タ線および走査信号を伝達するゲ−ト線が格
子状に配置されており各画素領域が区画形成された一方
側の透明絶縁基板と共通電極が形成された他方側の透明
絶縁基板との間に液晶が封入されており、共通電極と各
画素領域の画素電極との間に印加される電位を制御し
て、画素領域毎の液晶の配向状態を変化させるようにな
っている。このため、各画素領域から構成されたマトリ
クスアレイの一般的な構造は、垂直方向のデ−タ線と、
水平方向のゲ−ト線とによって区画形成された画素領域
にデ−タ線が導通接続するソ−スおよびゲ−ト線が導通
接続するゲ−トを有するＴＦＴが構成されており、その
ドレインには、それらの表面側に形成されたシリコン酸
化膜からなる層間絶縁膜の接続孔を介して画素電極が導
通接続している。2. Description of the Related Art In a liquid crystal display device, a data line for supplying a pixel signal and a gate line for transmitting a scanning signal are arranged in a grid pattern so that each pixel region is divided and formed on one transparent side. Liquid crystal is enclosed between the insulating substrate and the transparent insulating substrate on the other side on which the common electrode is formed, and the electric potential applied between the common electrode and the pixel electrode of each pixel region is controlled to control the pixel region. The alignment state of the liquid crystal is changed every time. Therefore, the general structure of the matrix array composed of the respective pixel regions is such that vertical data lines and
A TFT having a source to which a data line is conductively connected and a gate to which a gate line is conductively connected is constructed in a pixel region defined by a horizontal gate line and its drain. The pixel electrodes are electrically connected to each other via the connection holes of the interlayer insulating film made of a silicon oxide film formed on the surface side thereof.
【０００３】従来の液晶表示装置においては、デ−タ線
も画素電極と同一の層間絶縁膜上に形成されて、その接
続孔を介してソ−スに導通接続しているため、デ−タ線
と画素電極とデ−タ線とが短絡しやすい構造である。
（図２に従来の構造であるデ−タ線と画素電極が同一の
層間絶縁膜上に形成されている場合の構造断面図を示
す）従って、それらを絶縁分離しておくためには、画素
電極の端部とデ−タ線との間に所定の間隔を確保する必
要があり、その間隔に相当して、画素電極の形成領域が
狭くなり、開口率が低減するという問題がある。この問
題を解決する方法として、デ−タ線と画素電極とを異な
る絶縁膜上に形成すれば良い。これは、下層側層間絶縁
膜の第１の接続孔を介して導通接続するデ−タ線と、下
層側層間絶縁膜の第２の接続孔を介して導通接続する積
み上げ電極層とを同一材料で形成し、この積み上げ電極
層に上層層間絶縁膜の接続孔を介して端部がデ−タ線の
上方に位置する画素電極が導通接続する構造である。
（図３に画素電極とデ−タ線とを別層に形成した場合の
構造断面図を示す。）従って、デ−タ線と画素電極とは
互いに別層に形成されているため短絡する危険性がない
ので、デ−タ線の上方位置にまで画素電極の端部を配置
することができるため、開口率が増加し、表示品質が向
上する。In the conventional liquid crystal display device, since the data line is also formed on the same interlayer insulating film as the pixel electrode and is electrically connected to the source through the connection hole, the data line is formed. The line, the pixel electrode, and the data line are easily short-circuited.
(FIG. 2 is a structural cross-sectional view of a conventional structure in which a data line and a pixel electrode are formed on the same interlayer insulating film.) Therefore, in order to keep them isolated, It is necessary to secure a predetermined interval between the end portion of the electrode and the data line, and there is a problem that the area where the pixel electrode is formed becomes narrower and the aperture ratio decreases corresponding to the interval. As a method of solving this problem, the data line and the pixel electrode may be formed on different insulating films. This is because the same material is used for the data line which is conductively connected through the first connecting hole of the lower layer side interlayer insulating film and the stacked electrode layer which is conductively connected through the second connecting hole of the lower layer side interlayer insulating film. The pixel electrode whose end portion is located above the data line is electrically connected to the stacked electrode layer through the connection hole of the upper interlayer insulating film.
(FIG. 3 is a structural cross-sectional view when the pixel electrode and the data line are formed in different layers.) Therefore, since the data line and the pixel electrode are formed in different layers, there is a risk of short circuit. Since the edge portion of the pixel electrode can be disposed above the data line, the aperture ratio is increased and the display quality is improved.
【０００４】[0004]
【発明が解決しようとする課題】しかし、デ−タ線およ
び積み上げ電極層に低抵抗のＡｌを使用すると、画素電
極のＩＴＯ膜との接続抵抗が高く、不安定なために表示
品質低下の原因となる。また、画素電極のＩＴＯ膜をウ
ェットエッチングによりパタ−ニングする場合、塩酸系
の溶液を用いるため、画素電極の端部がデ−タ線の上方
位置に配置されているこの構造においては、上層側層間
絶縁膜の欠陥（ピンホ−ル）からエッチング液がしみこ
みデ−タ線の断線を引き起こし、歩留り低下の原因にも
なる。However, when Al having a low resistance is used for the data line and the stacked electrode layer, the connection resistance between the pixel electrode and the ITO film is high and the display quality is deteriorated because of instability. Becomes Further, when the ITO film of the pixel electrode is patterned by wet etching, since a hydrochloric acid-based solution is used, the end portion of the pixel electrode is arranged above the data line. The etchant penetrates from defects (pinholes) in the interlayer insulating film, causing disconnection of the data line, which also causes a decrease in yield.
【０００５】従って、本発明の課題は、前述の画素電極
と積み上げ電極層の接続抵抗の低減と、ＩＴＯ膜のエッ
チング液によるデ−タ線の断線防止が可能な構造とする
ことにより、表示品質向上可能な液晶表示装置を実現す
ることにある。Therefore, an object of the present invention is to provide a display quality by reducing the connection resistance between the pixel electrode and the stacked electrode layer and preventing the disconnection of the data line by the etching solution of the ITO film. It is to realize an improved liquid crystal display device.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、本発明の液晶表示装置において講じた手段は、透明
な絶縁基板の表面側に形成されたマトリクスアレイが、
薄膜トランジスタのソ−スに下層側層間絶縁膜の第１の
接続孔を介して導通接続する第１のデ−タ線およびこの
第１のデ−タ線表面に導通接続して多重配線構造を構成
する第２のデ−タ線と、前記薄膜トランジスタのドレイ
ンに前記下層側層間絶縁膜の第２の接続孔を介して導通
接続しており、導電性のある第１の積み上げ電極層及び
この第１の積み上げ電極層表面に導通接続して多重配線
構造を構成する第２の積み上げ電極層と、この積み上げ
電極層に上層側層間絶縁膜の接続孔を介して導通接続し
ており、端部が前記デ−タ線の上方に位置する画素電極
と、を有することである。Means for Solving the Problems In order to solve the above problems, the means taken in a liquid crystal display device of the present invention is that a matrix array formed on the surface side of a transparent insulating substrate is
A first data line which is conductively connected to the source of the thin film transistor through the first connection hole of the lower interlayer insulating film and a conductive connection to the surface of the first data line to form a multiple wiring structure. To the drain of the thin film transistor through the second connection hole of the lower interlayer insulating film, and has a conductive first stacked electrode layer and the first stacked electrode layer. And a second stacked electrode layer which is conductively connected to the surface of the stacked electrode layer to form a multi-wiring structure, and is conductively connected to this stacked electrode layer through a connection hole of an upper layer side interlayer insulating film, and the end is And a pixel electrode located above the data line.
【０００７】[0007]
【作用】本発明の液晶表示装置において、前記第１のデ
−タ線及び第１の積み上げ電極層は低抵抗で、ソ−ス・
ドレインとオ−ミックコンタクト可能なアルミニウムの
ような材料を用いた上に前記第２のデ−タ線と前記第２
の積み上げ電極層は、画素電極のＩＴＯとの接続抵抗が
良好でかつＩＴＯのエッチング液に溶解されない材料を
用いていることによって、画素電極ＩＴＯと積み上げ電
極層との接続抵抗は低減され良好な表示品質を得ること
ができ、またデ−タ線もＩＴＯのエッチング液から保護
されるためデ−タ線の断線を防止することが可能であ
る。In the liquid crystal display device of the present invention, the first data line and the first stacked electrode layer have a low resistance, and
The second data line and the second data line are formed by using a material such as aluminum capable of making ohmic contact with the drain.
The stacked electrode layer of is made of a material that has a good connection resistance with the ITO of the pixel electrode and is not dissolved in the etching liquid of the ITO, so that the connection resistance between the pixel electrode ITO and the stacked electrode layer is reduced and a good display is obtained. It is possible to obtain quality, and since the data line is also protected from the ITO etching solution, it is possible to prevent disconnection of the data line.
【０００８】[0008]
【実施例】次に本発明の一実施例について添付図面を参
照して説明する。図１は本発明の実施例の液晶表示装置
における画素領域の構造断面図を示したものである。An embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a structural sectional view of a pixel region in a liquid crystal display device according to an embodiment of the present invention.
【０００９】この画素領域には、第１のデ−タ線１３お
よび第２のデ−タ線１４が導通接続するソ−ス２、ゲ−
ト線が導通接続するゲ−ト７、および画素電極１８が第
１の積み上げ電極層１５および第２の積み上げ電極層１
６を介して導通接続するドレイン３によって、ＴＦＴ８
が形成されている。このＴＦＴの断面構造は、液晶表示
装置全体を支持する絶縁透明基板１の表面側に多結晶シ
リコン層４が形成されており、この多結晶シリコンに
は、真性の多結晶シリコン領域であるチャネル領域５を
除いて、ｎ型の不純物としてリンが導入されて（ｐ型を
形成する場合はボロン）、ソ−ス２およびドレイン３が
形成されている。ここでリンの導入は、多結晶シリコン
層４の表面側に形成されたゲ−ト酸化膜６上のゲ−ト７
をマスクとするイオン注入を利用することにより、ソ−
ス２およびドレイン３がセルフアラインとなるように行
われる。このＴＦＴ８の表面側には、シリコン酸化膜か
らなる第１の層間絶縁膜９が堆積されており、それには
第１の接続孔１１と第２の接続孔１２とが開口されてい
る。そのうち第１の接続孔を介して、アルミニウム層か
らなる第１のデ−タ線１３がソ−ス２に導通接続されて
いる。その第１のデ−タ線１３上に多層配線構造として
ＭｏＳｉ2層を堆積し、デ−タ線１３と同様にパタ−ニン
グあるいは被覆するようにパタ−ニングし、第２のデ−
タ線１４を形成する。一方、第２の接続孔を介して、第
１のデ−タ線１３と同一材料のアルミニウム層からなる
第１の積み上げ電極層１５がドレイン３に導通接続して
いる。更にその第１の積み上げ電極層１５上に多層配線
構造として、第２のデ−タ線１４と同一材料を用いて堆
積し、第１の積み上げ電極層１５と同様にパタ−ニング
あるいは被覆するようにパタ−ニングし、第２の積み上
げ電極層１６を形成する。この構造において、スル−プ
ット向上のため第１のデ−タ線１３と第１の積み上げ電
極層１５は同一材料（アルミニウム等）および第２のデ
−タ線１４と第２の積み上げ電極層１６も同一材料とす
ることが望ましい。更に第１の導電層（デ−タ線、積み
上げ電極層）と第２の導電層（デ−タ線、積み上げ電極
層）を連続工程で堆積し、エッチングも連続で行うとス
ル−プットが向上する。特に第２のデ−タ線１４と第２
の積み上げ電極層１６は画素電極ＩＴＯ１８との接続抵
抗が低く、ＩＴＯのエッチンク液に溶解しない材料が望
ましく、本実施例ではＭｏＳｉ2膜を使用したがＴｉＳｉ
2、ＷＳｉ2、ＴａＳｉ2、Ｔｉ、Ｗ、Ｔａ、ＴｉＮ等を用
いても同様な結果が得られる。A source 2 and a gate, to which the first data line 13 and the second data line 14 are electrically connected, are connected to this pixel region.
The gate 7 to which the gate line is electrically connected and the pixel electrode 18 are the first stacked electrode layer 15 and the second stacked electrode layer 1
By the drain 3 which is conductively connected via 6, the TFT 8
Are formed. In the cross-sectional structure of this TFT, a polycrystalline silicon layer 4 is formed on the surface side of an insulating transparent substrate 1 that supports the entire liquid crystal display device. In this polycrystalline silicon, a channel region that is an intrinsic polycrystalline silicon region is formed. With the exception of 5, the source 2 and the drain 3 are formed by introducing phosphorus as an n-type impurity (boron when forming a p-type). Here, the introduction of phosphorus is performed by the gate 7 on the gate oxide film 6 formed on the surface side of the polycrystalline silicon layer 4.
By using ion implantation with a mask
This is performed so that the drain 2 and the drain 3 are self-aligned. A first interlayer insulating film 9 made of a silicon oxide film is deposited on the surface side of the TFT 8, and a first connecting hole 11 and a second connecting hole 12 are opened in the first interlayer insulating film 9. A first data line 13 made of an aluminum layer is conductively connected to the source 2 through the first connection hole. A MoSi 2 layer is deposited on the first data line 13 as a multi-layer wiring structure, and patterned or coated in the same manner as the data line 13 to form a second data line.
Forming a wire 14. On the other hand, the first stacked electrode layer 15 made of an aluminum layer made of the same material as the first data line 13 is electrically connected to the drain 3 through the second connection hole. Further, a multilayer wiring structure is deposited on the first stacked electrode layer 15 by using the same material as that of the second data line 14, and patterning or covering is performed in the same manner as the first stacked electrode layer 15. Then, the second stacked electrode layer 16 is formed. In this structure, the first data line 13 and the first stacked electrode layer 15 are made of the same material (aluminum or the like) and the second data line 14 and the second stacked electrode layer 16 are used for improving the throughput. It is desirable to use the same material. Further, if the first conductive layer (data line, stacked electrode layer) and the second conductive layer (data line, stacked electrode layer) are deposited in a continuous process and etching is also performed continuously, the throughput is improved. To do. Especially the second data line 14 and the second data line
The stacked electrode layer 16 is preferably made of a material that has a low connection resistance with the pixel electrode ITO 18 and does not dissolve in the ITO etching liquid. In this embodiment, a MoSi 2 film is used, but TiSi is used.
Similar results can be obtained by using 2 , WSi 2 , TaSi 2 , Ti, W, Ta, TiN and the like.
【００１０】従って、本液晶表示装置において、上記の
構造を用いることにより画素電極ＩＴＯとの接続抵抗が
低減し、デ−タ線の断線を防止することができるため表
示品質を向上させることが可能である。Therefore, in the present liquid crystal display device, by using the above structure, the connection resistance with the pixel electrode ITO can be reduced and the disconnection of the data line can be prevented, so that the display quality can be improved. Is.
【００１１】[0011]
【発明の効果】本発明の液晶表示装置において前記のと
おり、下層側層間絶縁膜上に形成された、多層配線構造
のデ−タ線と同一材料を用いた画素電極と導通接続して
いる多層構造の積み上げ電極層が形成されていることに
特徴を有するので、以下の効果を奏する。As described above, in the liquid crystal display device of the present invention, a multi-layer formed on the lower interlayer insulating film and electrically connected to a pixel electrode using the same material as the data line of the multi-layer wiring structure. Since the stacked electrode layer having the structure is formed, the following effects can be obtained.
【００１２】従来画素電極ＩＴＯと導通接続していた
積み上げ電極層であるアルミニウム層上に新たにコンタ
クトメタルを形成することによって、積み上げ電極層を
多層構造とし、ＩＴＯとの接続抵抗を低減させることに
より表示品質を向上させることができる。By forming a new contact metal on the aluminum layer which is a stacked electrode layer which has been conductively connected to the pixel electrode ITO, the stacked electrode layer has a multi-layer structure and the connection resistance with ITO is reduced. The display quality can be improved.
【００１３】デ−タ線も前記積み上げ電極層と同一構
造として、デ−タ線の２層目のデ−タ線はＩＴＯのエッ
チング液に溶解しない材料を使用し、上層側層間絶縁膜
の欠陥よりＩＴＯのエッチング液が染み込んでもデ−タ
線が断線するようなことがないため歩留まり向上に非常
に有効な手段である。The data line also has the same structure as the stacked electrode layer, the second data line of the data line is made of a material which is not dissolved in the etching solution of ITO, and the upper layer side interlayer insulating film has a defect. This is a very effective means for improving the yield because the data line does not break even when the ITO etching solution permeates.
【００１４】デ−タ線が上層側層間絶縁膜によって埋
め込まれている構造のため、デ−タ線の電界の影響が少
なく、それによって液晶の配向を乱すことがないので表
示品質が向上する。Since the data line is buried in the upper interlayer insulating film, the influence of the electric field of the data line is small, and the alignment of the liquid crystal is not disturbed thereby, so that the display quality is improved.
【００１５】多層膜を連続工程で堆積し、パタ−ニン
グもドライエッチング等で連続エッチをすれば、フォト
エッチング工程も増えずスル−プットは下がらない。If the multilayer film is deposited in a continuous process and the patterning is also continuously performed by dry etching or the like, the photoetching process is not increased and the throughput is not lowered.
【図１】本発明の一実施例を説明する図。FIG. 1 is a diagram illustrating an embodiment of the present invention.
【図２】従来の液晶表示装置におけるマトリクスアレイ
の断面図その１。FIG. 2 is a sectional view of a matrix array in a conventional liquid crystal display device (Part 1).
【図３】従来の液晶表示装置におけるマトリクスアレイ
の断面図その２。FIG. 3 is a sectional view of a matrix array in a conventional liquid crystal display device (Part 2).
１ 透明絶縁基板 ２ ソ−ス ３ ドレイン ４ 多結晶シリコン膜 ５ チャネル ６ ゲ−ト酸化膜 ７ ゲ−ト電極 ８ ＴＦＴ ９ 下層側層間絶縁膜 １０ 上層側層間絶縁膜 １１ 接続孔１ １２ 接続孔２ １３ 第１のデ−タ線 １４ 第２のデ−タ線 １５ 第１の積み上げ電極層 １６ 第２の積み上げ電極層 １７ 接続孔 １８ 画素電極 DESCRIPTION OF SYMBOLS 1 Transparent insulating substrate 2 Source 3 Drain 4 Polycrystalline silicon film 5 Channel 6 Gate oxide film 7 Gate electrode 8 TFT 9 Lower layer side interlayer insulating film 10 Upper layer side interlayer insulating film 11 Connection hole 1 12 Connection hole 2 13 First Data Line 14 Second Data Line 15 First Stacked Electrode Layer 16 Second Stacked Electrode Layer 17 Connection Hole 18 Pixel Electrode
Claims (2)
リクスアレイが、薄膜トランジスタのソ−スに下層側層
間絶縁膜の第１の接続孔を介して導通接続する第１のデ
−タ線およびこの第１のデ−タ線表面に導通接続して多
重配線構造を構成する第２のデ−タ線と、前記薄膜トラ
ンジスタのドレインに前記下層側層間絶縁膜の第２の接
続孔を介して導通接続しており、導電性のある第１の積
み上げ電極層及びこの第１の積み上げ電極層表面に導通
接続して多重配線構造を構成する第２の積み上げ電極層
と、この積み上げ電極層に上層側層間絶縁膜の接続孔を
介して導通接続しており、端部が前記デ−タ線の上方に
位置する画素電極と、を有することを特徴とする液晶表
示装置。1. A first data line in which a matrix array formed on the front surface side of a transparent insulating substrate is conductively connected to a source of a thin film transistor through a first connecting hole of an interlayer insulating film on the lower layer side. And a second data line which is conductively connected to the surface of the first data line to form a multi-wiring structure, and a drain of the thin film transistor through a second connection hole of the lower interlayer insulating film. An electrically conductive first stacked electrode layer, a second stacked electrode layer which is conductively connected to the surface of the first stacked electrode layer to form a multiple wiring structure, and an upper layer above the stacked electrode layer. A liquid crystal display device, comprising: a pixel electrode which is electrically connected through a connection hole of a side interlayer insulating film, and an end portion of which is located above the data line.
前記第１の積み上げ電極層は同一材料で形成されてお
り、前記第２のデ−タ線と前記第２の積み上げ電極層も
同一材料で形成されていることを特徴とする液晶表示装
置。2. The first data wire and the first stacked electrode layer are formed of the same material as in claim 1, wherein the second data wire and the second stacked electrode are formed. A liquid crystal display device in which layers are also formed of the same material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3523692A JP3491904B2 (en) | 1992-02-21 | 1992-02-21 | Manufacturing method of liquid crystal display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3523692A JP3491904B2 (en) | 1992-02-21 | 1992-02-21 | Manufacturing method of liquid crystal display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003317928A Division JP3622757B2 (en) | 2003-09-10 | 2003-09-10 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05235360A true JPH05235360A (en) | 1993-09-10 |
| JP3491904B2 JP3491904B2 (en) | 2004-02-03 |
Family
ID=12436211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3523692A Expired - Lifetime JP3491904B2 (en) | 1992-02-21 | 1992-02-21 | Manufacturing method of liquid crystal display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3491904B2 (en) |
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|---|---|---|---|---|
| WO1997029400A1 (en) * | 1996-02-09 | 1997-08-14 | Seiko Epson Corporation | Contact structure for multilayer wiring, active matrix substrate and method of manufacturing the same |
| WO1998044566A1 (en) * | 1997-03-31 | 1998-10-08 | Seiko Epson Corporation | Display |
| US6051883A (en) * | 1996-05-16 | 2000-04-18 | Nec Corporation | Manufacturing method and semiconductor device with low contact resistance between transparent electrode and pad electrode |
| JP2001230321A (en) * | 1999-12-31 | 2001-08-24 | Samsung Electronics Co Ltd | Contact structure of wiring, method of forming the same, and thin-film transistor substrate containing the same and method of manufacturing it |
| US6448612B1 (en) | 1992-12-09 | 2002-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor |
| US6798023B1 (en) | 1993-12-02 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising first insulating film, second insulating film comprising organic resin on the first insulating film, and pixel electrode over the second insulating film |
| KR100509221B1 (en) * | 1997-03-31 | 2005-12-09 | 세이코 엡슨 가부시키가이샤 | Display |
| JP2006216936A (en) * | 2005-12-16 | 2006-08-17 | Mitsubishi Electric Corp | Liquid crystal display device, manufacturing method thereof the same and tft array substrate used therefor |
| JP2007103910A (en) * | 2005-09-30 | 2007-04-19 | Lg Philips Lcd Co Ltd | Array substrate for liquid crystal display device, method of manufacturing same, thin film transistor for liquid crystal display device, method of manufacturing same, and liquid crystal display device |
| US7403237B2 (en) | 2004-01-26 | 2008-07-22 | Seiko Epson Corporation | Electro-optical device with electrolytic corrosion preventing film and multiple relay electrodes |
| US7635895B2 (en) * | 1994-07-14 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7105898B2 (en) | 1992-12-09 | 2006-09-12 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
| US6448612B1 (en) | 1992-12-09 | 2002-09-10 | Semiconductor Energy Laboratory Co., Ltd. | Pixel thin film transistor and a driver circuit for driving the pixel thin film transistor |
| US6608353B2 (en) | 1992-12-09 | 2003-08-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having pixel electrode connected to a laminate structure |
| US7045399B2 (en) | 1992-12-09 | 2006-05-16 | Semiconductor Energy Laboratory Co., Ltd. | Electronic circuit |
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| US6798023B1 (en) | 1993-12-02 | 2004-09-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising first insulating film, second insulating film comprising organic resin on the first insulating film, and pixel electrode over the second insulating film |
| US7141461B2 (en) | 1993-12-02 | 2006-11-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a semiconductor device |
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| US7635895B2 (en) * | 1994-07-14 | 2009-12-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| WO1997029400A1 (en) * | 1996-02-09 | 1997-08-14 | Seiko Epson Corporation | Contact structure for multilayer wiring, active matrix substrate and method of manufacturing the same |
| US6051883A (en) * | 1996-05-16 | 2000-04-18 | Nec Corporation | Manufacturing method and semiconductor device with low contact resistance between transparent electrode and pad electrode |
| US6096572A (en) * | 1996-05-16 | 2000-08-01 | Nec Corporation | Manufacturing method and semiconductor device with low contact resistance between transparent electrode and pad electrode |
| US6414738B1 (en) | 1997-03-31 | 2002-07-02 | Seiko Epson Corporation | Display |
| KR100509221B1 (en) * | 1997-03-31 | 2005-12-09 | 세이코 엡슨 가부시키가이샤 | Display |
| WO1998044566A1 (en) * | 1997-03-31 | 1998-10-08 | Seiko Epson Corporation | Display |
| JP2001230321A (en) * | 1999-12-31 | 2001-08-24 | Samsung Electronics Co Ltd | Contact structure of wiring, method of forming the same, and thin-film transistor substrate containing the same and method of manufacturing it |
| US7403237B2 (en) | 2004-01-26 | 2008-07-22 | Seiko Epson Corporation | Electro-optical device with electrolytic corrosion preventing film and multiple relay electrodes |
| JP2007103910A (en) * | 2005-09-30 | 2007-04-19 | Lg Philips Lcd Co Ltd | Array substrate for liquid crystal display device, method of manufacturing same, thin film transistor for liquid crystal display device, method of manufacturing same, and liquid crystal display device |
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| JP2006216936A (en) * | 2005-12-16 | 2006-08-17 | Mitsubishi Electric Corp | Liquid crystal display device, manufacturing method thereof the same and tft array substrate used therefor |
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|---|---|
| JP3491904B2 (en) | 2004-02-03 |
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