JPH05235283A - Mos type input protective circuit device - Google Patents

Abstract

PURPOSE:To reduce the stress on a protective circuit and prevent the break of a protective element, by connecting a gate of an N channel or P channel transistor to a diffusion layer and a ground potential through a diode and connecting a drain of the transistor to a gate of an input internal circuit and an input terminal. CONSTITUTION:When a positive surge is inputted to a ground potential terminal 33, a part of surge electric charges reaching a drain 9 of an N channel transistor 5 enters a P-type semiconductor region 1 due to a breakdown. A diode 19 is formed in the P-type semiconductor region 1 and an N-type diffusion layer 4, and a potential of the P-type semiconductor region 1 other than a P-type diffusion layer 3 increases due to a resistance of the P-type semiconductor region 1 itself. Further, a potential of a gate 10 is temporarily maintained due to a resistor 17 connected between the gate 10 and the ground potential terminal 33. Thus, the N channel transistor 5 makes a continuity to absorb a surge current speedily. Normally, an input signal is directly transmitted to a gate 40 of an input internal circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit device for protecting an internal circuit of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Normally, when a surge such as static electricity is input to the input terminal from the outside of a MOS integrated circuit, the surge charge is absorbed to prevent the dielectric breakdown of the gate oxide film. Between the input gates of the internal circuit,
The protection circuit is connected.

However, due to the recent miniaturization of circuit elements, the protection circuit itself is destroyed in the process of absorbing electric charges. Therefore, there is a need for a protection circuit which quickly absorbs a large current and is not destroyed. Here, four types of surge input models will be considered. The first is to input between the ground potential terminal and the input terminal, the input terminal side is input with a positive bias with respect to the ground potential terminal, and the voltage of the input signal during actual use is exceeded, and the second is Input between the ground potential terminal and the input terminal and input to the input terminal side with a negative bias with respect to the ground potential terminal. Third, input between the power supply potential terminal and the input terminal, and the power source on the input terminal side. Input with a positive bias to the potential terminal. Fourth, input between the power supply potential terminal and the input terminal, and input to the input terminal side with a negative bias with respect to the power supply potential terminal. The voltage of the input signal of is exceeded.

3 and 4 show examples of conventional protection circuit devices. The source 27 of the N-channel transistor 23 formed in the P-type semiconductor region 21, the substrate contact diffusion region 28, and the gate 26 are connected to the ground potential terminal 35. Further, the source 31, the substrate contact diffusion region 32, and the gate 30 of the P-channel transistor 24 formed in the N-type semiconductor region are connected to the power supply potential terminal 36. N-channel transistor 23 drain 25
The drain 29 of the P-channel transistor is connected to the input terminal 38 and the gate 41 of the input circuit.
When a surge is input from the input terminal 38 to the ground potential terminal 35 with a negative bias, the N-channel transistor 23 is conductive and the PN junction from the drain 25 to the P-type semiconductor region 21 is forward biased. Surge current is absorbed, but conversely, when the surge is a positive bias, N
The channel transistor 23 will absorb the current due to breakdown. When inputting a positive bias from the input terminal 38 to the surge power supply potential terminal 36,
The P-channel transistor 24 is conductive, and the PN junction from the drain 29 to the N-type semiconductor region 22 becomes a forward bias to absorb the surge current. Conversely, when the surge has a negative bias, the P-channel transistor 24 24
Will absorb the current at breakdown.

[0005]

In the conventional example, depending on whether the bias of the surge is positive or negative, the surge is absorbed by the breakdown at the drain, but the current allowance at the time of breakdown is small, so that the protection circuit is used. However, there is a problem that the transistor is subjected to a great deal of stress and is destroyed. Considering that the surge voltage such as static electricity inputted may be positive or negative, it is necessary to have a structure capable of effectively absorbing a large instantaneous current in both cases.

[0006]

In a MOS type input protection device of the present invention, an N-type or P-type transistor in which a gate of an N-channel or P-channel transistor formed in a P-type or N-type semiconductor region is formed in the semiconductor region. A source of the transistor and a diffusion layer formed in the semiconductor region are connected to a ground potential, and a gate of the transistor is connected to the ground potential through an element having a finite resistance. The drain of is connected to the gate and the input terminal of the input internal circuit.

Still another invention is the above-mentioned two types of M.
The OS type input protection device is connected in parallel.

[0008]

Since the gate of the transistor is connected to the semiconductor region in which the transistor is formed through the diode, the semiconductor region in which the transistor is formed is selectively selected only when a bias surge that causes a breakdown is input. A part of the surge charge is transmitted to the gate via. Therefore, when a breakdown is about to occur, the potential of the gate changes. Further, the gate is connected to the ground potential terminal (when the protection transistor is an N-channel transistor) or the power supply potential terminal (when the protection transistor is P
By connecting to the channel transistor), the gate potential changed by the surge input can be maintained only for the delay time due to the resistance element. By doing so, the transistor is made conductive only at the moment of surge input, and the surge is quickly absorbed. At this time, the current gives less stress to the protection circuit than the breakdown current.

[0009]

1 is a sectional view according to the present invention, and FIG. 1 is an equivalent circuit diagram thereof. An N channel transistor 5, a P type diffusion layer 3 and an N type diffusion layer 4 are formed in the P type semiconductor region 1. The gate 10 of the N-channel transistor 5 is connected to the N-type diffusion layer 4, and the source 11 of the N-channel transistor 5, the substrate contact diffusion region 12 of the N-channel transistor 5, the P-type diffusion layer 3 and one end of the polysilicon resistor 17 are connected. It is connected to the ground potential terminal 33. The other end of the polysilicon resistor 17 is connected to the gate 10. Further, a P channel transistor 8, an N type diffusion layer 6 and a P type diffusion layer 7 are formed in the N type semiconductor region 2. The gate 14 of the P-channel transistor 8 is connected to the P-type diffusion layer 7, and the source 15 of the P-channel transistor 8 and the P-channel transistor 8 are connected.
The substrate contact diffusion region 16, the N-type diffusion layer 6, and one end of the polysilicon resistor 18 are connected to the power supply potential terminal 34. The other end of the polysilicon resistor 18 is connected to the gate 14. The drain 9 of the N-channel transistor 5 and the drain 13 of the P-channel transistor 8 are connected to the input terminal 37.
And the gate 40 of the input internal circuit.

First, consider the case where a positive surge is input to the ground potential terminal 33. A part of the surge charge reaching the drain 9 of the N-channel transistor 5 enters the P-type semiconductor region 1 due to breakdown. At this time,
Although the P-type semiconductor region 1 is held at the ground potential by the substrate contact diffusion region 12 and the P-type diffusion layer 3, the P-type semiconductor region 1 is P-type by the resistance 42 of the P-type semiconductor region itself.
The potential of the P-type semiconductor region 1 other than the type diffusion layer 3 increases. The P-type semiconductor region 1 and the N-type diffusion layer 4 form a diode 19, and the potential of the P-type semiconductor region 1 at the time of surge input is forward biased to the diode 19, so that the gate 1 is formed.
The potential of 0 rises. Further, because of the resistance element 17 connected between the gate 10 and the ground potential terminal 33, the potential of the gate 10 is temporarily maintained. Therefore, the N-channel transistor 5 becomes conductive and quickly absorbs the surge current. During normal use, the input signal from the input terminal 37 is equal to or lower than the breakdown voltage of the transistor, so that the N-channel transistor 5 as a protection element does not conduct, and the input signal remains as it is.
Is transmitted to. Next, consider the case where a negative surge is input to the ground potential terminal 33. In this case, a forward bias is applied to the drain 9 of the N-channel transistor 5 and the diode 19 formed of the P-type semiconductor region 1, and the input surge current passes through the P-type diffusion layer 3 and the substrate contact diffusion region 12. It is immediately absorbed by the ground potential terminal 33. Next, consider the case where a negative surge is input to the power supply potential terminal 34. A part of the surge charge reaching the drain 13 of the P-channel transistor 8 enters the N-type semiconductor region 2 due to breakdown.
At this time, although the N-type semiconductor region 2 is kept at the power supply potential by the substrate contact diffusion region 16 and the N-type diffusion layer 6, the resistance 43 of the N-type semiconductor region itself is suppressed.
As a result, the potential of the N-type semiconductor region 2 other than the N-type diffusion layer 6 drops. The N-type semiconductor region 2 and the P-type diffusion layer 7 form a diode 20, and the potential of the N-type semiconductor region 2 at the time of surge input is forward biased with respect to the diode 20, so that the potential of the gate 14 decreases. Further, because of the resistance element 18 connected between the gate 14 and the power supply potential terminal 34, the potential of the gate 14 is temporarily maintained. For this reason, the P-channel transistor 8 becomes conductive and quickly absorbs the surge current. Since the input signal from the input terminal 37 is below the breakdown voltage of the transistor during normal use, the P-channel transistor 8 as a protection element is used.
Does not conduct, and the input signal is directly transmitted to the gate 40 of the input internal circuit. Next, consider the case where a positive surge is input to the power supply potential terminal 34. in this case,
The drain 13 of the P-channel transistor 8 and the diode 20 formed of the N-type semiconductor region 2 become a forward bias, and the surge current that has been input passes through the N-type diffusion layer 6 and the substrate contact diffusion region 16 and is immediately supplied with the power supply potential. It is absorbed by the terminal 34.

[0011]

[Effect of the Invention] Whether the bias of the surge input with respect to the ground potential or the power supply potential is positive or negative, the stress applied to the protection circuit is reduced by absorbing the surge without breaking down the protection transistor, and the protection element is protected. Can be prevented from being destroyed.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment according to the present invention.

FIG. 2 is an equivalent circuit diagram showing an embodiment of the present invention.

FIG. 3 shows an example of a conventional MOS type input protection circuit device.

FIG. 4 is an equivalent circuit diagram of a conventional MOS type input protection circuit device.

[Explanation of symbols]

1,21 P-type semiconductor region 2,22 N-type semiconductor region 3,7 P-type diffusion layer 4,6 N-type diffusion layer 5,23 N-channel transistor 8,24 P-channel transistor 9,25 N-channel transistor drain 10, 26 N-channel transistor gate 11,27 N-channel transistor source 12,28 N-channel transistor substrate contact diffusion region 13,29 P-channel transistor drain 14,30 P-channel transistor gate 15,31 P-channel transistor source 16 , 32 P-channel transistor substrate contact diffusion region 19, 20 Diode 17, 18 Polysilicon resistance 33, 35 Ground potential terminal 34, 36 Power supply potential terminal 37, 38 Input terminal 40, 41 DOO 42 P-type semiconductor region itself of the resistance 43 N-type semiconductor region itself resistor

Claims (3)

[Claims] 1. A gate of an N-channel transistor formed in a P-type semiconductor region is connected to an N-type diffusion layer formed in the P-type semiconductor region, and formed in the source of the N-channel transistor and the P-type semiconductor region. The P-type diffusion layer is connected to the ground potential, the gate of the N-channel transistor is connected to the ground potential through an element having a finite resistance, and the drain of the N-channel transistor is connected to the gate of the input internal circuit and the input terminal. And a MOS type input protection circuit device. 2. A gate of a P-channel transistor formed in an N-type semiconductor region is connected to a P-type diffusion layer formed in the N-type semiconductor region, and formed in a source of the P-channel transistor and the N-type semiconductor region. The N-type diffusion layer is connected to the power supply potential, the gate of the P-channel transistor is connected to the power supply potential through an element having a finite resistance, and the drain of the P-channel transistor is connected to the gate of the input internal circuit and the input terminal. And a MOS type input protection circuit device. 3. A MOS type input protection circuit device in which the MOS type input protection circuit device according to claim 1 and the MOS type input protection circuit device according to claim 2 are connected in parallel.