JPH0523466B2 - - Google Patents

Description

[Detailed Description of the Invention] <<Industrial Application Field>> The present invention is an image processing method that detects the presence or absence of abnormal conditions on the surface of an object, such as scratches, by inputting a digital video signal output from a TV camera or the like. It is related to the device.

<Conventional technology> Conventionally, product flaw inspection involves binarizing the image from a TV camera using an appropriate threshold, effectively separating the flawed area, and measuring its area, shape, etc.

[Problems to be solved by the invention] However, with such methods, it is usually difficult to automatically set the optimal threshold, and even if the best threshold is found, it may not necessarily cause damage depending on the target. It is not always possible to separate the normal part from the normal part.

The present invention was made in order to solve the above problems, and an object thereof is to realize an image processing device with a simple configuration that can detect the presence or absence of an abnormal state on the surface of an object with high reliability. do.

《Means for solving the problem》 The digital video signal is stored in an image processing device that inputs the digital video signal output from a TV camera, etc., and detects the presence or absence of abnormal conditions on the surface of the object, such as scratches. an image memory that inputs the output of this image memory and calculates an autocorrelation value of the image using the amount of movement in the coordinate space as a parameter; The present invention is characterized by comprising: a register for storing a reference autocorrelation value; and a comparison means for comparing the autocorrelation value of the calculation means with the reference autocorrelation value stored in the register.

"Example" The basic principle of the embodiment will first be explained.

The autocorrelation of the grayscale image F(i,j) can be calculated using the following equation.

A(i, j) = 〓 ^m 〓 ⁿ F (m+i, n+j)・F(m, n) Generally, the autocorrelation of irregular images takes the maximum value at the origin, and the amount of movement (i, j) That is, as the deviation between the two images becomes larger, it becomes smaller. When something that disturbs the uniformity, such as a scratch, appears in the image, the autocorrelation value decreases rapidly. FIG. 2 is a characteristic curve diagram showing changes in the autocorrelation value with respect to the amount of movement (n, n) in the coordinate space. Since the value at the origin (peak value) differs depending on the object, the value at the origin is assumed to be 0, and if there is no flaw (upper 4 points)
The case with scratches (the one point below) is plotted overlappingly. Therefore, by evaluating the difference between the autocorrelation value at an appropriately moved point (for example, n=10) and the autocorrelation value at the origin (n=0), that is, the degree of inclination, the presence or absence of a flaw can be determined.

The present invention will be explained in detail below using the drawings.

FIG. 3 is a block diagram showing a basic embodiment of an image processing apparatus according to the present invention. M is an image memory that stores digital video signals, AG is an address generator that specifies the address of this image memory M, R ₁ is a register that holds the first image data read from the image memory M, and R ₂ is a register that also holds the second image data, MU
1 is a multiplier that inputs the outputs of these registers R ₁ and R ₂ , AU1 is an arithmetic logic circuit that uses the output of this multiplier MU1 as one input, and R ₃ is this arithmetic logic circuit.
a register that holds the output of AU1 and whose output is the other input of the arithmetic logic circuit AU1; MU2 is a multiplier whose two inputs are the outputs of the register _R1 ;
AU2 is an arithmetic logic circuit whose one input is the output of this multiplier MU2, and _R4 is this arithmetic logic circuit AU2.
holds the output of the arithmetic logic circuit AU.
2, AU3 is an arithmetic logic circuit to which the outputs of registers R ₃ and R ₄ are input;
CP is a comparator that takes the output of this arithmetic logic circuit AU3 as one input, R ₀ is a register that is set with the reference output that is the other input of this comparator CP, and 1 is connected to the output of the comparator CP. It is an output terminal.

Next, the operation of the image processing apparatus having such a configuration will be explained in detail. The address generator AG sequentially generates addresses at two points separated by the amount of movement (n, n). Image memory M sequentially outputs grayscale image signals at addresses designated by address generator AG. One of the two grayscale image signals is input to register _R1 , and the other is input to register _R2 and held there. Registers operated by multiplier MU1
The product of the R ₁ and R ₂ outputs is accumulated in the register R ₃ via the arithmetic logic circuit AU1, and becomes an autocorrelation value at the movement amount (n, n). Multiplier MU2 calculates the square of the output of register _R1 , and the output is sent to arithmetic logic circuit AU2.
is accumulated in register _R4 via the movement amount (0,
0) is the autocorrelation value. Arithmetic logic circuit AU3
calculates the difference between the two autocorrelation values output from registers R ₃ and R ₄ , and the output is the reference value output from register R ₀ at comparator CP, for example, when the surface of the object is in a normal state. The output of the comparator CP becomes a judgment output indicating the presence or absence of a flaw.

According to the image processing device having such a configuration, by using the slope of the autocorrelation value, it is possible to detect flaws that are difficult to detect using the binarization method.

Further, by substituting the slope of the autocorrelation value with the difference between the values of two points, the origin (0, 0) and another point (n, n), the amount of calculation can be reduced.

FIG. 1 is a block diagram showing a second embodiment of an image processing apparatus according to the present invention. The same parts as in FIG. 3 are given the same symbols and the explanation is omitted. _R5
is a register that creates a one-clock delay for the output of register _R1 , MU3 is a multiplier that inputs the outputs of register _R5 and register _R2 , _R6 is a register that holds the output of this multiplier MU3, and LU
is a lookup table that inputs the output of the register _R5 , and _S1 is this lookup table.
A selector that inputs the output of LU and the register _R6 , AU4 is an arithmetic logic circuit that receives the output of this selector _S1 as one input, and _S2 is this arithmetic logic circuit.
A selector _R7 inputting the output of AU4 and the output of register _R0 is an accumulation register that holds the output of selector _S2 and uses the output as the other input of the arithmetic logic circuit AU4. The register R ₀ and the selector S ₂ constitute a comparing means, and the parts other than this comparing means, the image memory M, and the address generator AG constitute an arithmetic means.

The operation of the image processing apparatus configured as above will be explained below. FIG. 4 is a timing chart showing the operation of this device. For example, if a 320x240x8 image memory M is used, the address generator AG generates a 9-bit address signal Ax.
Then, specify a 320×240 address using an 8-bit address signal Ay. For example, if the amount of movement in the coordinate space is (n, n) = (10, 10), then the addresses of two points (10, 10) apart are (0, 0), (10, 10), (1,
0), (11, 10), (2, 0), (12, 10), ... (0,
1), (10, 11), (1, 1), (11, 11), etc. are generated sequentially. Of the 8-bit (256 gradation) data output from the image memory M, data Df that is output earlier is held in register _R1 , and data Ds that is output later is held in register _R2 . register R ₁
Since the output of register _R5 is delayed by one clock, the timings of the outputs of register _R5 and register _R2 are aligned. Rutskup Table
LU inputs data Df from register _R5 and
Output Df ² . At this time, it is assumed that access to the lookup table LU is completed within one clock. The product DfDs of both register outputs output from multiplier MU3 is held in register _R6 . Selector _S1 selects the output of lookup table LU or register _R6 and outputs data ^Df2 or DfDs to one input of arithmetic logic circuit AU4. Arithmetic logic circuit AU4 is the output of selector _S1 and register
Input the output of R ₇ and perform addition and subtraction. D ₇ ^* in Figure 4
is the contents of register _R7 one clock ago. Usually, an adder/subtractor (here, an arithmetic logic circuit) has an operation speed about twice that of a multiplier, so that each addition/subtraction can be performed once during one multiplication.
That is, calculate 〓 ⁱ Dfi ² − 〓 ⁱ DfiDsi as 〓 ⁱ (Dfi ² −
DfiDsi). Since register _R0 sets a negative reference value as an initial value in register _R7 via selector _S2 , the sign of the accumulation result of register _R7 becomes the judgment output.

According to the image processing device having such a configuration, only one adder/subtractor is required, and a comparator can be omitted, resulting in a simple configuration.

Also, if the multiplier is about twice as slow as the adder/subtractor,
By using a lookup table for square calculation, it is possible to perform calculations with high efficiency as a whole.

In the above embodiment, the timing differs depending on the operating speed of the multiplier, arithmetic logic circuit, and lookup table. For example, if the lookup table is slow, a latch circuit will be required afterwards, and the timing chart will be different.

FIG. 5 is a configuration block diagram showing a third embodiment of the image processing apparatus according to the present invention, in which the multiplier has an operating speed comparable to that of the arithmetic logic circuit. The same parts as in FIG. 3 are given the same symbols and the explanation is omitted. S ₂ is register R ₁ and register R ₂
The selector MU4 which selects the output of is a multiplier which inputs the output of this selector _S3 and the register _R1 . The output of register _R6 which latches the output of multiplier MU4 becomes one input of arithmetic logic circuit AU4.

The operation of the image processing apparatus having such a configuration will be described below. FIG. 6 is a time chart for explaining the operation of the apparatus shown in FIG. Selector S ₃
selects register _R1 , multiplier MU4 selects Df
As two inputs, Df ² is output to selector R ₆ . When selector S ₃ selects register R ₂ , multiplier MU
4 inputs Df and Ds and outputs DfDs to selector _R6 . The output of selector _R6 is input to AU4 for accumulation and determination as in the case of FIG.

According to the image processing device having such a configuration, since the square is also calculated by the multiplier, a lookup table is not required, and the configuration is simplified.

Note that in each of the above embodiments, scratches on the target object are detected, but the present invention is not limited to this, and any abnormal state such as dirt can be detected.

Also, the amount of movement is (n, n) parallel to the diagonal line.
However, any appropriate (m, n) can be used.

<<Effects of the Invention>> As described above, according to the present invention, an image processing device capable of detecting the presence or absence of an abnormal state on the surface of an object with high reliability can be realized with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram showing a second embodiment of the image processing device according to the present invention, FIG. 2 is a characteristic curve diagram for explaining the operating principle of the device shown in FIG. 1, and FIG. A configuration block diagram showing a first embodiment,
FIG. 4 is a time chart showing the operation of the device shown in FIG. 3, FIG. 5 is a configuration block diagram showing the third embodiment of the present invention, and FIG. It's a chat. M...image memory, n...movement amount, CP...comparison means.

Claims (1)

[Scope of Claims] 1. In an image processing device that receives a digital video signal output from a TV camera or the like to detect the presence or absence of an abnormal state on the surface of an object such as a scratch, an image memory that stores the digital video signal. and a calculation means that inputs this image memory output and calculates the autocorrelation value of the image using the amount of movement in the coordinate space as a parameter, and a calculation means that calculates the autocorrelation value of the image when the surface of the object is in a normal state. An image processing device comprising: a register for storing a value as a value; and a comparison means for comparing an autocorrelation value of the calculation means with a reference autocorrelation value stored in the register.