JPH05234372A - Dynamic logic circuit - Google Patents

Abstract

PURPOSE:To provide a dynamic logic circuit wherein a noise which is generated in a power supply or in a ground can be reduced in a dynamic operation. CONSTITUTION:The title logic circuit is provided with the following: a signal- line group 2; and a signal supply circuit 3 which supplies individual logic signals to individual signal lines A0 to A7 in the signal-line group 2. A charge-giving means 4 which gives a precharge to the individual number of signal lines in the signal-line group 2, e.g. A0 to A3, and which gives a discharge to the remaining signal lines A4 to A7 is installed. By this constitution, a noise with reference to a power supply or a ground can be reduced as a whole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic logic circuit, and more particularly to a dynamic logic circuit which is applied to a bus or a memory bit line which dynamically operates in a semiconductor integrated circuit to reduce noise. Regarding

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, when an internal signal line such as an address signal or a logical signal is used, a logical signal is read or written in synchronization with a clock signal. Must be fixed.

Generally, dynamic operation and static operation are adopted to realize such operation.
The dynamic operation is to apply a certain potential to each signal line in advance and invert or hold the signal value at the timing of reading or writing. Further, the static operation is to read or write the signal value of each signal line as it is.

By the way, in recent years, as semiconductor integrated circuits have become more sophisticated and more complicated, real devices have become larger and bus configurations have become larger, and a large amount of address signals and logic signals are processed simultaneously. The number of signal lines having a required bus configuration has increased remarkably. In addition, the bus is often operated dynamically as the load on each signal line increases due to the increase in size of the semiconductor chip itself.

However, when such a bus is dynamically operated, many elements are simultaneously turned on during the operation.
Will be turned off. For this reason, the power supply or ground (ground) of the semiconductor chip depends on the current that flows when turning on and off
Noise is generated. This noise increases as the flowing current increases. In order to reduce such noise, it is conceivable to slightly shift the operation timing of each signal line forming the bus, but such a method cannot be applied to a circuit operating at a high frequency.

[0006]

As described above, the conventional configuration has a problem in that noise is generated in the power supply or the ground during dynamic operation, which causes malfunction or element destruction.

Therefore, it is an object of the present invention to provide a dynamic logic circuit capable of reducing noise generated in a power supply or a ground during dynamic operation and eliminating malfunction and element destruction.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a signal line group,
In a dynamic logic circuit having a signal supply circuit for supplying a logic signal to each signal line of this signal line group, precharging is applied to an arbitrary number of signal lines in the signal line group, and to remaining signal lines. A charge giving means for giving a discharge is provided.

[0009]

In the dynamic logic circuit having the above-mentioned structure, the charge giving means gives a precharge to an arbitrary number of signal lines in the signal line group and a discharge to the remaining signal lines. As a result, an arbitrary number of signal lines in the signal line group are precharged, and the remaining signal lines are discharged. As a result, when the signal supply circuit supplies a logic signal to each signal line to determine the signal value of each signal line, or when each determined signal value is read out, each element flowing in the same direction at the same timing The current decreases in accordance with the division ratio of the signal line divided into precharge and discharge, and as a result, noise with respect to the power supply and ground is reduced as a whole.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A dynamic logic circuit which is an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a dynamic logic circuit diagram showing an embodiment of the present invention.
The dynamic logic circuit 1 has an 8-bit structure using CMOS.

The dynamic logic circuit 1 includes a signal line A
Signal line group 2 consisting of 0 to A7 and each of the signal lines A0 to A
8 buffers B0 for supplying logic signals to 7
To B7 and signal lines A0 to A
A first charge applying circuit 4A for applying a precharge to four signal lines A0 to A3 among the seven, and a second charge applying circuit 4A for applying a discharge to the remaining signal lines A4 to A7.
Charge applying means 4 including a charge applying circuit 4B
And an inverter 5 for inverting the polarity of the charge signal input to the second charge applying circuit 4B among the charge signals supplied to the signal lines A0 to A7 via the charge applying means 4. ..

The first charge applying circuit 4A is composed of gates G0 to G3 using N-type FETs for supplying charge signals to the signal lines A0 to A3, respectively. The second charge applying circuit 4B is composed of gates G4 to G7 using P-type FETs for supplying the charge signals whose polarities are inverted by the inverter 5 to the signal lines A4 to A7, respectively. Further, for each buffer B0 to B7,
A clock signal for turning these on and off at a predetermined timing is input.

Next, the dynamic logic circuit 1 of the present embodiment.
The operation will be described. First, a high charge signal is input to the first charge applying circuit 4A, and a low charge signal whose polarity is inverted by the inverter 5 is input to the second charge applying circuit 4B. As a result, the gates G0 to G3 of the first charge applying circuit 4A are
Open, and the signal lines A0 to A3 are precharged by a high charge signal. On the other hand, since the low charge signal is input to the second charge applying circuit 4B, the gates G4 to G7 are opened and the signal lines A4 to A7 are discharged by the low charge signal.

During the precharge and discharge operations of the signal lines A0 to A3 and the signal lines A4 to A7, a current flows from the power source Vcc to the signal line group 2 to cause a momentary power source voltage drop. Since the signal lines A4 to A7 are discharged, the current is only the sum of the currents flowing in the precharged signal lines A0 to A3. The value of is only half, and as a result, the power supply voltage drop and the noise can be reduced.

After that, a clock signal is sent to each of the buffers B0 to B7 to turn on each of the buffers B0 to B7 and supply a logic signal from a signal source (not shown) to each of the signal lines A0 to A8 to supply each of the signal lines A0 to A8. Confirm the signal value of. At this time, if the logic signals are low, the signal line A0
The signal values of the signal lines A4 to A3 are inverted, but the signal values of the signal lines A4 to A7 are not inverted. Even in this case, the signal value to be inverted is half that in the case where all the signal lines A0 to A8 are precharged. As a result, each signal line A0
Only current flows from A3 to ground,
It is possible to reduce fluctuations in the ground voltage and noise.

The present invention is not limited to the above-mentioned embodiments, but various modifications can be made within the scope of the gist thereof. For example, although the signal line group forming the bus has been described in the above embodiments, the present invention intends to reduce the power supply and ground voltage of a large-capacity memory if the signal line group is considered as a bit line of the memory. May be.

[0017]

According to the present invention described in detail above, by providing the charge applying means for precharging an arbitrary number of signal lines in the signal line group and discharging the remaining signal lines. , Power supply according to the division ratio of the signal line,
It is possible to provide a dynamic logic circuit capable of reducing noise with respect to the ground and improving reliability.

[Brief description of drawings]

FIG. 1 is a dynamic logic circuit diagram that is an embodiment of the present invention.

[Explanation of symbols]

 1 dynamic logic circuit 2 signal line group 3 signal supply circuit 4 charge applying means 5 inverters A0 to A7 signal lines

Claims (1)

[Claims] 1. A dynamic logic circuit having a signal line group and a signal supply circuit for supplying a logical signal to each signal line of the signal line group, wherein an arbitrary number of signal lines in the signal line group are provided. A dynamic logic circuit characterized in that a charge applying means for applying a precharge to a remaining signal line is provided.