JPH05233761A - Wiring method and print circuit board design system - Google Patents

Abstract

PURPOSE:To attain the high speed of an automatic wiring processing validly using a channel in a multi channel substrate. CONSTITUTION:A path retrieval is normally operated in four horizontal and vertical directions, and operated in four oblique directions only when a proceeding to the four horizontal and vertical directions is not possible due to an obstacle (step 102-105). Also, at the time of a wiring pattern deciding processing by an automatic wiring, first of all, a straight wiring is operated, and then the wiring pattern is made to by-pass the surrounding of a bia, or a point where the capability of the usage of the bia is preliminarily decided (bia enabling position) on the wiring specification of a print circuit board (step 107 and 108).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for automatically determining a wiring pattern on a printed circuit board, and more particularly to a wiring method for a multi-channel circuit board and a printed circuit board design system.

[0002]

2. Description of the Related Art In recent years, a printed circuit board, which is an essential component in electronic equipment such as an information processing apparatus, has been made finer in pattern and has more channels in order to achieve higher density.

When the number of channels of the substrate is increased, the time required for the automatic wiring process increases accordingly. Particularly, in the case of the maze method wiring in which the substrate is divided into wiring grids and the wiring path is searched for each wiring grid, the processing time increases in proportion to the square of the number of channels.

Further, since the channel spacing is narrowed due to the miniaturization of the pattern, when the via is used, the channel at the position sandwiched by the via and the linear wiring pattern becomes impassable (for example, 91 in FIG. 9). Channel connecting 92). Therefore, there is a tendency that the wiring pattern becomes an obstacle to the next wiring, and the advantage of multi-channeling does not appear.

Therefore, conventionally, when another wiring is passed over a channel sandwiched by a via and a linear wiring pattern, or when a via is used over a channel sandwiched by a linear wiring pattern, it becomes an obstacle. Search for other wiring patterns,
This has been dealt with by pushing the wiring pattern to a position where the necessary gap can be secured, or by removing the existing wiring pattern once and then rewiring it.

[0006]

However, in the above-mentioned conventional technique, it takes a lot of time to search for a fault pattern and calculate rewiring. The high-density multi-channel substrate requires a huge amount of processing time, which may cause a delay in commercialization.

An object of the present invention is to provide a wiring method and a printed circuit board design system which can perform wiring processing of a multi-channel board at high speed.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above object, and in one aspect thereof, in a method of wiring a printed circuit board, a wiring forbidden to form a wiring pattern. A wiring method is provided in which a wiring pattern is detoured in the vicinity of the restricted area in advance.

The wiring restricted area is an area in which it has been determined that a via or a pin of a component is to be arranged, and / or an area in which it is predetermined to maintain the via in a settable state (hereinafter, It is preferable that it is a “via-settable area”.

Further, the above-mentioned detouring is performed with a space that allows at least one other wiring pattern to be formed between the detoured wiring pattern and the wiring restricted area. Is preferred.

After the placement positions of all vias are determined, it is preferable to shape the detoured wiring pattern near the via-possible region in the via-possible region portion where the vias are not actually provided.

In addition, even after the determination of all the wiring patterns, if there is an area where another wiring pattern can be formed between the detoured wiring pattern and the restricted area, It is preferable to shape the wiring pattern so that the length of the bypassed wiring pattern is shortened.

As another aspect of the present invention, in a route search method using a maze method used in a printed circuit board design system, a route search is first performed in four horizontal and vertical directions, and the four directions are not advanced. A wiring method is provided, which is characterized in that the path search is performed in four diagonal directions only occasionally.

According to another aspect of the present invention, the substrate is divided by a predetermined grid, and a storage means for storing grid data for each grid point and a wiring route are searched with reference to the grid data. In the printed circuit board design system including a search means, the grid data is configured to include information indicating a wiring restricted area where it is prohibited to form a wiring pattern, and the search means is In the vicinity of the wiring restricted area, there is provided a printed circuit board design system characterized by circumventing a wiring pattern in advance.

As another aspect of the present invention, in a printed circuit board design system for performing route search using a maze method,
The substrate is divided by a predetermined grid, and a storage means that stores grid data for each grid point and a reference to the grid data are first searched for a route in four horizontal and vertical directions. There is provided a printed circuit board design system, which further comprises a search means for performing path search in four diagonal directions only when the vehicle cannot proceed in the direction.

That is, in order to speed up the automatic wiring process of the multi-channel substrate, the following three means are taken.

(1) When wiring is completed for one pin pair, a wiring grid point on a channel next to some of the linear patterns used for the wiring is searched, and if there is a via at that point, the linear pattern is searched. Detour around that via.

(2) When the wiring is completed for one pin pair, the wiring grid points on the channels next to some of the straight line patterns used for the wiring are searched, and if these points are used in advance in the wiring specifications of the printed circuit board. If the point is determined to be possible (via possible position), the straight line pattern is detoured around the via possible position.

(3) In the wiring route search processing, the route search is first performed in four horizontal and vertical directions, and the diagonal four-direction route search is performed only when the obstacle cannot advance in these four directions.

[0020]

According to the above-mentioned means, the wiring grid which allows the passage of the pattern on the next wiring can be provided adjacent to the via by means of the means (1).

By the means (2), it is possible to leave a wiring grid for enabling the use of vias at the positions where vias can be made in the next wiring.

Further, the means (3) can search the wiring grid in the area sandwiched between the via and the detoured pattern, and can quickly find the wiring path constituted by the straight line and the diagonal line.

That is, according to the present invention, the processing (1) and (2) is performed by trial and error by preliminarily securing an area through which a pattern can be passed or an area through which a via can be used in consideration of a route search of a later wiring. In the horizontal, vertical, and diagonal directions in the wiring route search by means (3).
In the majority of cases where the direction is searched, only four directions are required, and only when the route is not found, the processing is speeded up by searching the route diagonally.

[0024]

An embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 2, the structure of the printed circuit board design system of this embodiment has a central processing unit 21 and a terminal 22. Also, the logical connection information file 2
3, a component library file 24, a board library file 25, a printed board design file 26,
And a storage device for storing.

The terminal 22 has a part name, shape, number of pins,
It is for inputting the shape of the board, the number of layers, the number of channels, the connection relationship between component pins, and the like.

The component library file 24 is stored in the terminal 2
It is a collection of the product names, shapes, pin numbers, etc. of the parts input from 2. Similarly, the board library file 25
Is a summary of the shape of the substrate, the number of layers, the number of channels, and the like. The logical connection information file 23 is a collection of connection relationships between component pins.

On the other hand, the printed circuit board design file 26 stores the grid data referred to when the wiring is determined and the designed information. As shown in FIG. 4, the grid data refers to the wiring area of the printed circuit board 41.
Wiring information such as hole information 43, pad information 44, pattern information (for 8 directions) 45, a wiring prohibition flag 46, and a via settable flag 47 are stored for each wiring grid.

The hole information 43 is information indicating whether or not a hole for a component pin or a hole for a via is provided at the lattice point. Also, the shape and size of the hole,
It also contains identification information indicating the application (for example, whether it is a hole for a component pin or a hole for a via).

The pad information 44 is information indicating whether or not a via pad or a component pin pad exists at the grid point. In addition, the shape and size of the pad, and further the application (for example, is it a pad for holes for component pins,
It also includes identification information indicating whether the pad is for a via).

The wiring prohibition flag 46 is a flag that is referred to when searching for a wiring route, and is a flag indicating whether or not wiring may be performed at the grid point. Therefore, in the hole information 43, the pad information 44, etc., when the parts, pads, etc. are to be arranged at the lattice points, the wiring prohibition flag is set.

The via settable flag 47 is for indicating a grid point that needs to be kept in a usable state in advance due to the wiring specifications of the printed circuit board. As for wirings passing alongside the grid point where the flag is set, detour processing is performed as described later.

The "wiring restriction area" referred to in the claims means an area in which the wiring prohibition flag 46 is raised due to the existence of a component pin hole or a via, and a via settable flag 47 is raised. It is a concept that includes both the area and

The central processing unit 21 has a function of performing an automatic wiring process by executing a program that it has internally. The central processing unit 2
By executing the program, 1 constitutes search means referred to in the claims.

The outline of the printed circuit board design will be described with reference to FIG.

Prerequisite data and the like are necessary for executing the automatic design. Therefore, first, the terminal 22
The product name, shape, number of pins, etc. of the parts are input to create the parts library file 24. Similarly, the board library file 25 and the logical connection information file 23 are created (step 30).

When the automatic design is started, the central processing unit 21 first carries out a component placement determining process based on the information stored in the various files (step 31). This processing is to determine the placement of components automatically or interactively in consideration of the wiring length and heat generation of components.

Next, a wiring pattern for connecting the component pins is determined by automatic wiring processing (step 32).
The present embodiment is characterized by the automatic wiring process, and details thereof will be described later.

Further, the wiring pattern is folded by the interactive wiring processing for the unwiring in the automatic wiring processing of step 32 (step 33).

After all the wiring patterns are determined, the connection check and the conductor gap check between the wiring patterns, that is, DRC (Design Rule Check) is performed.
k) is performed (step 34), and after confirming that there is no error, the designed information is printed circuit board design file 2
Store in 6.

Then, if necessary, the data stored in the printed circuit board design file 26 is output as various NC control data (step 35).

Details of the automatic wiring process performed in step 32 of FIG. 3 will be described.

The automatic wiring process described below is basically a maze method, and candidates for wiring (paths, grid points) are possible.
The search is continued for all of them, and one of the obtained plurality of wiring routes is selected based on the condition such as the length of the wiring. However, in order to simplify the explanation, only one path and lattice will be taken out for explanation.

First, an initial setting is performed by preprocessing of automatic wiring. That is, the placement information of the components determined by the component placement determination process (step 31 in FIG. 3) is extracted from the printed circuit board design file 26. Further, the relative position of the component pin with respect to the reference point of the component, the hole of the component pin, and the type of pad are taken out from the component library file 24, and the wiring grid position where the component pin exists is calculated from the component arrangement information and the relative coordinates of the component pin. Then, the hole information 43 of the component pins and the pad information 44 are set in the wiring grid. In addition, the wiring prohibition flag 46 is set at a wiring grid point where wiring cannot be performed due to the presence of the holes or pads of the component pins. In addition to this, the via usable position previously determined by the board designer and registered in the board library file 25 is taken out, and the via settable flag 47 is set in the wiring grid at that position.

After the preprocessing is finished, the actual search is started.

First, one pin pair to be connected is taken out (step 101). Next, while avoiding the grid point where the wiring prohibition flag 46 of each wiring grid point is set, it is searched whether or not the adjacent wiring grid in the horizontal and vertical directions can be reached (step 1).
02). Then, the search result is determined, and if the search is successful, the process directly proceeds to step 105 (step 10
3). On the other hand, if it was not successful, it is further diagonally 4
The search for the direction is executed (step 104), and if the adjacent wiring grid can be reached, the process proceeds to step 105. It should be noted that if the adjacent grid point cannot be reached even by the diagonal search, the route is excluded from the candidates.

In the search for the wiring route performed here, the above-mentioned wiring prohibition flag 46 is referred to, and
When using a via because wiring cannot be done unless the wiring layer is switched, via setting flag 4 of the wiring grid
See 7. If the route search is successful, the wiring pattern and via for connecting this route are also patterned.
Wiring information, hole information, and pad information, which are additionally set, and a wiring prohibition flag 46 is added to a wiring grid that cannot be used for other wiring due to the wiring pattern and vias.
Set.

In step 105, it is determined whether the reaching point matches the goal point, that is, whether the pin pair is connected. If the goal point is not reached yet, the process returns to step 102, and the same processing (steps 102 to 105) is repeated from the arrival point until the goal point is reached.

After the wiring pattern is thus determined, the wiring grid information on the side of the wiring pattern is extracted (step 106), and it is determined whether or not there is a via or a via possible flag at that point (step 107). ). If there is no via or the like, the process directly proceeds to step 109, but if there is the via or the like, the straight line wiring pattern is bypassed (step 108), and then the process proceeds to step 109. The detour process is performed by the pad information 44 and the hole information 43 described above.
This is performed with reference to the via settable flag 47, and at least one other wiring pattern can be formed between the grid point where the via or the like exists and the bypassed wiring pattern. To do so.

In step 109, the processing (step 1
06 to 108) is performed for all wiring grids on the side of the wiring pattern. As a result, if completed,
Go to step 110. On the other hand, if it has not been completed, the process returns to step 106, and the same processing (step 106-
108) is repeated.

In step 110, it is determined whether or not all the processes described above (steps 101 to 109) have been performed for all pin pairs. Then, if there is a pin pair that has not been processed yet, the processing returns to step 101 and the same processing (steps 101 to 109) is repeated. On the other hand, if the processing has been completed for all the pin pairs, the unnecessary bypass portion is shaped (step 111). The shaping process of the bypass portion will be described.

When the wiring of all pin pairs is completed, there are the following two unnecessary detour patterns.

(1) The wiring route beside the via was secured by the detour of the adjacent wiring pattern. However, the wiring around the via was not so congested as a result, so that the wiring route beside the via was obtained. -When the wiring is finished without using the gate (when the state of FIG. 5C exists after the wiring is completed).

(2) By circumventing the wiring pattern around the via-possible position, an area where the via can be used is secured, but there are many other via-possible positions around it, or The wiring was not so congested that it had to be used, and the wiring ended without using that point as a via (Fig. 8
(When the states of (c) and (d) exist).

Since these unnecessary detour patterns unnecessarily increase the wiring pattern length, pattern shaping is performed to restore the original straight line pattern. This process sequentially refers to the wiring grid, and if there is a via (composed of holes and pads) or a via possible flag (actually, no via is formed) at that point, If there is an unnecessary detour, refer to the lattice pattern information of
This is done by returning the pattern to a straight line.

When the shaping process of the unnecessary detour process is completed, the automatic wiring process is ended. Then, the process proceeds to step 33 in FIG. 3 to interactively determine what to do with the wiring that could not be wired in the automatic wiring process.

A specific example of the search will be described with reference to FIG.

For simplicity, it is assumed that the start point S51 and the goal point G51 in FIG. 5A are wired.
In this figure, the crosses represent grid points where the wiring prohibition flag 46 is set, that is, grid points where wiring is prohibited.

In the route search, the number of routes obtained is not limited to one, and a plurality of routes may be obtained (usually, there are a plurality of routes). One of the routes is shown in FIG. In this route (see FIG. 6), only the search in the horizontal and vertical directions is performed and S
51 and G51 are connected successfully. The processing performed up to this point corresponds to the processing of steps 102 to 105 in FIG.

After the wiring pattern 510 of FIG. 5B is tentatively determined by the search shown in FIG. 6, the lattice data of the lattice on the side of the wiring route is then referred to and the via pattern or the like is used. Check the existence. Discovering Via 501
The wiring pattern beside the via 501 is bypassed. As a result, the wiring pattern 520 of FIG. 5C is obtained. Note that these processes correspond to the processes of steps 106 to 108 in FIG.

FIG. 7 shows how the start point S52 and the goal point G52 are further wired after this. In this wiring route search, the route cannot be found only by the horizontal and vertical route search at the grid points 71 and 72, and the route is not found until the diagonal search (corresponding to step 104 in FIG. 1) is performed. There is. The connection between S52 and G52 is successful. The wiring determines the wiring pattern 530 of FIG. 5D.

When the detouring process is not carried out by these processes, the component pins 502, 50 as shown in FIG.
Between the via 3 and the via 501, a portion where only one wiring can pass can be passed through two wirings as shown in FIG. 5D.

Further, in this embodiment, the via enable flag is used, and the wiring pattern around the position where the via enable flag is located is bypassed so that the channel can be used more effectively. A specific example of this processing will be described with reference to FIG.

In this case, the start point S81 in FIG.
And the goal point G81 is assumed to be wired. At the grid point 801, the via settable flag 47 is assumed to be set.

First, the maze wiring process (step 102 in FIG. 1).
(Corresponding to ~ 105), a wiring pattern 810 shown in FIG. 8B is obtained. Next, with reference to the grid data of the grid points on the side of the wiring pattern 810, the state of the via enable flag for each grid point is confirmed. Then, when it is confirmed that the via possible flag is set at the grid point 801,
By circumventing the wiring pattern on the side of the grid point 801, FIG.
A wiring pattern 820 of is obtained. Also, the start point S82
The wiring pattern 821 of FIG. 8D is obtained by performing the same processing for the goal point G82.

As a result, it is possible to ensure the use of the via at the point that the via possible flag is present. Therefore, even after the wiring patterns 820 and 821 are determined, the wiring pattern 830 (FIG. 8) having vias connected to other layers at the end points.
(See (e)) can be set.

As described above, in the above embodiment, the search is preferentially performed only in the horizontal and vertical directions.
The amount of calculation processing was reduced, and the overall processing speed could be increased.

When determining the wiring pattern, the state of the grid points beside the pattern is also taken into consideration to some extent, and the wiring pattern is determined.
The wiring can be made more efficient by performing a correction process such as bypassing the cable. Further, by making a detour, it is possible to provide a wiring with some margin around the via, and the number of times of re-searching is reduced. Therefore, the processing speed can be increased.

In the above embodiment, the detouring process is performed every time one wire is wired, but in addition to this, the automatic wiring is divided into a plurality of phases, and after one phase is completed, that phase is terminated. There is also a method in which detour processing is collectively performed on all the patterns wired in step 1 to prepare for the wiring in the next phase.

[0070]

According to the present invention, it is possible to perform wiring at a high speed by effectively using channels in a multi-channel substrate.

[Brief description of drawings]

FIG. 1 is a flowchart showing a flow of processing of automatic wiring according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a printed circuit board design system for carrying out the present invention.

FIG. 3 is a diagram showing a design process of a printed circuit board.

FIG. 4 is an explanatory diagram showing an example of lattice data.

FIG. 5 is an explanatory diagram showing a specific example of wiring pattern determination (a detour around a via).

FIG. 6 is an explanatory diagram showing an execution process (horizontal and vertical direction search) of the maze method wiring according to the present embodiment.

FIG. 7 is an explanatory diagram showing an execution process (oblique direction search) of the maze method wiring according to the present embodiment.

FIG. 8 is an explanatory diagram showing a specific example of wiring pattern determination (a detour around a via position).

FIG. 9 is an explanatory diagram showing a state where passage is prohibited.

[Explanation of symbols]

 101-111 ... Automatic wiring processing step 21 ... Central processing unit 22 ... Terminal 23 ... Logical connection information file 24 ... Component library file 25 ... Board library file 26 ... Printed circuit board design file 31 ... Component placement 32 ... Automatic wiring 33 ... Dialog Wiring 34 ... DRC (Design Rule Check) 35 ... Manufacturing data output 41 ... Printed circuit board 42 ... Wiring grid 43 ... Hole information 44 ... Pad information 45 ... Pattern information (8 directions) 46 ... Wiring prohibition flag 47 ... Via settable flag 501 ... Vias 502 to 505 ... Component pins 506 to 508 ... Existing wiring pattern 801 ... Via available flag 802 to 805 ... Component pins 806, 807 ... Existing wiring pattern

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Noboru Otani 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Ltd. Information & Communication Division

Claims (8)

[Claims] 1. A wiring method for a printed circuit board, wherein a wiring pattern is preliminarily bypassed in the vicinity of a wiring restricted area where the formation of a wiring pattern is prohibited. 2. The wiring restricted area is an area in which it has been determined that a via or a pin of a component is to be arranged, and / or an area in which it is predetermined to maintain the via in a settable state (hereinafter, referred to as: The wiring method according to claim 1, wherein the wiring method is a “via-settable area”. 3. The detour is performed at an interval between the detoured wiring pattern and the wiring restricted area so that at least one other wiring pattern can be formed. The wiring method according to claim 1, wherein: 4. After deciding the arrangement positions of all vias, for a via-possible region portion where no vias are actually provided, a detoured wiring pattern near the via-possible region is shaped. The wiring method according to claim 2. 5. Even after all the wiring patterns have been determined, if there is still an area in which another wiring pattern can be formed between the detoured wiring pattern and the restricted area, The wiring method according to claim 3, wherein the wiring pattern is shaped so that the length of the bypassed wiring pattern is shortened. 6. A route search method using a maze method used in a printed circuit board design system, wherein a route search is first performed in four horizontal and vertical directions, and only four diagonal directions are obtained when the process does not proceed in the four directions. Wiring method characterized by performing route search. 7. A structure comprising: a substrate divided by a predetermined grid, and storing means for storing grid data for each grid point; and searching means for searching a wiring route while referring to the grid data. In the printed circuit board design system described above, the lattice data is configured to include information indicating a wiring restricted area in which it is prohibited to form a wiring pattern, and the searching means includes a vicinity of the wiring restricted area. In
A printed circuit board design system characterized in that the wiring pattern is bypassed in advance. 8. A printed circuit board design system for performing a route search using a maze method, wherein a board is divided by a predetermined grid, and storage means for storing grid data for each grid point and the grid data are provided. A printed circuit board design system comprising: a search unit that first performs a route search in four horizontal and vertical directions, and further performs a route search in four diagonal directions when the process does not proceed in the four directions. ..