JPH05233455A - Automatic write-back cycle generation cache device - Google Patents

Abstract

PURPOSE:To prevent the processing performance of a processor from decreasing by automatically generating a write-back cycle at the timing where a common memory bus is not used. CONSTITUTION:A memory bus monitor 11 once confirming that no user uses the common memory bus informs a bus control part 13 that a common memory access request is possibly generated. At the same time, the monitor 11 picks up a line in a corrected state which is not high in the frequency of access from the processor for an M-line memory 7. At this time, the memory 7 informs the control part 13 that there is no line in the corrected state unless there is the line in the corrected state in the memory. When, however, the memory 7 confirms that there is the line in the corrected state in the memory, an indication for updating the state of a status memory 8 for a corrected line from the corrected state to an uncorrected state is sent to the control part 3 so as to carry out the write-back cycle of the line in the corrected state.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a cache device of an information processing device,
In particular, the present invention relates to a write-back cache device that operates by a write-once protocol in a system that constitutes a multiprocessor.

[0002]

2. Description of the Related Art Generally, in a write-back type cache system, when data for that address is held in the cache memory at the time of write access,
The write data at the time of write access is written to the cache memory, but not to the shared memory. Therefore, the data in the cache for the same address may be different from the data in the shared memory. In the write-back cache system, a write-back cycle is executed as a means for eliminating this different state of data.

The write-back cycle that occurs in the conventional write-back cache system has the following states.

1. When a replacement (replacement) request is issued to a data block (hereinafter referred to as a modified state) indicating that the data in the cache memory is different from the memory contents.

2. When it is confirmed that the address for the shared memory address access being executed by another bus owner is the access for the modified line.

3. When there is a modified line in the cache memory for the flush request executed by the processor.

When the above-mentioned condition occurs, the cache memory control device issues a write access to the shared memory regardless of the cycle issued by the processor. In a multi-processor system in which multiple processors and shared memory are connected by a shared memory bus, shared memory access is used as a means of reducing the frequency in order to reduce bus traffic on the shared memory bus and improve system performance. , The above-mentioned multiple processors are equipped with a high hit rate cache.

However, as the cache hit rate increases, many modified lines are held in the cache memory, causing a write-back cycle (replace or flush process) caused by the processor itself or sharing with other processors. The frequency of write-back cycles caused by memory access increases.

As a result, the bus occupation time of the shared memory bus required for shared memory access becomes long, and the processor's own cycle is often interrupted by a write-back cycle caused by the shared memory access of another processor. Occurs and reduces the processing performance of the processor.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic write back cycle generation cache device which does not deteriorate the processing performance of a processor.

[0011]

An automatic write-back cycle generation cache device according to the present invention comprises a host control unit for controlling an interface with a processor, a cache memory for storing cached data, and a tag memory for storing an address of the data. , A status memory that stores the state of the data, a bus control unit that controls the interface between the internal address bus and the memory bus, a bus snoop control unit that monitors the cycles on the memory bus, and a write back request A write-back buffer for storing data, an address buffer for storing an address for the data requested by the write-back buffer, each of the memories, an address comparator,
A write-back buffer, a memory controller for controlling the address buffer, a host address bus driver,
A memory bus monitor that constantly monitors the bus traffic of the host data bus driver, memory address bus driver, memory data bus driver, and shared memory bus to recognize that idle time has occurred, and the modified state data and address that the cache memory holds. And a modified line memory for storing

[0012]

The present invention will now be described in more detail with reference to the drawings showing one embodiment of the present invention.

Referring to FIG. 1, in one embodiment of the present invention, the host controller 2 controls the interface with the processor 1. The memory controller 3 has four memories 4,
It controls 5, 7, and 8, the address comparator 6, and the two buffers 9 to 10.

The cache memory 4 stores the cached data. The tag memory 5 stores the address of the cached data. The address comparator 6 compares the address on the address bus with the output of the tag memory 5.

The M line memory 7 stores the data in the correction state held by the cache memory 4 and the address for the data. The status memory 8 stores the status of the cached data. The address buffer 9 stores the address when executing the write back cycle. The write-back buffer 10 stores the data when executing the write-back cycle.

The memory bus monitor 11 constantly monitors the bus traffic of the shared memory bus and recognizes that an idle time has occurred. The bus snoop controller 12 monitors the cycle on the memory bus. The bus control unit 13 controls the interface with the memory bus. The host address driver 14a is located between the processor 1 and the internal address bus 16b, and controls the drive of the address bus.

The host data driver 14b is located between the processor 1 and the internal data bus 16a and controls the drive of the data bus. Memory address driver 1
5a is located between the shared memory and the internal address bus 16a and controls the drive of the address bus. The memory data driver 15b is located between the shared memory bus and the internal data bus 16b, and controls the drive of the data bus.

The host address bus 17a is the processor 1
Connected to the address bus. Host data bus 1
7b is connected to the data bus of the processor 1. The host control signal 17c is connected to the control signal of the processor 1. 18a is a shared memory address bus, 18b is a shared memory data bus, and
Reference numeral 8c is a shared memory control signal.

The processor 1 executes a read access to the shared memory, and the read access is performed by the address comparator 6.
If the comparison result indicates a cache mishit, the bus control unit 13 starts a memory read access to the shared memory by a signal from the host control unit 2 and the memory control unit 3. At the same time, the memory read access of the memory is a cache fill read access, and the value of the status memory corresponding to the area of the cache memory that stores the data to be cache-filled is in the modified state indicating "modified the data of the shared memory". When the memory control unit 3 confirms that there is, the memory control unit 3 reads the modified data from the cache memory 4, and the write-back buffer 1
In addition to storing the data in 0, the address corresponding to the data in the modified state is read from the tag memory 5 and stored in the address buffer 9.

The bus control unit 13 finishes the cycle on the shared memory, and at the same time, the host control unit 2 notifies the processor 1 of the completion of the cycle. At this time, the memory control unit 3 requests the shared memory bus access to the bus control unit 13 in order to perform the write-back cycle regardless of the cycle of the processor 1. The address is driven from the address buffer 9 and the write data is driven from the write back buffer.

When the processor executes the flash instruction, it informs the memory controller 3 and the bus controller 13 that the cycle of the host controller 2 is due to the flash instruction. The memory control unit 3 checks the address in the correction state from all the data in the status memory 8, reads the address of the data in the correction state from the tag memory 5, stores it in the address buffer 9, and writes the data in the correction state. Stored in the back buffer 10. The bus control unit 13 acquires the shared memory bus and starts write access to the shared memory.

The write address is driven from the address buffer 9, and the write data is driven from the write buffer. At this time, the memory control unit performs the same processing again, and generates a write back cycle until the status memory 8 has no data in the modified state.

When another processor is executing the shared memory access cycle as the bus owner of the shared memory, the bus snoop control unit 12 controls the memory address driver 15a of the address performing the shared memory access, and the shared memory address bus 18a. Drive to the internal address bus 16a. At the same time, the bus snoop control unit 12 notifies the memory control unit 3 that another bus owner is accessing the shared memory.

The memory control unit 3 includes an address comparator 6
It is determined from the comparison result and the value of the status memory 8 that the shared memory access by another bus owner is an access to the line in the modified state, the line in the modified state is stored in the write-back buffer 10, and the bus control unit 13 The write back buffer is driven to drive the data on the shared memory bus.

The memory bus monitor 11 constantly monitors the bus traffic of the shared memory. Memory bus monitor 11
After confirming that there is no user of the shared memory bus, informs the bus control unit 13 that a shared memory access request may be issued. At the same time, the memory bus monitor 11 causes the M line memory 7 to pick up a line in a modified state that is not frequently accessed by the processor. At this time, the M line memory 7 informs the bus control unit 13 that there is no modified state line when there is no modified state line in the memory, and that there is no shared memory bus access request.

However, when the M line memory 7 confirms the corrected line in the memory, the state of the status memory 8 for the corrected line is changed to the memory control unit 3 in order to perform the write-back cycle for the corrected line. Instruct to update from the modified state to the unmodified state. The M line memory 7 stores the data of the modified line in the write back buffer 10 and the address for the data in the address buffer 9. The M line memory 7 requests the bus control unit 13 to perform write back access to the shared memory bus.

The bus controller 13 drives the write address from the address buffer 9 and drives the write data from the write back buffer 10. The memory bus monitor 11 confirms that the shared memory bus is empty,
If the M-line memory 7 confirms the modified line in the memory, the write-back cycle is automatically generated again for the modified line regardless of the processor cycle, and the line is executed until the modified line disappears. It

In the embodiment described above, the M line memory 7
Recognizes the presence / absence of a modified line by using it as a memory that stores only the modified line address and data, but is not limited to this, the status It can be recognized by searching the contents of the memory 8.

[0029]

As described above, according to the present invention,
By automatically issuing a write-back cycle when the shared memory bus is not used, the frequency of write-back cycles that occur during replacement and bus snooping is reduced, and the write-back cycles that occur at this time can reduce shared memory access. It is possible to prevent deterioration of response time.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 processor 2 host control unit 3 memory control unit 4 cache memory 5 tag memory 6 address comparator 7 M line memory 8 status memory 9 address buffer 10 write back buffer 11 memory bus monitor 12 bus snoop control unit 13 bus control unit 14a host address driver 14b Host data driver 15a Memory address driver 15b Memory data bus driver 16a Internal address bus 16b Internal data bus 17a Host address bus 17b Host data bus 17c Host control signal 18a Shared memory address bus 18b Shared memory data bus 18c Shared memory control signal

Claims (3)

[Claims] 1. A host control unit for controlling an interface with a processor, a cache memory for storing cached file data, a tag memory for storing an address of the data, and a status memory for storing a state of the data. A bus control unit that controls an interface between the internal address bus and the memory bus, a bus snoop control unit that monitors a cycle on the memory bus, a write back buffer that stores data when a write back request occurs, and the write back unit. An address buffer that stores an address for data for which a buffer request has occurred, a memory control unit that controls each of the memories, the address comparators, the write-back buffer, and the address buffer, a host address bus driver, a host data bus driver, and a memory controller. Memory bus monitor, memory data bus driver, memory bus monitor that constantly monitors the bus traffic of the shared memory bus to recognize that an idle time has occurred, and a modified line that stores the data and address of the correction state held by the cache memory An automatic write-back cycle generation cache device having a memory. 2. A host controller that controls an interface with a processor, a memory controller, a cache memory that stores cached data, a tag memory that stores an address of the cached data, and an address bus. An address comparator that compares the address with the output of the tag memory, a modified line memory that stores the modified state data that the cache memory holds and the address for the data, a status memory that stores the state of the cached data, and a write The address buffer that stores the address when executing the back cycle, the write back buffer that stores the data when executing the write back cycle, and the bus traffic of the shared memory bus are constantly monitored to check if there is any free time. Is located between the processor and the internal address bus, the bus bus snoop controller that monitors the cycles on the memory bus, the bus controller that controls the interface with the memory bus, The host address driver that controls the drive, the host data driver that is located between the processor and the internal data bus, the host data driver that controls the driver of the data bus, and the host address driver that is located between the shared memory and the internal address bus An automatic write-back cycle generation cache having a memory address driver for controlling the drive of the data bus and a memory data driver located between the shared memory bus and the internal data bus for controlling the drive of the data bus. apparatus. 3. The automatic write back cycle generation cache device according to claim 1, wherein the contents of the status memory are searched.