JPH0962580A - Multi-processor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the degradation in use efficiency of a cross coupling network by maintaining the consistency of data blocks existing in each cache memory based on issue of a prescribed instruction at the time of issue of this instruction from the processing of each processor. SOLUTION: Cache units 11 and 21 are connected to a main storage unit 12 and a bus arbiter 16. Cache units 11 and 21 update data entries of data blocks in units themselves or reflect them on the main storage unit 12 based on requests of processors and snoop the address information or the like flowing on a local bus 15 to execute the operation of cache consistency maintenance or the like. The bus arbiter 16 arbitrates the use right of the local bus 15. When the processing of each of processors 10 and 20 issues the prescribed instruction, the consistency of data blocks existing in each cache memory is maintained based on this instruction issue.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor device, and more particularly to a multiprocessor device in which each processor has a cache.

[0002]

2. Description of the Related Art In a parallel computer system, a cache memory is often attached to each processor in order to respond to an access request issued from a processor to a main memory at high speed and to reduce traffic of an interconnection network. . The memory access issued from each processor is performed via the cache memory (and the cache memory controller), and a copy of the data block of the memory access is placed in the cache memory.

In a parallel computer system, a situation may occur in which multiple copies of the same data block exist in multiple cache memories, but various methods have been devised in order to guarantee the consistency between the copies. -It has been realized.

The snoop method is generally used in a parallel computer system using a bus such as a bus capable of monitoring all transactions in a connection network connecting processors or processors and main memories to each other. In the snoop method, the cache memory monitors all transactions issued on the connection network, and if a copy of the data block to be transacted exists in its own cache memory, the necessary coherency maintenance operation is performed. It is something to give.

A directory system is used in a parallel computer system in which it is difficult to monitor all transactions in a connection network interconnecting processors and processors / main memories. The directory method stores and manages, in a storage device called a directory, caching information indicating in which cache memory the copy exists in each data block unit or similar unit, and the cache information from the processor is stored. When a transaction is issued, the occurrence of a transaction is notified to the cache memory having a copy of the transaction target data block based on the caching information obtained from the directory, and the consistency is maintained between the copies.

[0006]

Conventionally, the operation for maintaining the consistency among the copies existing in a plurality of cache memories in a parallel computer system has been performed for each transaction as described above. However, this is incompatible with the loose memory consistency model that has been devised / implemented in various ways to reduce the access latency to the memory.

Generally, in the loose memory consistency model, it is required to set a synchronization point in the process of processing and, when the processing reaches the synchronization point, reflect the memory transaction issued so far in the system. ing. This means that it is not necessary to reflect the outcome of each memory transaction prior to the sync point. In other words, when a conventional cache coherency retention method is used in a parallel computer system that adopts a loose memory consistency model, a coherency retention operation that is unnecessary at that point will be entered for each transaction,
It can be said that the overhead carelessly increases the memory access latency, contrary to the purpose of the loose memory consistency model.

However, the implementation of the cache coherency operation is performed in a memory-consistent model with memory
In a system that reduces the overhead of unnecessary cache coherency behavior by delaying to the point of the sync point where it is necessary to reflect the transaction, the cache coherency behavior is intensive at the time of the sync point. Therefore, the traffic is intensively generated on the interconnection network at the time of the synchronization point, and as a result, the utilization efficiency of the interconnection network may be extremely reduced.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and delays the execution of the cache coherency holding operation until a convenient time, for example, to loosen memory consistency. In the model system, avoiding the decrease in utilization efficiency of the interconnection network due to the concentration of traffic on the interconnection network at the synchronization point,
It is intended to provide a multiprocessor device having higher performance.

In order to solve this problem, for example, the present invention has the following configuration. That is, in a parallel computer system including a plurality of processors, a cache memory attached to them, a main storage device, and a connection network interconnecting the cache memory and the storage devices, each processor process issues a predetermined instruction. When this is done, the data block existing in each cache memory is kept consistent based on the issue of the instruction.

According to a preferred embodiment of the present invention,
Consistency retention is an identification means for identifying that a memory transaction issued from each processor is a memory transaction for a data block that may be shared in another cache, and the shared data block. Holding means for holding that the data block in the cache stored by the executed memory transaction is a shared data block, and a data block for performing a coherency holding operation using the information held by the holding means. It is desirable to have a selecting means for selecting. As a result, the processor performs the consistency maintaining operation in the system only on the shared data block at a predetermined stage.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of a system for realizing the present invention. In the figure, 10 and 20 are processors, which are connected to the cache units 11 and 21 via processor buses 14 and 24, respectively.

The processor 10 can issue multiple memory accesses, and
Special instructions to complete the access with a data consistency guarantee with a loose memory consistency model
(Synchronization command).

Further, the processor 10 has a special instruction (hereinafter referred to as a shared data block access start instruction) for declaring that a memory access to a shared data block (for example, a data block read and written in a critical section) is started, and a shared instruction. A special instruction that declares the end of a memory access to a data block
(Hereinafter referred to as shared data block access end instruction), and these instructions are executed by the processor control bus 143 (described later)
However, the mechanism for clearly indicating the start and end of memory access to the shared data block and the non-shared data block is not limited to this embodiment. Further, the shared data block access start instruction secures an exclusive right to use the shared data block, and the shared data block access end instruction releases an exclusive right to use the shared data block. Both the data block access start instruction and the shared data block access end instruction require notification of completion to the main memory unit.

The cache units 11 and 21 are connected to the main memory unit 12 and the bus arbiter 16 via the local bus 15, respectively. Further, the cache units 11 and 21 update the data entry of the data block inside the cache units 11 and 21 and / or the main storage unit 12 based on the request of the processor.
And the like, and also snoops the address information and the like flowing on the local bus 15 to carry out operations such as cache coherency retention. The bus arbiter 16 is for arbitrating the right to use the local bus 15. In this embodiment, a multiprocessor system configuration connected to the shared bus is taken as an example, but these configurations are not limited to this embodiment.

In the present embodiment, the consistency control adopting the loose memory consistency model is performed so that the consistency of the data block is guaranteed at the time of issuing the synchronous instruction explicitly given from the processor. In the information processing system configured as shown in (1), the cache control sequencer that controls the cache coherency operation operates as follows: (1) An instruction to start memory access to a shared data block (shared data block access start instruction) is issued from the processor. When issued, sets the shared data block access flag until the processor issues an instruction to end the memory access to the shared data block for the subsequent memory access (shared data block access end instruction). .

(2) State in which the value is not reflected in the main memory
It is determined whether the cache data block in the (DIRTY state) is a shared data block, and the write-back process to the main memory of only the shared data block at the time of issuing the synchronization command, and the coherency maintenance operation if necessary. Run.

By performing the operation described above, it is possible to prevent the write-back processing traffic to the main memory, which occurs intensively at the time of issuing the synchronous instruction, and the consistency maintaining operation / traffic for the non-shared data block from occurring. ing.

FIG. 2 is a diagram showing the structure of a cache unit which is a part of this embodiment. Although the cache unit 11 is taken as an example in FIG. 2, the cache unit 21 also has a similar configuration.

In the figure, 144 is a processor address bus 1.
41 is a processor address bus interface for connecting to 41, 145 is a processor data bus interface for connecting to the processor data bus 142, and 146 is a processor control bus interface for connecting to the processor control bus 143.

154 is a local address bus 15
1 is a local address bus interface for connecting with 1, and 155 is a local data bus interface for connecting with the local data bus 152.
Reference numeral 56 is a local control bus interface for connecting to the local control bus 153.

Reference numeral 115 is a data entry for holding data, 112 is an address tag for holding the address of the data entry 115, 113 is a status flag for holding the status of the data entry 115, Reference numeral 114 is a shared data block flag for holding whether or not the data entry 115 is a shared data block. These parts are assumed to be a set of storage elements such as SRAM, but this is not limited to the present embodiment.

Reference numeral 116 denotes the contents of the address tag 112, the processor address bus 141, and the local address bus 15.
It is a comparator that compares the address on 1. Also, 117
Is a selector for selecting the data in the data entry from the comparison result of the comparator 116.

Further, in the figure, reference numeral 118 denotes a shared data block access flag which indicates that the processor 10 is accessing the shared data block, which is set when the shared data block access start instruction issued from the processor 10 is completed. It shall be reset when the shared data block access end instruction issued from the processor 10 is completed.

Reference numeral 111 is a cache control sequencer for controlling each module in the cache unit.

In the present embodiment, the cache unit has a 2-way set associative structure of 256 bytes per cache line and 16 cache lines per set, but these structures are the same as those of the present embodiment. It is not limited.

FIG. 3 shows the relationship between the address tag 112, the status flag 113, the shared data block flag 114, and the data entry 115 in the cache unit 11, and the address field at the time of address comparison.

In the figure, 32-bit address 0x
f8000701 (0x indicates a hexadecimal number) is the processor address bus 141 or the local address bus 151.
Describes how the address comparison is done when passed from.

In this embodiment, since the cache unit has a 2-way set associative structure of 256 bytes per cache line and 16 cache lines per set, the address tag 112
Has a field of 20 bits, an index used to select a cache line is 4 bits, and an offset designating the position of a data block in the cache line has an 8-bit field. The lower 8 bits of the passed address are an offset field that specifies the location of the data block within the cache line. The upper 20 bits of the passed address are an address tag field and are compared with the address tag 112. The part of the passed address excluding the offset field and the address tag field is an index field, and specifies the position of the cache line in the set.

The comparator 116 stores the value stored in the address tag of the cache line designated by the index field and the upper two addresses of the address passed from the processor address bus 141 or the local address bus 151.
Compare with 0 bit. The above comparison results are in agreement,
And, if the status flag of the cache line specified by the index field (details of the status of the status flag is described later) is in the valid status (CLEAN or DIRTY), it is considered as a cache hit (if the transaction is READ, the cache is hit).・ In the case of read hit, WRITE is called cache write hit). If it is not a cache hit, it is considered as a cache miss.
EAD is called a cache read miss, and WRITE is called a cache write miss).

In FIG. 3, address 0xf80007.
Since the offset field of 01 is 0x01, the offset in the cache line is 1. The index field of address 0xf8000701 is 0x7
Therefore, the cache line index in the set is 7. The address tag field of the address 0xf8000701 is 0xf8000,
The address tag stored in the line index 7 is compared.

FIG. 4 is a state transition diagram of the state flags at the time of executing each memory transaction (hereinafter described as the state flag of the cache unit 11).
In FIG. 4, the status INVALID indicates that the data entry managed by the status flag is invalid. Condition CLEAN
Indicates that the data entry managed by the status flag has never been rewritten after being loaded from the main memory unit. However, although the same value as the main storage unit is stored in the data entry, the latest value may be stored in the data entry of another cache unit. The status DIRTY is 1 after the data entry managed by the status flag is loaded from the main storage unit.
Indicates that the value has been rewritten with the latest value more than once and the value is not reflected in the main memory. The latest value is stored in the data entry. The transition conditions from each state are as follows.

(1) When a LOAD instruction is issued from the processor 10 to a data block in the INVALID state,
The status flag transits to CLEAN.

(2) When the STORE instruction is issued from the processor 10 to the data block in the INVALID state, the cache read hit process is executed once, the state flag transits to CLEAN, and then the cache write hit process is executed. It is executed and the status flag transits to DIRTY.

(3) When the LOAD command is issued from the processor 10 to the data block in the CLEAN state, the state flag transits to CLEAN.

(4) When the STORE command is issued from the processor 10 to the data block in the CLEAN state,
The status flag transits to DIRTY.

(5) When the consistency maintaining operation is executed on the data block in the CLEAN state, the state flag is IN
Transition to VALID.

(6) When the LOAD instruction is issued from the processor 10 to the data block in the DIRTY state, the state flag transits to DIRTY.

(7) The status flag issued by the processor 10 for the STORE instruction for the data block in the DIRTY state transits to DIRTY.

(8) When the processor 10 issues a synchronization command to a data block in the DIRTY state, the state flag transits to CLEAN.

(9) When the write-back process to the main memory is executed for the data block in the DIRTY state, the state flag transits to CLEAN.

(10) When the consistency maintaining operation is executed for the data block in the DIRTY state, the state flag is
Transition to INVALID.

FIG. 5 shows a control procedure at the time of executing the LOAD instruction (hereinafter, it is assumed that the LOAD instruction is issued from the processor 10).

In FIG. 5, address comparison is performed for the LOAD instruction issued from the processor 10 (step S
1) If a cache read hit occurs, the cache unit 11 supplies the data block stored therein to the processor 10 (step S2).

LOAD issued from the processor 10
When an address comparison is performed on the instruction and a cache read miss occurs, the cache unit 11 issues a read request to the local bus 15 (step S).
3). In this case, the cache unit 11 does not supply the data block to the processor 10 until the cache read missed data block is supplied to the cache unit 11. Cash unit 1
1 transfers the address of the read access to the local address bus 151, issues a read request to the local control bus 153, and services the consistency maintaining operation until a data block is supplied to the local data bus 152. Also, the service for the access request from the processor is stopped, but this is not limited to the present embodiment. The main memory unit 12 receives the read request and the address of the read access and supplies a data block to the local data bus 152 (step S4). The cache unit 11 replaces the data block supplied to the local data bus 152 with the entry of the data block in the cache unit 11, and sets the status flag 113 of the data block to CLEAN (step S5). When the shared data block access flag 118 is set, the shared data block flag 114 of the data block in the cache unit 11 is set. When the shared data block access flag 118 is reset, the shared data block flag 114 of the data block in the cache unit 11 is reset. The cache unit 11 supplies the data block to the processor 10 (step S6).

Next, the control procedure for executing the STORE instruction will be described with reference to FIG. 6 (hereinafter, the STORE instruction will be described as issued from the processor 10).

In FIG. 6, address comparison is performed on the STORE instruction issued from the processor 10 (step S10), and if a cache write hit occurs, the status flag of the data block is set to the DIRTY status (step S12). , 13). Issued from processor 10
Performs address comparison for the STORE instruction and caches
When a write miss occurs, the cache write hit process is performed after the cache read miss process (step S11).

FIG. 7 shows a control procedure at the time of executing the synchronous instruction (hereinafter, it is assumed that the synchronous instruction is issued from the processor 10).

In the figure, the shared data block flag 114 is set in the cache unit 11, and
When there is one or more data blocks in the DIRTY state (step S20) and a synchronization instruction is issued from the processor 10, write-back processing to the main memory of the DIRTY block is executed, and the state flag of the data block. To
Set to CLEAN (steps S22 and S23).

In this embodiment, the write-back processing of the DIRTY block to the main memory is repeatedly executed until the DIRTY block is exhausted, but this is not limited to this embodiment.

FIG. 8 shows a control procedure at the time of executing the write-back process to the main memory (hereinafter, it is assumed that the write-back process to the main memory is issued from the cache unit 11).

In FIG. 8, the cache unit 11
Transfers the write-back request source information to the local control bus 153 and the address of the write-back access to the local address bus 151, issues a write-back request to the local control bus 153, A data block to be written back to 152 is supplied (step S30). Then, the written-back data block is supplied to the entry of the main memory unit, and the execution is stopped until the necessary consistency holding operation is completed and the write-back processing to the main memory is completed.

The main memory unit 12 receives the read request, the address of the write-back access, and the data block supplied to the local data bus 152, and reads the entry of the data block. At the same time, if the data copy is also held in the cache unit other than the cache unit 11 in the valid state (CLEAN state or DIRTY state), the cache unit held in the valid state is transferred to the local bus 15. The address to be stored is snooped and the consistency holding operation is executed for the data block held in the valid state (steps S31 to S34).

In this embodiment, the consistency holding operation is an invalidation type transaction, but this is not limited to this embodiment.

FIG. 9 shows a control procedure at the time of executing the data block replacement (hereinafter, the cache unit 11 will be described as the data block replacement).

In FIG. 9, the cache unit 11
When a data block replacement request is issued, the data block replacement algorithm detects a replacement target data block by a data block replacement algorithm such as LRU (step S40).

When the data block to be replaced is in the DIRTY state (step S41), the write-back process to the main memory of the DIRTY block is executed (step S42). If the replacement target data block is in the INVALID state, or if the replacement target data block is in the CLEAN state, or if the replacement target data block is in the DIRTY state and the write-back processing to the main memory is complete, the data of the data block The data block is loaded into the entry (steps S43, 44).

In order to understand the present method, first, an example in which the consistency maintaining operation regarding the memory access to the shared data block, which is a characteristic of the present method, is postponed until the synchronous command issuance is described.

Specifically, for example, the processors 10 and 20
Is a non-shared data block at address f800000
The LOAD instruction is issued to address 0, and after each LOAD instruction is completed, the processor 10 stores STORE to the address f8000000, which is a non-shared data block.
When an instruction is issued, the coherency holding operation is not issued to the cache unit 21 at the time of issuing the STORE instruction and at the subsequent issuing of the synchronous instruction or the shared data block access start instruction, and the memory for the shared data block is issued. -A shared data block access start command is issued to access, and the processor 10 sends an STO to the shared data block at address f8010000.
When the RE instruction is issued, the coherency holding operation is not issued to the cache unit 21 at the time of issuing the STORE instruction, and then the coherency holding operation is executed when the synchronization instruction is issued from the processor 10. How to realize will be described with reference to FIG.

FIG. 10 is a timing chart showing an example of the consistency maintaining operation of this embodiment.

It is assumed that the address f8000000 and the address f8010000 are assigned to the main memory unit 12.

However, before the time 1, the execution of the shared data block access end instruction is completed or the shared data block access start instruction is not executed, and the shared data block access flag 11
8 is in the reset state, and the address f80
It is assumed that neither the address 00000 nor the address f8010000 has been loaded into the cache unit.

At time 1, the processors 10 and 20 issue a LOAD instruction to the address f8000000000, which is a non-shared data block, and the respective LOADs have been completed from the main memory unit 12. At this time, the address f8
Cache unit 11 corresponding to address 000000,
The status flags 113 and 213 of 21 are CLEA, respectively.
N, and the shared data block flag 114 has been reset.

At time 2, the processor 10 addresses the address f800000, which is a non-shared data block.
STORE command is issued and STORE is completed. At this time,
Access to the local bus and consistency maintenance operation do not occur. Since the status flag 113 of the data block in the cache 11 is DIRTY as a result of the STORE instruction issued by the processor 10 and the shared data block access flag 118 is reset, the shared data of the data block Block flag 1
14 is reset.

At time 3, the processor 10 starts memory access to the shared data block,
A shared data block access start instruction has been issued, and the shared data block access start instruction has been completed.

At time 4, the processor 10 sends the shared data block to the address f8010000.
STORE command is issued and STORE command is completed. At this time, access to the local bus and consistency holding operation do not occur. The status flag 113 of the data block in the cache 11 is the STOR issued by the processor 10.
The result of the E instruction is DIRTY, and the shared data block access flag 118 is set by the shared data block access start instruction completed at time 2, so the shared data block flag 114 is set.

At time 5, the processor 10 finishes the memory access for the shared data block, issues the shared data block access end instruction, and the shared data block access end instruction is completed.

At time 6, the processor 10 issues a synchronization instruction.

At time 7, it is a shared data block in which the shared data block flag 114 is set among the data blocks held in DIRTY in the cache 11 by the synchronization instruction of the processor 10 issued at time 6. Write back processing to the main memory at the address f8010000 has occurred. Similarly, the data block at address f8000000 held in the cache 11 at DIRTY is the shared data block flag 11
Since 4 is a reset non-shared data block, write back processing to the main memory does not occur.

<Second Embodiment> Next, a second embodiment will be described. The system configuration, the cache unit configuration and control, etc. are almost the same as those in the first embodiment. Therefore, description will be omitted and only different points will be described.

In FIG. 1, the processor 10 is capable of issuing multiple memory accesses in multiple numbers, and in order to complete the multiple issued memory accesses under the data consistency guarantee based on the loose memory consistency model. However, the processor 10 declares that the memory access to the shared data block is started (shared data block access start instruction) and the shared data block to the shared data block. It shall not have a special instruction (shared data block access end instruction) that declares the end of memory access.

In the second embodiment, instead of the shared data block access start instruction and shared data block access end instruction of the first embodiment, memory access to the shared data block is started at the shared data block access start address. The memory access to the shared data block is declared by storing the value indicating that
The memory access to the shared data block shall be declared to be completed by STORE the value indicating that the access is completed. In addition, the cache unit 11 determines whether the memory access to the shared data block is started or ended by the value stored in the shared data block access start address.
The shared data block access flag 118 is set to STORE with a value indicating that the processor 10 has started the memory access to the shared data block at the shared data block access start address, and the shared data block access start address is set to the shared data block. STORE the value indicating that the memory access is completed
Then, it shall be reset.

In the present embodiment, the consistency control adopting the loose memory consistency model is performed so that the consistency of the data block is guaranteed at the time of issuing the synchronous instruction explicitly given from the processor. In the information processing system having the configuration as shown, the cache control sequencer that controls the cache coherency maintaining operation sets a value indicating that the shared data block access start address starts the memory access to the shared data block.
When the STORE is performed, the shared data block access flag is set until the value indicating that the memory access to the shared data block has been completed is stored in the shared data block access start address for the subsequent memory access. State that does not reflect that value in memory
It is determined whether the cache data block in the (DIRTY state) is a shared data block, and the write-back process to the main memory of only the shared data block at the time of issuing the synchronization command, and the coherency maintenance operation if necessary. By executing it, it is possible to prevent the write-back processing traffic to the main memory, which occurs intensively at the time of issuing the synchronous instruction, and the traffic for the non-shared data block among the consistency maintaining operation / traffic from occurring.

As described above, according to the present embodiment, in the parallel computer system which adopts the loose memory consistency model and is connected to each other by the interconnection network, the cache memory for improving its performance is further improved. By providing a coherency maintenance mechanism for memory and cache memory, and generating traffic on the interconnection network that concentrates at the synchronization point time only for shared data blocks, the utilization efficiency of the interconnection network is reduced. , And the processing overhead associated with the synchronous operation can be reduced, which has the effect of improving the processing capacity of the entire system.

It should be noted that the present invention is characterized by adapting to a plurality of processors (the number of processors is two in the above-mentioned embodiment, but it is of course possible to have more than two), and the system or apparatus can be used for any purpose. It is needless to say that it may be used for the above or a general-purpose computer device.

[0076]

As described above, according to the present invention,
Delaying the implementation of the cache coherency operation until a convenient point in time, and coherency only for shared data blocks, allows, for example, a system with a loose memory consistency model to interact with each other at the point of synchronization. A multiprocessor device having higher performance can be provided while avoiding a decrease in utilization efficiency of the mutual connection network due to concentration of traffic on the connection network.

[0077]

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration around a processor of an information processing system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a cache unit in the embodiment.

FIG. 3 is a diagram illustrating address comparison in a cache unit according to the embodiment.

FIG. 4 is a state transition diagram of state flags of the embodiment.

FIG. 5 is a chart of a process performed by a cache unit when executing a LOAD instruction in the embodiment.

FIG. 6 shows a cache unit STORE in the embodiment.
It is a chart of the processing performed when an instruction is executed.

FIG. 7 is a chart of processing performed by a cache unit when executing a synchronous instruction in the embodiment.

FIG. 8 is a chart at the time of performing write back processing to the main memory in the embodiment.

FIG. 9 is a chart of a process performed when replacing a data block in the embodiment.

FIG. 10 is a diagram showing an example in which a consistency maintaining operation regarding a memory access to a shared data block is postponed until a synchronous command is issued in the embodiment.

[Explanation of symbols]

 10, 20 processor 11, 21 cache unit 12 main memory unit 14, 24 processor bus 16 bus arbiter 15 local bus

Claims (4)

[Claims] 1. In a parallel computer system including a plurality of processors, a cache memory associated with them, a main memory, and a connection network interconnecting the cache memory and the memory, each processor issues a predetermined instruction. When performing, the multiprocessor device is characterized in that the data blocks existing in the respective cache memories are held consistent based on the instruction issuance. 2. The coherency retention means for identifying that a memory transaction issued by each processor is a memory transaction for a data block that may be shared in another cache. Holding means for holding that the data block in the cache stored by the memory transaction identified as the shared data block is a shared data block, and a consistency holding operation using the information held by the holding means 2. The method according to claim 1, further comprising selection means for selecting a data block for executing the method, wherein the processor performs the consistency maintaining operation in the system only on the shared data block at a predetermined stage. Multiprocessor device. 3. The multiprocessor system according to claim 1, wherein the system takes a loose memory consistency model. 4. The multiprocessor device according to claim 2, wherein the shared data block is a data block read and written in a critical section.