JPH0962577A - Method and system for information processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the processing capability of the whole of a system by reflecting a data block in a cache memory on a main memory at the time of attaining the prescribed processing stage of each processor in advance. SOLUTION: Cache units 11 and 21 update the data entries of data blocks in themselves or reflect them on a main storage unit 12 based on requests of processors 10 and 20 and snoop the address information or the like flowing on a local bus 15 to execute the cache maintenance. If the number of data blocks whose values are not reflected on the main storage exceeds a prescribed value after they are rewritten with latest values at the time other than the time of issue of a synchronizing instruction, a cache control sequencer which controls the consistency maintenance operation of caches writes back these data blocks of caches to the main storage unit by write-back processing and performs the consistency maintenance operation if necessary to distribute the traffic.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus in which a plurality of processors having caches operate in synchronization with each other.

[0002]

2. Description of the Related Art In a parallel computer system, a cache memory is often attached to each processor in order to respond to an access request issued from a processor to a main memory at high speed and to reduce traffic of an interconnection network. . The memory access issued from each processor is performed via the cache memory, and a copy of the data block to be the memory access target is placed in the cache memory. In a parallel computer system, a situation may occur in which multiple copies of the same data block exist in multiple cache memories, but in order to guarantee consistency among these copies,
Various methods have been devised / implemented in the past.

The snoop method is generally used in a parallel computer system that uses a bus such as a bus capable of monitoring all transactions in a connection network that interconnects processors and processors and main memory. In the snoop method, the cache memory monitors all transactions issued on the connection network, and if a copy of the data block to be transacted exists in its own cache memory, the necessary coherency maintenance operation is performed. It is something to give.

Further, a directory system is used in a parallel computer system using a coupled network that interconnects processors and a processor / main memory with each other, in which it is difficult to monitor all transactions. The directory method stores and manages, in a storage device called a directory, caching information indicating in which cache memory the copy exists in each data block unit or similar unit, and the cache information from the processor is stored. When a transaction is issued, the occurrence of a transaction is notified to the cache memory having a copy of the transaction target data block based on the caching information obtained from the directory, and the consistency is maintained between the copies.

[0005]

Conventionally, the operation for maintaining the consistency among the copies existing in a plurality of cache memories in a parallel computer system has been performed for each transaction as described above. However, this is incompatible with the loose memory consistency model that has been devised / implemented in various ways to reduce the access latency to the memory. Generally, in the loose memory consistency model, a synchronization point is set in the course of processing, and when the processing reaches the synchronization point, it is obliged to reflect the memory transaction issued so far in the system. This means that it is not necessary to reflect the outcome of each memory transaction prior to the sync point. In other words, when a conventional cache coherency retention method is used in a parallel computer system that adopts a loose memory consistency model, an unnecessary coherency retention operation is entered in each transaction at that time, and the overhead is loose memory.・ Carefully against the purpose of the consistency model
It can be said that access latency is increased.

However, the implementation of the cache coherency operation is performed in a memory-consistent model with memory
In a system that reduces the overhead of unnecessary cache coherency behavior by delaying to the point of the sync point where it is necessary to reflect the transaction, the cache coherency behavior is intensive at the time of the sync point. Therefore, the traffic is intensively generated on the interconnection network at the time of the synchronization point, and as a result, the utilization efficiency of the interconnection network may be extremely reduced.

The present invention has been made in view of the above-mentioned conventional example, and provides a cache memory and a coherency maintaining operation mechanism of the cache memory, and distributes traffic on the interconnection network concentrated at the synchronization point. In this way, it is possible to reduce the utilization efficiency of the interconnection network and to reduce the processing overhead associated with the synchronous operation, and improve the processing capacity of the entire system. The purpose is to provide a method.

[0008]

In order to achieve the above object, the information processing system of the present invention has the following configuration. That is, in an information processing system including a plurality of processors, a cache memory attached to each of them, a main memory, and a connection network interconnecting the cache memory and the main memory, the processing of each processor is at a predetermined stage. When it reaches, the data block existing in the cache memory attached to the processor is reflected in the main memory, and the coherency holding process for holding the consistency of the content of the data block is executed.

Preferably, if the data block existing in the cache memory satisfies a predetermined condition before the processing by the processor reaches the predetermined stage, the data is stored in the cache memory. The present invention is characterized in that an existing data block is reflected in the main memory, and a consistency maintaining process is executed to maintain the consistency of the contents of the data block.

More preferably, the predetermined condition is determined by comparing the number of data blocks whose contents are not reflected in the main memory with a prespecified value.

More preferably, the predetermined condition is determined by comparing the number of times data has been written by the processor with a predetermined value.

More preferably, the information processing system employs a loose memory consistency model.

More preferably, the consistency maintaining process is
This is a process of invalidating a copy of a data block reflected in a main memory from one cache memory and held in a cache memory other than the cache memory.

More preferably, the main memory is connected to each of the plurality of processors, and the cache memory associated with one of the processors is a cache memory of another processor that stores data stored therein.
Detects via the bus that the process of reflecting the block in the main memory has been performed, and executes the consistency maintaining process by invalidating the copy of the corresponding data block stored in the cache memory. To do.

More preferably, the main memory is distributed and connected to each of the plurality of processors, and the main memory is connected to a cache memory each time a data block having its contents is copied. Record the copy destination,
When the process of reflecting the data block stored therein from the one cache memory of the plurality of processors to the main memory is performed, the duplication of the corresponding data block is invalidated based on the record of the duplication destination. By doing so, the consistency maintaining process is executed.

Further, the information processing method of the present invention has the following configuration, that is, it is constituted by connecting a plurality of information processing means, and data is copied from the storage means to the cache means attached to each information processing means. In an information processing system in which the contents of the storage means are shared by the plurality of information processing means, an information processing method of simultaneously writing back the contents of the cache means to the storage means at a predetermined stage, wherein the contents are stored in the storage means Also, a reading step of reading a desired data block into the cache means, a cache updating step of updating the data block read into the cache means by the reading step, and a counting for counting the number of data blocks updated by the cache updating step. Comparing the number of data blocks counted by the step and the counting step with a predetermined value, The updated data block based on compare results, and a step writeback written back to the storage means.

Preferably, the cache means other than the cache means that has been written back detects the write-back of the data block to the storage means by the write-back process, and the write-back target held in the cache means is detected. The method further comprises the step of invalidating the duplication of the data block.

Preferably, a recording step of recording the read destination for each data block read from the main storage means to the cache means in the read step, and a data block in the main memory by the write-back step. When the data block is written back, the method further comprises the step of invalidating the duplication of the data block stored in the read destination cache means recorded by the recording step for the data block.

The computer controller of the present invention has the following configuration. That is, multiple units were connected,
A plurality of computer control devices for reading and controlling a predetermined program from a memory medium, comprising a module of a reading step of reading a desired data block stored in the storage means into a cache means, and a cache means by the reading step. A module for a cache updating step for updating the read data block, a module for a counting step for counting the number of data blocks updated by the cache updating step, a number of data blocks counted by the counting step and a predetermined value. A module for a write-back step of comparing and writing back the updated data block to the storage means based on the comparison result, and a write-back process for writing back the updated data block of the cache means to the storage means all at once And a module for a write back process.

With the above configuration, the write-back is performed when a predetermined number of data blocks are updated even before the cache data blocks are simultaneously written back. Therefore, the write-back of the data blocks is concentrated and the performance is degraded. There is no.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A multiprocessor system will now be described in detail as an embodiment of the present invention with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram showing a configuration of a first embodiment of a system for realizing the present invention.

In FIG. 1, 10 and 20 are processors,
The cache units 11 and 21 are connected via the processor buses 14 and 24, respectively.

In FIG. 2, the processor 10 is capable of issuing multiple memory accesses, and in order to complete the multiple issuing memory access under the data consistency guarantee based on the loose memory consistency model. Shall have a special command (synchronous command).

The cache units 11 and 21 are connected to the main memory unit 12 and the bus arbiter 16 via the local bus 15, respectively. Further, the cache units 11 and 21 update the data entry of the data block inside the cache units 11 and 21 and / or the main storage unit 12 based on the request of the processor.
The cache information is reflected on the local bus 15, and the address information flowing on the local bus 15 is snooped to perform cache maintenance.

The bus arbiter 16 is for arbitrating the right to use the local bus 15.

In the present embodiment, the consistency control adopting a loose memory consistency model that guarantees data consistency at the time of issuing a synchronous instruction explicitly given from the processor is shown in FIG. In an information processing system having such a configuration, the cache control sequencer that controls the cache coherency operation is rewritten with the latest value except when the synchronous instruction is issued, and the data that does not reflect that value in the main memory Block (DIRTY block)
Even if the number of times exceeds the default value, it is rewritten with the latest value, and the value is not reflected in the main memory (DI
The data block of the cache in the RTY state) is written to the main memory unit in the main memory by performing write-back processing to the main memory and a coherency holding operation if necessary, to the main memory that occurs intensively at the time of issuing the synchronous instruction. It is possible to distribute the write-back processing traffic and the consistency maintenance operation / traffic.

FIG. 2 is a diagram showing the configuration of a cache unit which is a part of this embodiment. Although the cache unit 11 is shown as an example in FIG. 2, the cache unit 21 also has a similar configuration.

In FIG. 2, 144 is a processor address bus interface for connecting to the processor address bus 141, and 145 is a processor data bus 142.
Is a processor data bus interface for connecting to the processor control bus 143, and 146 is a processor control bus interface for connecting to the processor control bus 143.

Reference numeral 154 is a local address bus interface for connecting with the local address bus 151, 155 is a local data bus interface for connecting with the local data bus 152, and 156 is for connecting with the local control bus 153. It is a local control bus interface.

Reference numeral 114 is a data entry for holding data, 112 is an address tag for holding the address of the data entry 114, and 113 is a status flag for holding the status of the data entry 114. These parts are assumed to be a set of storage elements such as SRAM, but are not limited thereto.

Reference numeral 115 denotes the contents of the address tag 112, the processor address bus 141, and the local address bus 1.
A comparator for comparing the address on 51. 116 is
It is a selector that selects the data in the data entry from the comparison result of the comparator 115.

Reference numeral 111 is a cache control sequencer for controlling each module in the cache unit.

In this embodiment, the cache unit has a two-way set associative structure.
It is not limited to this configuration. <Processing Procedure of LOAD Instruction> FIG. 3 shows a control procedure for executing a LOAD instruction for loading data into the processor in the cache unit configured as described above. Hereinafter, it will be described that the LOAD instruction is issued from the processor 10.

In FIG. 3, when a cache read hit occurs for the LOAD instruction issued from the processor 10 (S301-YES), the cache unit 11
Supplies a data block to the processor 10 (S306).

Further, the LO issued from the processor 10
When a cache read miss occurs for an AD instruction (S
301-NO), the cache unit 11 issues a read request to the local bus 15 (S302).
In this case, the cache unit 11 does not supply the data block to the processor 10 until the cache read missed data block is supplied to the cache unit 11.

The cache unit 11 transfers the address of the read access to the local address bus 151, issues a read request to the local control bus 153, and executes until a data block is supplied to the local data bus 152. However, this is not limited to the present embodiment.

The main memory unit 12 receives the read request and the address of the read access, supplies the data block to the local data bus 152, and the cache unit 11 receives it (S303).

The cache unit 11 replaces the data block supplied to the local data bus 152 with the entry of the data block in the cache unit 11 (S304). This process will be described later with reference to FIG.

The cache unit 11 is the processor 1
A data block is supplied to 0 (S305).

As described above, data is supplied to the processor in response to the LOAD instruction. <Processing Procedure of STORE Instruction> FIG. 4 shows a control procedure by the cache unit when executing the STORE instruction for writing data from the processor. Below, S
The TORE instruction will be described as issued from the processor 10.

In FIG. 4, when a cache write hit occurs for the STORE instruction issued from the processor 10, the data to be stored is received from the processor (S403), and the status flag corresponding to the data is set to "D".
IRTY "(S404). At the same time, the status flag counter 117 is incremented by 1 (S4).
05).

When the number of DIRTY blocks in the cache unit 11 reaches or exceeds a predetermined value set in the status flag counter 117, write back processing of the DIRTY blocks to the main memory is executed (S407). After writing back, the state flag counter is reset (S408). In the present embodiment, the default value of the number of DIRTY blocks in the cache, which is a criterion for determining whether or not to execute the write-back process to the main memory of the DIRTY block, is preset in the specified value memory in the status flag counter 117. However, the storage position is not limited to this.

The write-back process is performed by selecting a DIRTY block and executing the process shown in FIG. 6 for it.

STORE issued from the processor 10
When a cache write miss is made to the instruction, that is, when there is no corresponding address in the address tag of the cache unit, the cache read miss process, that is, the process after step S302 in FIG. 3 is performed (S402). Cache write hit processing shall be performed.

In this way, at the time of STORE processing of data, if the number of blocks brought into the DIRTY state by the STORE processing exceeds a predetermined number, the data block in the cache is written back to the main storage unit. <Procedure of Synchronous Instruction Processing> FIG. 5 shows a synchronous instruction for writing back the contents of a data block which may be accessed by a plurality of processors to the main memory so as to match the contents of the main memory with the contents of the cache. The control procedure at the time of execution is shown. Hereinafter, the synchronization instruction is the processor 1
It will be described as being issued from 0.

In FIG. 5, when the processor 10 issues a synchronization instruction, the cache unit 11 receives the DIR.
If one or more TY blocks exist (S501-YE
S), write back processing to the main memory of the DIRTY block is executed (S502). In this embodiment, DIRT
The write-back process to the main memory of Y block is DIRTY
It is repeatedly executed until there are no more blocks, but it is not limited to this.

After writing back, the state flag of the written back data block is set to CLEAN (S5
03), the state flag counter is decremented (S5
04).

In this way, all the blocks in the DIRTY state can be written back to the main memory and returned to the CLEAN state.

<Procedure of Write Back Processing> FIG. 6 shows a control procedure for executing the write back processing to the main memory. Hereinafter, it is assumed that the write-back process to the main memory is issued from the cache unit 11.

In FIG. 6, the cache unit 11
Transfers the write-back request source information to the local control bus 153 and the address of the write-back access to the local address bus 151, issues a write-back request to the local control bus 153, The data block to be written back to 152 is supplied, and the data block written back is supplied to the entry of the main storage unit,
Execution is stopped until the necessary consistency holding operation is completed and the write-back processing to the main memory is completed (S601). When the completion notification is received (S604), the write back process ends.

The main memory unit 12 accepts the read request, the address of the write back access, and the data block supplied to the local data bus 152, and writes it in the entry of the data block (S60).
2). After that, the completion is notified to the request source (S603).

At the same time, the cache units other than the cache unit 11 snoop the addresses transferred to the local bus 15 (S605) and hold the data copy in the valid state (either the CLEAN state or the DIRTY state). If so, the cache unit executes the coherency holding operation for the data block held in the valid state (S607). In the present embodiment, the coherency holding operation is an invalidation transaction in which a data block other than the written-back data block that is duplicated in the cache is invalid data, but the present invention is not limited to this. The invalidation is the status flag 13
Is set to "INVALID".

<Procedure of Replace Processing> FIG. 7 shows a control procedure at the time of replacing the data block. Hereinafter, it is assumed that the cache unit 11 executes the replacement of the data block.

In FIG. 7, the cache unit 11
When a data block replacement request is issued, the data block replacement algorithm detects a data block to be replaced by a data block replacement algorithm such as LRU (S701).

The data block to be replaced is DIRTY.
In the case of the state, the write-back processing to the main memory of the DIRTY block is executed (S704).

The data block to be replaced is DIRTY.
If the data block is not in the state or the replacement target data block is DI
When the write-back process to the main memory is completed in the RTY state, the data block is read to the data entry of the data block (S703, S705).

When a data block is read into the cache, this replacement process is executed to secure a usable area, and a new data block is read there. <State Transition of Data Block> FIG. 8 is a state transition diagram of the state flag when each memory transaction is executed. Hereinafter, the state flag of the cache unit 11 will be described.

In FIG. 8, the status INVALID indicates that the data entry managed by the status flag is invalid. The status CLEAN is set to 1 after the data entry managed by the status flag is read from the main storage unit.
Indicates that it has not been rewritten even once. Although the same value as the main memory unit is stored in the data entry, the latest value may be stored in the data entry of another cache unit. The state DIRTY indicates that the data entry managed by the state flag has been read from the main memory unit and then rewritten with the latest value one or more times, and the value is not reflected in the main memory. The latest value is stored in the data entry.

Each state transits as follows. When the LOAD instruction is issued from the processor 10 to the data block in the INVALID state, the state flag transits to CLEAN. When the STORE instruction is issued from the processor 10 to the data block in the INVALID state, the cache read miss process is once executed, the state flag transits to CLEAN, and the cache write hit process is then executed. Transition to DIRTY. When the LOAD instruction is issued from the processor 10 to the data block in the CLEAN state, the state flag transits to CLEAN. When the STORE instruction is issued from the processor 10 to the data block in the CLEAN state, the state flag transits to DIRTY. If a data integrity block operation in the CLEAN state is executed, the status flag is INVALI.
Transition to D. When the LOAD instruction is issued from the processor 10 to the data block in the DIRTY state, the state flag transits to DIRTY. When the STORE instruction is issued from the processor 10 to the data block in the DIRTY state, the state flag transits to DIRTY. When the processor 10 issues a synchronization instruction to a data block in the DIRTY state, the state flag transits to CLEAN. When the write-back process to the main memory is executed for the data block in the DIRTY state, the state flag transits to CLEAN. (10) When the consistency maintaining operation is executed for the data block in the DIRTY state, the state flag is INVAL
Transition to ID.

In order to understand the consistency maintaining operation according to the present invention, an example in which the consistency maintaining operation is postponed until the synchronous command issuance, which is a feature of this system, will be described first, and then the DIRT.
An example will be described in which the consistency keeping operation is postponed until the number of Y blocks exceeds a predetermined value.

Specifically, for example, the processors 10 and 20
Issues a LOAD instruction to the address f8000000, and after each LOAD instruction is completed, when the processor 10 issues a STORE instruction to the address f8000000, the cache unit 21 is issued to the cache unit 21 when the STORE instruction is issued. How to realize the execution of the consistency maintaining operation when the consistency maintaining operation is not issued and the synchronization instruction is issued from the processor 10 will be described with reference to FIG.

Similarly, when the processors 10 and 20 issue a LOAD instruction to the address f8000000 and the processor 10 issues a STORE instruction to the address f8000000, the inter-node interface 13 is issued when the STORE instruction is issued. DI is not issued to the cache unit 21
FIG. 10 shows how the mechanism of the cache units 11 and 21 realizes that the coherency hold operation is executed when the number of RTY blocks exceeds a predetermined value (2 in this example). Will be explained with reference to. <Maintaining Consistency (by Synchronous Command)> FIG. 9 is a timing chart showing an example of the consistency maintaining operation of this embodiment.

The description will be made assuming that the address f8000000 is assigned to the main memory unit 12.

At time 1, the processors 10 and 20 issue the LOAD instruction to the address f8000000, and each of them has completed reading from the main memory unit 12. At this time, the state flags 113 and 213 in the cache units 11 and 21 corresponding to the address f8000000000 are CLEAN, respectively.

At time 2, the processor 10 sends the address f
Issue a STORE command to the address 8000000,
The STORE command has been completed. At this time, the local bus access and the consistency holding operation do not occur. The status flag 113 in the cache 11 has been changed to DIRTY as a result of the STORE instruction issued by the processor 10. Further, the status flag counter 117 is incremented.

At time 3, the processor 10 issues a synchronization instruction.

At time 4, the DIRT is stored in the cache 11 by the synchronization instruction issued by the processor 10 at time 3.
A write back process to the main memory at the address f8000000 held in Y occurs.

At time 5, the address f8 generated at time 4
The data entry of the cache unit 21 is invalidated by the write-back process to the main memory at address 000000.

At time 6, the cache unit 11 which has accepted the completion of the coherency holding operation and completed the write-back processing to the main memory notifies the processor 10 of the completion of the synchronization instruction, and the synchronization instruction issued at time 3 is issued. Has been completed.

As described above, the sync command is issued before the number of DIRTY blocks becomes 2 or more, and the write back is performed by this. <Maintaining Consistency (Triggered by Number of DIRTY Blocks)> FIG. 10 is a timing chart showing an example of the consistency maintaining operation of this embodiment.

It is assumed that the address f8000000000 and the address f8000001 are assigned to the main memory unit 12.

At time 1, the processor 10 sends the address f
The LOAD instruction is issued to the address 8000000, and the reading from the main memory unit 12 is completed. The status flag 113 in the cache unit 11 is CLEAN.
It is.

At time 2, the processor 10 sends the address f
Issue a STORE command to the address 8000000,
The STORE command has been completed. At this time, the consistency maintaining operation does not occur. State flag 11 in cache 11
3 is the result of the STORE instruction issued by the processor 10,
It has been changed to DIRTY. Further, the status flag counter 117 is incremented.

At time 3, the processor 20 sends the address f
Issue a LOAD command to the address 8000000, and
The OAD instruction has been completed. Also at this time, the cache unit 21 only reads the data block from the main memory unit 12, and the coherency holding operation does not occur. LOA
As a result of the D instruction, the status flag 213 in the cache unit 21 is CLEAN.

At time 4, the processor 10 sends the address f
Issue a STORE command to 8000001
The STORE command has been completed. Status flag counter 1
When 17 is incremented, the number of DIRTY blocks becomes equal to or larger than the predetermined value (2), so that write-back processing to the main memory is occurring.

At time 5, the address f8 generated at time 4
The data entry of the cache unit 21 is invalidated by the write-back process to the main memory at address 000000.

At time 6, write-back processing to the main memory at address f8000001 occurs.

At time 7, when the write-back process to the main memory at the address f8000001 is completed, the write-back is performed when the number of data blocks in the DIRTY state becomes a predetermined value (2 in this example) or more. Since it is executed, even if the consistency maintaining operation by the synchronization instruction is executed,
Since a predetermined number or more of data blocks to be written back do not remain in each cache unit, it is possible to reduce the congestion of the bus traffic and the overhead associated with the synchronization operation.

The object of the present invention achieved by the function of the above apparatus or the function of the method can also be achieved by a storage medium storing the program in the above-mentioned apparatus for carrying out the present invention. That is, the storage medium is mounted on the device, and the program itself read from the storage medium achieves the novel function of the present invention. The structural characteristics of the program according to the present invention for this purpose are as shown in FIG. [Second Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 11 is a block diagram showing the configuration of the second embodiment of the system for realizing the present invention.

In FIG. 11, reference numerals 1, 2, and 3 are computer nodes. Reference numerals 10, 20, 30 denote processors, which are connected to the cache units 11, 21, 31 via processor buses 14, 24, 34, respectively.

Further, the cache units 11, 21, 31
Are connected to the main storage units 12, 22, 32 and the inter-node interfaces 13, 23, 33 via the local buses 15, 25, 35, respectively. Reference numeral 4 denotes a global bus, which is an inter-node interface 13, 23, 33.
Also, the global bus arbiter 5 is connected.

In FIG. 11, the number of connected computer nodes is 3, but the number is not limited to this number.

In the present embodiment, the consistency control adopting a loose memory consistency model that guarantees data consistency at the time of issuing a synchronous instruction explicitly given from the processor is shown in FIG. In an information processing system having such a configuration, the cache control sequencer that controls the cache coherency holding operation, when the number of DIRTY blocks exceeds the default value other than when the synchronous instruction is issued, cache data in the DIRTY state. By executing write-back processing to the main memory unit in the main memory unit and performing a coherency maintenance operation if necessary, a write-back processing traffic or consistency to the main memory that occurs intensively at the time of issuing a synchronous instruction It realizes holding operation and distributing traffic.

FIG. 12 is a diagram showing the internal structure of a computer node which is a part of this embodiment. In FIG.
Although the computer node 1 is taken as an example, the computer node 2,
The same configuration is adopted for 3.

In FIG. 12, the processor 10 can issue multiple memory accesses multiple times, and completes the multiple issued memory accesses under the data consistency guarantee by the loose memory consistency model. Shall have a special command (synchronous command).

In FIG. 12, 11 is a cache unit, 12 is a main memory unit, 15 is a local bus, and 13 is an internode interface. Also,
The main memory unit 12 includes a main memory control sequencer 121,
The memory 123 and the directory unit 122 are included. 141 is a processor 10 and a cache unit 11
Is a processor address bus for connecting the processor 10 and the cache unit 11, 142 is a processor data bus for connecting the processor 10 and the cache unit 11, and 143 is a processor control bus for connecting the processor 10 and the cache unit 11.

A memory access request signal line issued by the processor 10 is connected to the processor control bus 143.
And a memory access type signal line group indicating the type of the memory access request signal line.

Reference numeral 151 is a local address bus connecting the cache unit 11 to the inter-node interface 13 and the main memory unit 12, and 152 is a local data bus connecting the cache unit 11 to the inter-node interface 13 and the main memory unit 12. , 153 is the cache unit 11 and the inter-node interface 1
3. A local control bus for connecting the main memory unit 12.

The local control bus 153 includes a transaction request signal line issued by the cache unit 11 and a transaction type signal line group indicating the type of the coherency holding operation.

Reference numeral 43 is an inter-node interface 13, 2
Reference numeral 41 is a global control bus for connecting the nodes 3 and 33, 41 is a global address bus for connecting the inter-node interfaces 13, 23, 33, and 42 is a global data bus for connecting the inter-node interfaces 13, 23, 33.

The global control bus 43 includes a transaction request signal line issued by the inter-node interfaces 13, 23, 33 and a transaction type signal line group indicating the type of the transaction request signal line.

The global bus arbiter 5 receives the transaction request signal line issued from the inter-node interface and arbitrates the right to use the global bus 4.

Since the cache unit has the same structure as that of the first embodiment, its explanation is omitted.

FIG. 13 is a diagram showing the configuration of the main memory unit 12 which is a part of this embodiment.

In FIG. 13, reference numeral 121 is a main memory control sequencer for controlling each module in the main memory unit. 1
Reference numeral 24 is a directory flag for holding shared information of the data blocks held in the cache units 11, 21, 31. The 122 directory unit is a module that internally holds a directory flag. Reference numeral 123 is a memory that holds a data block.

157 is a local address bus interface for connecting to the local address bus 151, 158 is a local data bus interface for connecting to the local data bus 152, and 159 is for connecting to the local control bus 153. It is a local control bus interface. <Processing Procedure of LOAD Instruction> FIG. 14 shows a control procedure for executing a LOAD instruction in each node of the multiprocessor system configured as described above.
Hereinafter, it will be described that the LOAD instruction is issued from the processor 10. It should be noted that the broken-line arrow indicates that control is transferred between units.

In FIG. 14, in response to the LOAD instruction issued from the processor 10, the LOAD
If there is an address to be D, that is, if there is a cache read hit (S1401-YES), the cache unit 11 supplies a data block to the processor 10 (S1416).

Further, the LO issued from the processor 10
When a cache read miss occurs for the AD instruction, the cache unit 11 issues a read request to the local bus 15 (S1402). In this case, the cache unit 11 does not supply the data block to the processor 10 until the cache read missed data block is supplied to the cache unit 11.

The cache unit 11 transfers the read request source information to the local control bus 153 and the address of the read access to the local address bus 151, and the local control bus 153.
Issue a read request to the local data bus 15
Wait until 2 is supplied with data block.

(1) When a cache read miss occurs and the address of the read access (the address to be LOADed) is the main storage unit 12 in the computer node 1.
Read access to (S1403-YE
S), the cache unit requests data from the main storage unit (S1411). In response to this request, the main memory unit 12 receives the read request and the address of the read access, and supplies the data block to the local data bus 152. At the same time, the main memory unit 12
A directory flag corresponding to the cache unit 11 which is the read request source is registered in the directory unit 122 therein (S1412, 1413). This step is an operation by the main memory unit, not the cache unit.

When the cache unit 11 receives data from the main storage unit, it performs a replacement process to create a usable area in the cache (S1414),
The data block supplied to the local data bus 152 is written in the entry of the data block in the cache unit 11 (S1415).

(2) When a cache read miss occurs and the address of the read access is a main memory unit outside the computer node 1 (for example, main memory unit 22)
If the read access is to (S1403-N
O), the cache unit issues a data request to the global bus (S1404). In response to this, the inter-node interface 13 accepts the read request and the address of the read access and transfers the read request source information to the global control bus 43 and the address of the read access to the global address bus 41. And the internode interface 2 of the remote node
A read request is issued to No. 3, and waits until a data block is supplied to the global data bus 42.

The inter-node interface 23 receives the read request and the address of the read access and transfers the read request source information to the local control bus 253 and the address of the read access to the local address bus 251. , Issues a read request to the local control bus 253, and waits until a data block is supplied to the local data bus 252. In this way, a data request is made to the main storage unit of the remote node (S1405).

The main memory unit 22 receives the read request and the address of the read access and supplies a data block to the local data bus 252. At the same time, the directory unit 22 in the main memory unit 22
A directory flag corresponding to the cache unit 21 that is the read request source is registered in 2 (S1406).

The inter-node interface 23 transfers the data block supplied to the local data bus 152 to the global data bus 42 (S1407).

The inter-node interface 13 transfers the data block supplied to the global data bus 42 to the local data bus 152 (S1408).

Steps S1406 to S1408 are not the processing by the cache unit but the processing on the side that receives the request.

The cache unit 11 secures a usable data block by the replacement process (S140).
9) Read the data block supplied to the local data bus 152 into the entry of the data block in the cache unit 11.

The cache unit 11 is the processor 1
A data block is supplied to 0 (S1410).

In this way, the desired data block is loaded from the main memory unit of each node.

The control procedure for executing the STORE instruction is the first
The description is omitted because it is the same as that of the above. Further, the control procedure at the time of executing the synchronous command is similar to that of the first embodiment, and therefore the description thereof is omitted. <Procedure of Write Back Process> FIG. 15 shows a control procedure when executing the write back process to the main memory.
Hereinafter, it is assumed that the write-back process to the main memory is issued from the cache unit 11.

In FIG. 15, the cache unit 11
Transfers the write-back request source information to the local control bus 153 and the write-back access address to the local address bus 151, and issues a write-back request to the local control bus 153 (S1501). Local data bus 152
The data block to be written back to is supplied to the entry of the main memory unit concerned, the necessary consistency holding operation is completed, and the write-back processing to the main memory is completed.

(1) When the address of the write-back processing to the main memory is a write-back access to the main memory unit 12 in the computer node 1 (S1502-Y)
ES), and issues a write back request to the main storage unit of the local node (S1510).

The main memory unit 12 receives the read request, the address of the write-back access and the data block supplied to the local data bus 152, and receives the directory unit 12 in the main memory unit 12.
2 is checked to see if a directory flag other than the cache unit 11 which is the write-back request source is registered (S1511). When a copy of data is also held in the valid state in a cache unit other than the cache unit 11, the coherency holding operation is executed for the cache unit data block held in the valid state. In this case, a process of invalidating the copy of the data block held in the cache unit is executed as the coherency holding operation (S1513).

In this embodiment, the consistency holding operation is an invalidation type transaction, but this is not limited to this embodiment.

After the consistency holding operation is completed, the main memory unit writes the write back data in the entry of the data block (S1514). Finally, the completion of write-back processing to the main memory is notified to the cache unit 11 (S1515).

(2) When the address of the write-back processing to the main memory is a write-back access to the main memory unit (for example, the main memory unit 22) outside the computer node 1 (S1502-NO), the cache unit 1
1 issues a write back request to the inter-node interface 13.

The inter-node interface 13 uses the write-back request and the address of the write-back access,
The data block supplied to the local data bus 152 is accepted, the write-back request source information is sent to the global control bus 43, the write-back access address is sent to the global address bus 41, and the write-back access address is sent to the global data bus 42. A data block for write-back access is transferred, and a write-back request is issued to the inter-node interface 23 (S
1503).

The inter-node interface 23 accepts the write-back request and the address of the read access, and writes the write-back request source information to the local control bus 253 and the address of the write-back access to the local address bus 251. The data block of the write-back access is transferred to the local data bus 252, and the local control bus 25
Issue a write-back request to 3. In this way, the write back request is issued for the main storage unit of the remote node (S1504).

The main memory unit 22 is the main memory unit 2
2 is searched for a directory flag other than the cache unit 11 which is the source of the write-back request (S150).
5). When a copy of data is also held in the valid state in a cache unit other than the cache unit 11, the coherency holding operation is executed for the cache unit data block held in the valid state. In this case, the copy in the valid state is invalidated for consistency.

After the consistency holding operation is completed, the main memory unit 2
2 receives the read request, the address of the write-back access, and the data block supplied to the local data bus 252, and writes it in the entry of the data block (S1508).

The inter-node interface 23 notifies the inter-node interface 13 of the completion of write-back processing to the main memory.

The inter-node interface 13 notifies the cache unit 11 of the completion of the write-back processing to the main memory (S1509).

Of the above procedure, steps S1501 to S1501.
1503 and S1510 are processes of the cache unit, step S1504 is a process of the inter-node interface, and other steps are processes by the main memory of the node that has received the write-back request. With the above procedure, the directory is referenced to invalidate, and write back is executed.

The control procedure at the time of execution of the replacement process is the same as that of the first embodiment, and therefore its explanation is omitted.

The state transition of the state flag at the time of executing each memory transaction is also the same as that of the first embodiment, and the description thereof is omitted.

In order to understand the procedure of the consistency maintaining operation according to the present method, an example in which the consistency maintaining operation is postponed until the synchronous command is issued will be described first, and then the number of DIRTY blocks will exceed a predetermined value. An example will be described in which the consistency maintaining operation is executed at that time.

Specifically, for example, the processors 10 and 2
0 and 30 are LO for the address f8000000
When the processor 10 issues a STORE instruction to the address f8000000 after issuing the AD instruction and completing each LOAD instruction, the coherency holding operation is not performed on the cache units 21 and 31 at the time of issuing the STORE instruction. Synchronous instructions not issued and processor 1
It will be described with reference to FIG. 16 how to realize that the consistency holding operation is issued when issued from 0. Similarly, the processors 10, 20, and 30 are set to the address f8000000. If the LOAD instruction is issued to the processor 10 and the STORE instruction is issued to the address f8000000, the inter-node interface 13 does not issue the coherency holding operation to the cache units 21 and 31 at the time of issuing the STORE instruction. , When the number of DIRTY blocks exceeds a predetermined value (2 in this example), how to implement the coherency maintaining operation is realized by the mechanism possessed by the inter-node interfaces 13, 23, 33. This will be described with reference to FIG.

FIG. 16 is a timing chart showing an example of the consistency maintaining operation of this embodiment. Address f80
Main storage unit 1 in computer node 1 at address 00000
It will be described as being assigned to 2.

At time 1, the processors 10, 20, 30
Are LO for the address f8000000.
An AD instruction has been issued, and each has completed loading from the main memory unit 12. At this time, the address f8000
In the directory flag corresponding to address 000, the cache unit 11, which is the node holding the copy,
21 and 31 are registered.

At time 2, the processor 10 sends the address f
Issue a STORE command to the address 8000000,
The STORE command has been completed. At this time, the consistency maintaining operation does not occur. State flag 11 in cache 11
3 is the result of the STORE instruction issued by the processor 10,
The state has been changed to DIRTY. Further, the status flag counter 117 is incremented.

At time 3, the processor 10 issues a synchronization instruction.

At time 4, the DIRT is stored in the cache 11 by the synchronization instruction of the processor 10 issued at time 3.
A write back process to the main memory at the address f8000000 held in Y occurs.

At time 5, the address f8 generated at time 4
A write-back process to the main memory at address 000000 causes a consistency holding operation.

At time 6, the cache units 21 and 31 are invalidated due to the consistency holding operation that occurred at time 5.

At time 7, the cache unit 11 which has accepted the completion of the coherency holding operation and completed the write-back processing to the main memory notifies the processor 10 of the completion of the synchronization instruction, and the synchronization instruction issued at time 3 is issued. Has been completed.

Thus, any cache unit has a DIRT equal to or higher than a predetermined threshold value (2 in this case).
Since the data block in the Y state does not occur by the predetermined synchronization time (time when the synchronization command is issued),
The write back and the consistency maintaining operation (invalidation processing) are performed for the first time by the synchronization instruction.

FIG. 17 is a timing chart showing an example of activating the consistency maintaining operation triggered by the number of data blocks in the DIRTY state.

It is assumed that the address f8000000 and the address f8000001 are assigned to the main storage unit 12 in the computer node 1.

At time 1, the processors 10 and 20 issue a LOAD instruction to the address f8000000, and the respective processors have completed reading from the main memory unit 12. At this time, the cache unit 1 is set in the directory flag corresponding to the address f8000000.
1, 21 are registered.

At time 2, the processor 10 sends the address f
Issue a STORE command to the address 8000000,
The STORE command has been completed. At this time, the consistency maintaining operation does not occur. State flag 11 in cache 11
3 is the result of the STORE instruction issued by the processor 10,
It has been changed to DIRTY. Further, the status flag counter 117 is incremented.

At time 3, the processor 30 sets the address f
Issue a LOAD command to the address 8000000, and
The OAD instruction has been completed. Also at this time, the cache unit 31 only reads the data block from the main memory unit 12, and the coherency holding operation does not occur. LOA
As a result of the D instruction, the cache unit 11 or 2 is added to the directory flag corresponding to the address f8000000.
1, 31 are registered.

At time 4, the processor 10 sends the address f
Issue a STORE command to 8000001
The STORE command has been completed. Status flag counter 1
When 17 is incremented, the number of DIRTY blocks becomes 2 or more, which is the default value, so that the write-back process to the main memory occurs.

At time 5, the address f8 generated at time 4
A write-back process to the main memory at address 000000 causes a consistency holding operation.

At time 6, the cache units 21 and 31 are invalidated by the coherency holding operation that occurred at time 5.

At time 7, write-back processing to the main memory at address f8000001 occurs.

At time 8, the write-back processing to the main memory at the address f8000001 is completed, and as described above, when the number of DIRTY data blocks in the cache exceeds the predetermined number. In addition, by writing back the DIRTY block in the cache to the main memory (and the consistency holding processing), the number of blocks to be written back and the consistency holding processing at the next synchronization time becomes less than the preset upper limit. Can be suppressed. For example, in the present example, in a system consisting of N nodes, if writeback is performed when b blocks or more DIRTY blocks occur for one node, writeback and synchronization holding processing are performed at once by a synchronization command. The number of data blocks to be covered does not exceed N × b.

As described above, by providing the cache memory and the coherency maintaining operation mechanism of the cache memory and distributing the traffic on the interconnection network concentrated at the synchronization point, the utilization efficiency of the interconnection network is reduced. Also, the processing overhead associated with the synchronous operation can be reduced.

It goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus. In this case, the system or device enjoys the effects of the present invention by reading the program into the system or device from a storage medium storing a program represented by software for achieving the present invention. It becomes possible.

[0151]

As described above, according to the present invention,
In a parallel computer system that employs a loose memory consistency model and is connected to each other by an interconnection network,
Providing a cache memory and a coherency retention operation mechanism for the cache memory to further improve its performance,
By distributing the traffic on the interconnection network that concentrates at the synchronization point, it is possible to reduce the utilization efficiency of the interconnection network and reduce the processing overhead associated with the synchronization operation, improving the processing capacity of the entire system. It has the effect of

[0152]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an information processing system according to a first embodiment.

FIG. 2 is a diagram showing a configuration of a cache unit of the first and second embodiments.

FIG. 3 is a chart of processing performed by a cache unit when a LOAD instruction is executed in the first embodiment.

FIG. 4 is a chart of processing performed by a cache unit when a STORE instruction is executed in the first and second embodiments.

FIG. 5 is a chart of processing performed by a cache unit when executing a synchronous instruction in the first and second embodiments.

FIG. 6 is a chart at the time of performing a write-back process to a main memory in the first embodiment.

FIG. 7 is a chart of a process performed when replacing a data block in the first embodiment.

FIG. 8 is a state transition diagram of state flags of the first and second embodiments.

FIG. 9 is a chart showing an example in which the consistency holding operation is postponed until the time when a synchronous instruction is issued in the first embodiment.

FIG. 10 is a chart showing an example in which the consistency maintaining operation is postponed until the number of DIRTY blocks exceeds a predetermined value in the first embodiment.

FIG. 11 is a diagram showing a configuration of an information processing system according to a second embodiment.

FIG. 12 is a diagram showing a configuration of a computer node according to the second embodiment.

FIG. 13 is a diagram showing a configuration of a main memory unit of the second embodiment.

FIG. 14 is a chart of processing performed by a cache unit when a LOAD instruction is executed in the second embodiment.

FIG. 15 is a chart of processing performed at the time of write-back processing to the main memory in the second embodiment.

FIG. 16 is a chart showing an example in which the consistency holding operation is postponed until the synchronous command issuance time according to the second embodiment.

FIG. 17 is a chart showing an example in which the consistency maintaining operation is postponed until the number of DIRTY blocks according to the second embodiment exceeds a predetermined value.

FIG. 18 is a diagram showing a memory map in which program modules for realizing the first embodiment are recorded in a storage medium.

[Explanation of symbols]

1, 2, 3 Computer node 4 Global bus 5 Global bus arbiter 10, 20, 30 Processor 11, 21, 31 Cache unit 12, 22, 32 Main memory unit 13, 23, 33 Inter-node interface 14, 24, 34 Processor bus 15, 25, 35 Local Bus 16 Bus Arbiter 41 Global Address Bus 42 Global Data Bus 43 Global Control Bus 44 Global Address Bus Interface 45 Global Data Bus Interface 46 Global Control Bus Interface 111 Cache Control Sequencer 112 Address Tag 113 Status Flag 114 Data Entry 115 Comparator 116 Selector 117 Status flag counter 121 Main memory control sequencer 122, 2 2,322 directory unit 123,223,323 memory 124,224,324 directory flag 144,244,344 processor address bus interface 145,245,345 processor data bus interface 146,246,346 processor control bus interface 154,254,354 , 157 Local address bus interface 155, 255, 355, 158 Local data bus interface 156, 256, 356, 159 Local control bus interface 141, 241 and 341 Processor address bus 142, 242 and 342 Processor data bus 143, 243 and 343 Processor Control bus 153, 253, 353 Local control bus 51,251,351 local address bus 152,252,352 local data bus

Claims (12)

[Claims] 1. In an information processing system including a plurality of processors, a cache memory associated with each of them, a main memory, and a connection network interconnecting the cache memory and the main memory, the processing of each processor is predetermined. When reaching the stage, the data block existing in the cache memory attached to the processor is reflected in the main memory,
An information processing system characterized by executing a consistency maintaining process for maintaining consistency of block contents. 2. Data existing in the cache memory, if a data block existing in the cache memory satisfies a predetermined condition before the processing by the processor reaches the predetermined stage.・
2. The information processing system according to claim 1, wherein the block is reflected in the main memory, and a consistency maintaining process is executed to maintain the consistency of the contents of the data block. 3. The information according to claim 2, wherein the predetermined condition is determined by comparing the number of data blocks whose contents are not reflected in the main memory with a predetermined value. Processing system. 4. The information processing system according to claim 2, wherein the predetermined condition is determined by comparing the number of times data is written by the processor with a predetermined value. 5. The information processing system is a loose memory consistency model.
5. The information processing system according to any one of 4 to 4. 6. The coherency maintaining process is a process of invalidating a copy of a data block reflected in a main memory from one cache memory and retained in a cache memory other than the cache memory. The information processing system according to claim 1, wherein: 7. The main memory is connected to each of the plurality of processors, and a cache memory attached to one of the processors is a cache memory of another processor.
Detects from the memory that the process of reflecting the data block stored in it to the main memory has been performed and invalidates the duplication of the corresponding data block stored in the cache memory. The information processing system according to claim 6, wherein the consistency holding process is executed by performing the process. 8. The main memory is connected to each of the plurality of processors in a distributed manner, and the main memory is copied to a cache memory every time a data block whose content is to be copied is copied to a cache memory. Is recorded and a process of reflecting the data block stored therein from the cache memory of one of the plurality of processors to the main memory is performed, the corresponding data block of the corresponding data block is recorded based on the record of the copy destination. The information processing system according to claim 6, wherein the consistency holding process is executed by invalidating the copy. 9. A plurality of information processing means are connected to each other, data is copied from a storage means to a cache means attached to each information processing means, and the contents of the storage means are shared by the plurality of information processing means. In the information processing system, there is provided an information processing method of simultaneously writing back the contents of the cache means to the storage means at a predetermined stage, the reading step of reading a desired data block stored in the storage means into the cache means, A cache updating step of updating the data blocks read in the cache means by the reading step, a counting step of counting the number of data blocks updated by the cache updating step, a number of data blocks counted by the counting step and a predetermined value And the updated data block based on the comparison result. The information processing method characterized by comprising the steps writeback written back to the means. 10. A cache means other than the cache means that has been written back detects the write-back of the data block to the storage means by the write-back process, and is the object of write-back held in the cache means. The information processing method according to claim 9, further comprising the step of invalidating the duplication of the data block. 11. For each data block read from the main storage means to the cache means in the reading step,
When a data block is written back to the main memory by the recording step of recording the read destination and the write back step, the data block stored in the cache means of the read destination recorded by the recording step for the data block. The information processing method according to claim 9, further comprising the step of invalidating the duplication of the. 12. A plurality of computer control devices, which are connected to a plurality of devices and read a predetermined program from a memory medium to control the program, and read a desired data block stored in the storage means into a cache means. A module of a cache updating step of updating the data block read in the cache means by the reading step, a module of a counting step of counting the number of data blocks updated by the cache updating step, and a counting step of The number of data blocks counted is compared with a predetermined value, and based on the comparison result, the updated data block is written back to the storage means. Batch writing back all data blocks to storage means Computer controller, characterized in that it comprises a module step was.