JPH05233339A - Circuit for preventing malfunction of microcomputer - Google Patents

Abstract

PURPOSE:To prevent malfunction from occurring due to an erroneous program by applying interruption to a microcomputer and initializing the program when a work area and an operand is read in as an operation code. CONSTITUTION:An identification code (ninth bit) of at least one or more bits can be stored by expanding the memory space of a ROM 2 which operates an MPU 1 by a loaded program. and the identification code (ninth bit) is inputted from the ROM 2 to a latch circuit 4 at a timing to read out an instruction by the MPU 1. The latch circuit 4 outputs the identification code (ninth bit) by latching with a latch pulse (M1) inputted from the MPU 1, and inputs the output to the interruption terminal of the MPU 1, and when the polarity of the output is inverted, an erroneous instruction is prevented from being executed by the MPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction prevention circuit for a microcomputer (hereinafter abbreviated as "microcomputer").
In recent years, microcomputers have come to be used for controlling various devices.
There is a problem of malfunction due to electrostatic noise or external noise such as EMI, and it is necessary to prevent this and improve the reliability of the control circuit.

[0002]

2. Description of the Related Art In conventional microcomputer boards and the like,
By properly arranging the ground line and thickening the ground line, it is difficult to be affected by power source noise, electrostatic noise, or external noise such as EMI. However, it is not enough as a preventive measure, and the microcomputer reads the work area provided inside the microcomputer or the operand in one instruction composed of the instruction code (opcode) and multiple operands as the opcode, and the wrong program Due to this, the microcomputer worked and sometimes went out of control.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a malfunction of a microcomputer by interrupting the microcomputer to initialize the program when the microcomputer reads a work area or an operand as an operation code. ..

[0004]

FIG. 1 is an electric circuit block diagram of a microcomputer malfunction prevention circuit showing an embodiment of the present invention. As shown in FIG. 1, the MPU 1 is operated by a written program. In ROM2,
The memory space of the ROM 2 is expanded so that an identification code of at least 1 bit (9th bit in FIG. 1) can be stored, and the identification code (9th bit) is read from the ROM 2 at the timing when the MPU 1 reads an instruction. ) Is input to the latch circuit 4, and the latch circuit 4 receives the MPU1
The identification code (9th bit) is latched and output by the latch pulse (M1) input from the MPU1, and the MPU1 is controlled based on the output. When the polarity of the output is inverted, the MPU1 is output. An interrupt is applied to initialize the program to prevent the MPU 1 from executing the wrong instruction.

[0005]

According to the present invention, when the polarity of the output from the latch circuit 4 is reversed, the MPU 1 is interrupted to initialize the program, and the microcomputer reads the work area and the operand as an opcode. Thus, it is possible to prevent the microcomputer from operating due to an incorrect program.

[0006]

FIG. 1 is an electric circuit block diagram of a microcomputer malfunction prevention circuit showing an embodiment of the present invention. The microcomputer is composed of an MPU, a memory LSI, and an interface LSI that is a link between the input / output device and the like.
Is a CPU (central processing unit) having a control unit and a calculation unit,
The I / O device is incorporated in one LSI.
1 is MPU (abbreviation of Micro Processor Unit), and 2
Is ROM (abbreviation of Read Only Memory), and MPU1
The ROM2 and ROM2 are connected by an address bus and a data bus. The program executed by the MPU1 is written in the ROM2 in advance as data, and the MPU1 specifies the address so that the data corresponding to the specified address is read from the ROM2. Read and MP the specified instruction
U1 is trying to execute. In the embodiment shown in FIG. 1, the address bus uses 16 bits and is therefore composed of 16 lines, and the data bus uses 8 lines when an 8-bit microcomputer is used. Composed of. The memory space of the ROM2 is expanded so that an identification code of at least 1 bit or more (9th bit in FIG. 1)
Is stored, and the identification code (9th bit) can be output from the ROM 2 at the timing when the MPU 1 reads the instruction.

Reference numeral 4 denotes a latch circuit, which inputs the identification code (9th bit) to a data input terminal (DATA) of the latch circuit 4 and outputs a latch pulse (M1) output from the MPU 1 to the latch circuit 4. It is input to the clock pulse input terminal (CK) and the output (Q) of the latch circuit 4 is MP.
It is input to the interrupt terminal (NMI) of U1. As the latch circuit 4, for example, a flip-flop circuit can be used. The latch circuit 4 outputs a latch pulse (M
The identification code (9th bit) is latched and output according to 1), and the MPU1 is controlled based on the output. If the polarity of the output is inverted, the program that interrupts the MPU1 and is executed by the MPU1 To prevent the microcomputer from operating with an incorrect program. Reference numeral 3 denotes an address decode, which uses a logic circuit to branch the address bus and input it to the address decode 3. The output is input to the chip select terminal (CS) of the ROM 2 to operate and stop the ROM 2. The data written in the ROM 2 can be read out to a designated register in the MPU 1. Further, the output from the address decode 3 is input to the reset terminal (reset) of the latch circuit 4, and RO
The latch circuit 4 can be reset at the timing of operating M2.

2A and 2B are operation timing charts of the microcomputer malfunction prevention circuit of the present invention.
For example, assume that a general-purpose Z80 is used as the microcomputer. One instruction executed by the microcomputer consists of one opcode and up to six operands, and the opcode and operands are defined as machine cycles of up to M6 cycles. It is assumed that an instruction to transfer hexadecimal 10 is input to the A register as an instruction to be executed by the MPU 1. In this case, the instruction used between the MPU 1 and the ROM 2 is 3E · 10, 3E indicates the operation code of the M1 cycle, 10 indicates the operand of the M2 cycle, and this instruction is composed of 2 bytes.

In FIG. 3A, the upper waveform is MPU1.
From the ROM 2 to the ROM 2 through the address bus, the second-stage waveform M1 is a clock pulse output from the MPU 1, and the third-stage waveform 9th bit data is data read from the ROM 2. Yes, the waveform NMI at the bottom shows the output of the latch circuit 4. In this case, the ninth bit data input to the latch circuit 4 is latched and output at the rising edge of the clock pulse M1, and the output from the latch circuit 4 is maintained at the H level. The input to the terminal (NMI) becomes H level, and the MPU 1 executes the input instruction. For example, as shown in FIG. 6B, a malfunction factor is generated by noise or the like, and when an instruction executed by the MPU1 is read from the ROM2 with the M2 cycle as an operation code (M1) cycle, the MPU1 malfunctions or runs out of control. It will be.

In this case, the ninth bit data input to the latch circuit 4 is latched and output at the rising edge of the clock pulse M1, and the output from the latch circuit 4 becomes L level and the output polarity is Invert, MPU1
MP to set the interrupt terminal (NMI) of L level to
The U1 is interrupted to initialize the program and prevent the MPU1 from operating due to a wrong program.
Even when the MPU1 reads the work area provided inside the microcomputer as an operation code, the output from the latch circuit 4 becomes the L level and the polarity of the output is inverted in the same manner as described above, and the MPU1 interrupt terminal (NMI) Is interrupted and the program is initialized to prevent the MPU 1 from operating due to a wrong program. Figure 3
It is a flow chart which shows the initialization procedure of a microcomputer,
As shown in the figure, when the interrupt terminal NMI is interrupted, the MPU 1 interrupts the program being executed,
The NMI signal is reset, the input of each register of the MPU 1 is reset, and the program is initialized and terminated.

[0011]

As described above, according to the present invention,
It is possible to provide a microcomputer malfunction prevention circuit that prevents the microcomputer from reading and executing an erroneous program, which greatly contributes to improving the reliability of the control circuit using the microcomputer.

[Brief description of drawings]

FIG. 1 is an electric circuit block diagram of a microcomputer malfunction prevention circuit showing an embodiment of the present invention.

2A and 2B are operation timing charts of the microcomputer malfunction prevention circuit of the present invention.

FIG. 3 is a flowchart showing an initialization procedure of a microcomputer.

[Explanation of symbols]

 1 MPU 2 ROM 3 Address decode 4 Latch circuit

Claims (3)

[Claims] 1. A ROM operating an MPU by a written program to expand a memory space of the ROM so that an identification code of at least 1 bit or more can be stored, and the MPU reads the instruction at the timing. The identification code is output from the ROM and input to a latch circuit. The latch circuit latches and outputs the identification code with a latch pulse input from the MPU, and the same output is input to an interrupt terminal of the MPU. A microcomputer malfunction prevention circuit, characterized in that, when the polarity of the output is reversed, the MPU is interrupted to initialize a program so that the MPU does not execute a wrong instruction. 2. The latch circuit comprises a flip-flop circuit, the identification code is input to a data input terminal of the flip-flop circuit, the latch pulse is input to a clock pulse input terminal, and an output from the flip-flop circuit is input. Is input to the interrupt terminal of the MPU, and the M
2. The microcomputer malfunction prevention circuit according to claim 1, which controls the PU. 3. An address bus connecting between the MPU and the ROM is branched and input to a logic circuit,
The control signal from the logic circuit is input to the chip select terminal of the ROM, and in the logic circuit controlling the operation and stop of the ROM, the output from the logic circuit is input to the reset terminal of the latch circuit. , Said R
3. The microcomputer malfunction prevention circuit according to claim 1, wherein the latch circuit is reset at a timing at which the OM is operated.