JPH0523058B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a charge-coupled device, and in particular, automatically adjusts the bias conditions of the input section of the charge-coupled device so that the DC component of the amount of transferred charge to be injected is optimized. This relates to a device that determines the

[Background of the invention]

Conventional charge-coupled devices require preconditioning of the DC bias charge at their input in order to successfully transfer AC signal components. This problem will be explained below using the drawings.

The input operation will be described with reference to FIG. 1 showing the cross-sectional structure of the input section of the charge-coupled device and the internal potential under each gate electrode during operation, and FIG. 2 showing the drive pulse waveform. The example shown in FIG. 1 is a buried channel charge coupled device with a two-layer gate electrode structure and two-phase drive, in which a diode cut-off method is used as the input method. First, the structure shown in FIG. 1 will be explained. 1 is a P-type semiconductor substrate, 2 is a high concentration N-type diffusion layer, 3 is an N-type buried layer, 4,
5, 6, and 7 are N-type buried layers with low concentration formed by doping the N-type buried layer 3 with P-type impurities, respectively. When the voltages of the gates 8 to 15 are the same, the internal potential under the gate electrodes 8, 10, 12, 14 with the low concentration N-type buried layers 4, 5, 6 and the gate electrode 9 without the same buried layer. ,11,
A difference occurs between the internal potential below 13. This difference in internal potential prevents reverse flow of charges and gives directionality to charge transfer. 8 to 15 are gate electrodes, and 16 to 19 are drive pulse input terminals, respectively. Sampling pulses are applied to the electrode 8 from the input terminal 16 shown in FIG.
Therefore, the driving pulse shown in Fig. 2 _P1 is applied to electrode 1.
The drive pulses shown in FIG. 2 _{, P2} , are input to the input terminals 2 and 13, respectively. Reference numeral 20 denotes a constant voltage source that applies a DC bias voltage to the N-type diffusion layer 2 via a resistor 23. 21 is also a constant voltage source and applies a DC voltage to the gate electrode 9. A signal source 22 supplies a delayed signal to the N-type diffusion layer 2 via an AC coupling capacitor 24.

Here, it is assumed that the constant voltage sources 20 and 21 have adjusted appropriate voltages. As shown in Figure 2, at time t= _t1 , the sampling pulse Ps is at the level
The internal potential under the gate electrode 8 becomes high, and the potential wells under the gate electrodes 8 and 9 are filled with charges supplied from the N-type diffusion layer 2 up to the potential of the N-type diffusion layer 2. At this time, since the drive pulse _P1 is at a low level, the internal potential under the gate electrode 10 is shallow and acts as a potential barrier against the supplied charges. At time t= _t2, the sampling pulse Ps becomes low level, so the internal potential under the gate electrode 8 becomes shallow, and the potential well under the electrode 9 is disconnected from the N-type diffusion layer 2, which is the charge supply source. Ru. At this time, the charge Qi _N accumulated under the gate electrode 9 is
It is approximately proportional to the difference between the potential φ _R below and the potential Vs ₁ of the N-type diffusion layer 2. That is, Qi _N =K(φ _R −Vs ₁ ). Here, K is a constant that depends on the area of the gate electrode 9, etc. At time t= _t3, the drive pulse _P1 becomes high level and the drive pulse _P2 becomes low level, so that the charge under the electrode 9 is transferred to the potential well below the electrode 11. At time t= _t5 , drive pulses P ₁ and P ₂ are reversed,
Charges under electrode 11 are transferred to under electrode 13. Thereafter, charge transfer is performed every time the drive pulses P ₁ and P ₂ are reversed. Here, the potential Vs ₁ is the constant voltage source 2
Since it is the sum of the zero potential V _DC and the AC signal f(t) of the signal source 22, the supplied charge Qi _N is Qi _N = K (φ _R − V _DC ) − Kf(t) (1) and the AC signal is It is expressed as the sum of a charge Kf(t) proportional to the signal and a DC charge K (φ _R −V _DC ).

Next, the operation of the output section will be explained. FIG. 3 shows the cross-sectional structure of the output section in the floating diffusion layer amplification method and the internal potential under each electrode during operation. First, the structure shown in FIG. 3 will be explained. Reference numeral 69 denotes an N-type diffusion layer, which acts as a drain for transferred charges. 70 is an N-type floating diffusion layer, and this diffusion layer 70 and the P-type substrate 7
The junction capacitance formed between 1 and 1 converts the transferred charge into voltage. 72 and 73 are N-type buried layers similar to 3 in FIG. 1, and 74, 75, and 76 are low-concentration N-type buried layers similar to 4, 5, and 6 in FIG. 77-82 are gate electrodes, 83,
84 and 85 are drive pulse input terminals. Electrode 7
Drive pulses (second
_P2 ), the electrodes 79 and 80 receive a drive pulse (P1 in Fig. ₁ ) from the input terminal 84, the electrode 81 receives a suitable DC voltage from the constant voltage source 86, and the electrode 82 receives a drive pulse from the input terminal 85. Reset pulse (Fig. 2 P _R )
are input respectively. 87 is a constant voltage source, 89,
92 is a constant current source, 88 and 91 are N-type MOS transistors, 90 is a sample hold, and 93 is an output terminal.

At time t=t ₃ , the driving pulse P ₁ is at a high level, so that the charge transferred from the potential well below the electrode 78 is accumulated in the potential well below the electrode 80 . Also, since the reset pulse P _R is at a high level, the electrode 8
The internal potential below 5 falls, and the floating diffusion layer 70 and the diffusion layer 69 are electrically connected, and the potential of the floating diffusion layer 70 is lower than that of the diffusion layer 6.
9, that is, the potential determined by the voltage source 87. This operation is called a reset operation.At time t= _t4 , the reset pulse P _R reaches the level
The floating diffusion layer 70 is insulated from the diffusion layer 69, that is, from the constant voltage source 87. At time t=t ₆ , the driving pulses P ₁ and P ₂ are reversed, and the charges under the electrode 80 are transferred to the floating diffusion layer 70 . The transferred charge
When Qs ₁ ^G and the junction capacitance of the floating diffusion layer are C, the voltage change ΔV appearing in the floating diffusion layer 70 is approximately expressed as ΔV=Qs ₁ ^G /C. At time t= _t7 , drive pulses P ₁ and P ₂
is inverted again, and the next signal charge is accumulated in the potential well below the electrode 80. From then on, the process is repeated from _t3 . Therefore, the voltage waveform appearing in the floating diffusion layer 70 becomes a comb-shaped waveform having the same period as the driving pulse, as shown in FIG. 4a. The high potential side of this voltage waveform is the voltage of the constant voltage source 87 determined by the reset operation. Since the transferred charges are electrons, the voltage change ΔV appearing in the floating diffusion layer 70 described above is negative, and a voltage change proportional to the signal charge appears on the low voltage side of the voltage waveform. In other words, Figure 4a
The low potential side envelope of is the delayed signal.
The signal shown in FIG. 4a is input to the sample and hold circuit 90 via a source follower composed of an N-type MOS transistor 88 and a constant current source 89. The sampled and held signal waveform shown in FIG. After this, by band-limiting, the signal waveform shown in FIG. 4c can be obtained.

Now, let's consider the maximum transfer charge amount.
In the internal potential diagram at time t= _t3 in FIG. 1, the internal potential difference Δφ _TS between the electrodes 10 and 11 is as follows:
This is a constant determined by processes such as the concentration of the N-type buried layer 3 and the concentration of the low-concentration N-type buried layer 4. If an attempt is made to input charges beyond the depth Δφ _TS , the charges will flow back from below the electrode 11 to below the electrode 9 at the change from time t ₃ to time t ₅ in FIG. That is, there is an upper limit KΔφ _TS for the charge supplied at the input section. Further, the upper limit of the charge transferred each time the driving pulses P ₁ and P ₂ are inverted is also KΔφ _TS . Therefore, the maximum transfer charge amount Q _MAX =KΔφ _TS . 0
Since Qi _N Q _MAX , it becomes 0K(φ _R −V _DC )−Kf(t)KΔφ _TS (2), and if the signal f(t) of the signal source 22 is expressed as Asinωt, 0φ _R −V _DC −AsinωtΔφ _TS ( 3) The maximum amplitude of the signal A _MAX is when φ _R −V _DC = 1/2Δφ _TS (4) A _MAX = Δφ _TS /2 (5). This shows that the optimal amount of bias charge supplied at the input section is 1/2 of the maximum transfer charge amount Q _MAX . Therefore, it is usually necessary to set the values of the constant voltage sources 20 and 21 so as to satisfy equation (4). However, while V _DC depends only on the potential of the constant voltage source 20, φ _R depends on the constant voltage source 21, the concentration of the N-type buried layer 3, and the thickness of the insulating oxide film between the gate electrode 9 and the semiconductor substrate. etc. Furthermore, as described above, Δφ _TS depends on the concentration of the N-type buried layer 3, the concentration of the low-concentration N-type diffusion layers 4, 5, 6, 7, and the like. As described above, there is no consistency between V _DC and φ _R Δφ _TS in terms of integrated circuits, and adjustment is always required when considering variations in elements. Generally, a single sine wave is input and adjustments are made so that harmonic distortion in the output is minimized. This method requires manual adjustment or the use of a special adjustment jig, which increases manufacturing costs. Also as mentioned earlier
It is also difficult to design temperature compensation because there is no consistency between V _DC , φ _R , and Δφ _TS .

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bias voltage determining device that does not require adjustment of the DC bias at the input section of a charge-coupled device and always supplies an appropriate DC bias voltage.

[Summary of the invention]

The outline of the present invention is as follows. FIG. 5 shows the relationship between input voltage and injected charge in the diode cutoff method. When the input voltage is less than Vi _NL, charge of Q _MAX , which is the maximum amount of charge transferred, is always injected. It can be seen that when the input voltage is more than or equal to Vi _NL and less than Vi _NH , a charge corresponding to the input voltage is injected, and when the input voltage is more than or equal to Vi _NL and less than Vi _NH , the signal component is normally converted to charge. Also, the input voltage
When Vi _NH or higher, a charge of Q _MiN is always injected, but Q _MiN is a random charge component due to noise at the input section and can be considered to be almost zero. When the injected charge is Q _MAX or Q _MiN , the input voltage range is
It is easy to set the input voltage in advance so that the injected charge is Q _MAX or Q _MiN , which is sufficiently wide compared to fluctuations due to temperature and process variations. Using the characteristics of the input section as described above,
A first input set to inject a charge of Q _MAX and a second input set to inject a charge of Q _MiN .
By adding and distributing the charges transferred from the input section of , it becomes possible to detect the charge (Q _MAX +Q _MiN )/2 approximately at the center of the dynamic range. Furthermore, as described above, since Q _MiN is approximately zero, the same effect can be expected even if the second input section and addition section are omitted. Alternatively, since the maximum transfer charge Q _MAX of a charge-coupled device is approximately proportional to the storage gate area, a charge-coupled device with a storage gate area approximately half that of the main signal charge-coupled device can be used at an input voltage below Vi _NL . By operating it, it is possible to always detect a charge of Q _MAX /2.

A first charge-coupled device that always detects the charge at the center of the dynamic range of the charge-coupled device without being affected by fluctuation factors such as temperature and process, and a main charge-coupled device for signals by the above-described means. A second charge-coupled device having substantially equal characteristics is provided, the outputs of the first and second charge-coupled devices are compared, and negative feedback is applied to the input bias charge of the second charge-coupled device so that the outputs of the first and second charge-coupled devices match. automatically biases the second charge-coupled device approximately to the center of the dynamic range. Therefore, by setting the input bias condition of the second charge-coupled device as the input bias condition of the main charge-coupled device for signal, the main charge-coupled device for signal is always biased in the optimum state.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 6 is a block diagram showing one embodiment of the present invention. In the figure, 25 is a first charge coupled device, 35 is a second charge coupled device, 39 is a main charge coupled device for signals, 33, 38 and 42 are sample holds, and 34 is a comparator.

Here, the first charge-coupled device 25 includes a first input section 26, a second input section 27, an addition section 28, and output sections 31 and 32 of a distribution section 30. The first input section 26 is set to input charge of the maximum transfer charge amount Q _MAX , and the second input section 27 is set so that the input charge is zero. First input section 2
6 and the second input section 27 are added together in the addition section 28, transferred to the transfer section 29 with a slightly thick channel width to prevent the charge from overflowing, and further transferred to the distribution section 30. The charge is divided into two by Q _MAX /2 and transferred to output sections 31 and 32, respectively. The charge transferred to the output section 32 is converted into a voltage at the output section 32, passes through a sample hold 33, and becomes a DC voltage corresponding to Q _MAX /2. The output voltage of this sample hold 33 is input to a comparator 34 and compared with the output voltage of a sample hold 38 connected to the output section 37 of the second charge-coupled device 35.
This serves as a reference voltage when changing the bias voltage of the input section 36 of the second charge-coupled device 35 so that the output voltages 3 and 38 are equal. By the above means, the second
The input bias voltage at the input 36 of the charge-coupled device 35 is always biased to the center of the dynamic range, and by using this bias voltage as the bias voltage at the input 40 of the main signal charge-coupled device 39, The signal main charge coupled device 39 can be operated at the optimum bias without any external adjustment. Furthermore, since control is performed using feedback for disturbance factors such as temperature changes and changes over time, it is possible to maintain the optimum bias at all times.

FIG. 7 is a block diagram showing another embodiment of the present invention. In the figure, 43 is a first charge-coupled device, 49 is a second charge-coupled device, 44 and 50 are input sections, 46, 47 and 51 are output sections, 48 and 52 are sample and hold devices, and 53 is a comparator. be.

The input section 44 of the first charge-coupled device 43 is set to input charges of the maximum transfer charge amount Q _MAX . The charges transferred from the input section 44 are distributed by the distribution section 45 into charges of Q _MAX /2, respectively. This allows sample hold 4
The output of No. 8 corresponds to the charge of Q _MAX /2, that is, the charge corresponding to the center of the dynamic range of the charge-coupled device. Using the output of this sample hold 48 as a reference, the sample hold 5
Negative feedback is applied to the input section 50 of the second charge-coupled device 49 so that the two outputs are the same. By setting the input bias condition of the input section 50 as the input bias condition of the main charge-coupled device for signals, the input section of the main charge-coupled device can be operated with an optimum bias.

FIG. 8 is a block diagram showing another embodiment of the present invention. In the figure, 54 is a first charge coupled device, 59 is a second charge coupled device, 64 is a main charge coupled device for signals, 57, 61 and 68 are sample holds, and 58 is a comparator.

Here, the channel width of the input section 55 of the first charge-coupled device 54 is approximately 1/2 of the channel width of the input section and transfer section of the main charge-coupled device 64 for signals, and the input section 55 receives the maximum charge. It is set to inject. At this time, approximately
A charge of Q _MAX /2, that is, a charge approximately at the center of the dynamic range of the signal main charge coupling device 64 is input. As a result, the first charge-coupled device 5
Using the output voltage of the sample hold 57 of the second charge coupled device 59 as a reference, the comparator 58 performs a comparison so that the voltage is equal to the output voltage of the sample hold 61 of the second charge coupled device 59, and controls the variable voltage source 62. Therefore, the input 60 of the second charge-coupled device 59 is always biased to the center of the dynamic range. By supplying said bias voltage via a resistor 63 to an input 65 of a main charge coupling device 64, a signal source 67 is connected to an AC coupling capacitor 66.
The optimum bias voltage can always be applied to the signal component input via the .

Furthermore, the charge injected from the input section is measured by the difference between the potential of the input section source diffusion layer (2 in Figure 1) and the internal potential under the second gate electrode (9 in Figure 1). . Therefore, when the output of the comparator 58 is fed back to the input section of the second charge-coupled device 59 and the main charge-coupled device for signal 64, the same effect can be obtained whether the feedback destination is the input section source diffusion layer or the second gate electrode. It is clear that you can get Furthermore, in other input methods, it is also possible to feed back to either of the two potentials (corresponding to the input source diffusion layer potential and the potential under the second gate electrode described above in the diode cut-off method) that measure the charge. It is also clear that it is possible.

It should be understood that the present invention is not limited to the above embodiments, and is applicable to BBD regardless of input method, output method, surface channel type, buried channel type, number of drive phases, etc. It is.

〔Effect of the invention〕

According to the present invention, the input section of a charge-coupled device can be operated under optimal conditions without adjustment, so there is no need for a variable resistor for adjustment, which was required in the past, and it is economical and can also be used to reduce the size of the device. It has the advantage of being connected.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram showing the cross-sectional structure of the input part of the charge-coupled device and the internal potential during operation. Figure 2 is a waveform diagram showing the drive pulse waveform of the charge-coupled device. Figure 3 is the output part of the charge-coupled device. Fig. 4 is a waveform diagram showing the output waveform of the charge-coupled device, Fig. 5 is a diagram showing the characteristics of the input section of the charge-coupled device, and Fig. 6 is a schematic diagram showing the internal voltage during operation. FIG. 7 is a block diagram showing another embodiment of the invention, and FIG. 8 is a block diagram showing yet another embodiment of the invention. 25, 43 and 54... first charge coupled device, 35, 49 and 59... second charge coupled device, 34, 53 and 58... comparator, 39 and 64... main charge coupled device for signals.

Claims (1)

[Scope of Claims] 1. A highly doped N-type buried layer to which a first voltage is applied and a gate electrode placed close to the N-type buried layer and to which a second voltage is applied; 1st
A bias charge determining device for an input section of a signal charge coupling device having an input section in which the amount of bias charge is determined according to the difference between a voltage of 1 and a second voltage, the input section being supplied with a DC bias voltage. and the first
a first charge-coupled device for bias charge determination having an output section to which a sample-and-hold circuit is connected; an input section having the same structure as the input section of the charge-coupled device for signals; and a second sample-and-hold circuit. a second charge-coupled device for bias charge determination, which is connected to the first charge-coupled device and has an output section having the same structure as the output section of the first charge-coupled device for bias charge determination; and first and second sample-and-hold circuits. a comparator for comparing output signals; feedback means for feeding back the output signal of the comparator to the input section of the second charge-coupled device as a bias voltage; A bias charge determination device for a charge-coupled device, characterized in that it comprises supply means for supplying the signal to an input of the charge-coupled device.