JPH05227114A - Address counter - Google Patents

Abstract

PURPOSE:To reduce the circuit scale of an address counter and to decrease power consumption. CONSTITUTION:Two kinds of operations for self-running an address value of each channel depending on the kind of an n-multiplex signal and making it equal to the address value of channel 1 are provided on the address counter for memory write in a staff synchronous circuit which synchronizes the n- multiplex signal with the frequency of a reception part at every (n) digital signals. In this address counter, a selective signal SEL is connected to the loads of binary counters CNT2, 3 on channels 2, 3, and the output values AD1-1 to AD1-4 of a binary counter CNT1 on channel 1 are connected to the data input parts D1-D4 of the binary address counters CNT2, 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission stuff synchronization system, and more particularly to an address counter of a signal write control signal generator of a signal holding memory.

[0002]

2. Description of the Related Art In order to facilitate the explanation with respect to a conventional address counter, the explanation will be given by limiting to the number of memories 3 (3 multiplexed signals) and a 4-bit binary counter, and using FIG. 2 shown as an example. I do.

First, the types of three-multiplex signals which are memory input signals will be described with reference to FIGS. 5 and 6.
However, the 3 multiplexed signal serving as a memory input signal has a stuff bit for each channel, and the stuff information of each channel can be set independently (three channels can operate asynchronously).

First, asynchronous digital signals D1 (f1), D2 (f2), D3 (f3) as shown in FIG.
Are stuff-synchronized for each channel, and the signals D1 (f0), D2 (f0), and D3 (f3) are synchronized with the frequency f0.
A signal in which three signals are multiplexed by a triplex circuit (MUX), ...
.. Hereinafter, referred to as TYPE 1 (first digital signal).

Second, the synchronized digital signals D1 (f1) and D2 (f shown in FIG. 6 as an example.
1) and D3 (f1) are synchronized with the stuff synchronization circuit (STUFF1) with respect to D1 (f1), and D is updated by the stuff information (E) obtained by this STUFF1.
The digital signals of 2 (f1) and D3 (f1) are synchronized with the frequency f0 in the memories MEM1 and MEM2, and the signal D (3f0) is 3 multiplexed by the 3 multiplex circuit (MUX). Digital signal).

The operation of the address counter which receives the above two kinds of signals will be described with reference to FIG. AA) and TYPE1 are received, the selection signal SEL indicates "high" level, and the binary counters CNT1, CNT2, and CNT3 of each channel are addressed in synchronization with the three-phase missing clocks CLK1, CLK2, and CLK3, respectively. AD1-1-4, ADR2-1-4,
Outputs ADR3-1 to 4 and selects circuits SEL1 and SEL
2 outputs the outputs of the binary counters CNT2 and CNT3 as address values AD2-1 to AD-4 and AD3-1 to AD4. BB) and TYPE2 are received, the selection signal SEL indicates “low” level, and the selection circuit SE
L1 and SEL2 output the output of the binary counter CNT1 to the three-phase clock CLK by the timing circuits FF1 and FF2.
2, the signals AD1T to AD8T synchronized with CLK3 are selected, and the address values AD2-1 to AD4 of the channels 2 and 3 are selected.
It becomes 3-1-4.

Here, f0 to f3 in parentheses () in the signal names in FIGS. 5 and 6 mean frequencies. Further, the expected output value of the address counter has three phases in synchronization with the rising edges of the three-phase clocks CLK1 to CLK3 as shown in the time chart of FIG. Further, the operation of the clocks in each part in FIG. 2 is based on the truth table of FIGS. 3 (a) to 3 (c).

[0008]

However, the conventional address counter has a problem that the circuit scale is large and the power consumption is large because it has the timing circuit and the selection circuit.

The present invention has been made in view of the above-mentioned conventional circumstances. Therefore, an object of the present invention is to solve the above-mentioned problems inherent in the prior art and to provide a load unit of a binary counter with each channel independent. By sharing the function of selecting whether to operate or switching to the address of the channel 1 and outputting the binary counter in synchronization with the clock, the timing circuit is also shared, so that the selection circuit and the timing circuit can be shared externally. It is to provide a novel address counter that can reduce the circuit scale.

[0010]

In order to achieve the above object, an address counter according to the present invention uses an output value (address value) of a main address counter (channel 1) in cascade connection. n) is connected to the input data section and the load input section is connected to the selection signal.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the accompanying drawings, which is a preferred embodiment thereof.

FIG. 1 is a block diagram showing an embodiment of the present invention.

Referring to FIG. 1, a memory write address counter in a stuff synchronizing circuit that synchronizes an n-multiplexed signal with a frequency of a receiving section for every n digital signals is used. There are two operations to make the address value free running and to make it equal to the channel 1 address value. In this address counter, the present invention connects the selection signals SEL to the loads of the binary counters CNT2 and CNT3 of the channels 2 and 3, and outputs the output values AD1-1 to AD1-4 of the binary counter CNT1 of the channel 1 to the binary address. Data input sections D1 to D of the counters CNT2 and CNT3
Connected to 4. AA) and TYPE1 are received, the selection signal SEL indicates "high" level, and the address counters (binary counters) CNT1 to CNT3 of each channel are independent of each channel in synchronization with the three phase missing clocks CLK1 to CLK3. Address values AD1-1-4, AD2-1-4, AD3
-1 to 4 are output. BB) and TYPE2 are received, the selection signal SEL indicates the “low” level, and the address counters CNT2 and CNT3 of the two and three channels have three-phase clocks CLK2 and CLK3 because the LOAD becomes the “low” level. The output address values AD2-1 to AD4 and AD3-1 to AD4-1 of the address counters CNT2 and 3 are loaded with the output address values AD1-1 to AD1-1 to CNT1 and the three address counters output the same value. To do.
However, the change point of the address becomes three phases (as shown in FIG. 4).

The TYPEs 1 and 2 represent signals of the memory input section shown in the above-mentioned conventional example.

[0015]

As described above, according to the present invention,
The output value (address value) of the main address counter (address counter for the first channel) is input to the input data part of the cascaded address counter (address counters for the second and subsequent channels) to select the address counter itself and the timing. By using the circuit in common, the effect of reducing the circuit scale and power consumption can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a truth table of each block.

FIG. 4 is a time chart showing a phase relationship between an input clock and an output address value.

FIG. 5 is a diagram showing a transmission side of a memory input signal.

FIG. 6 is a diagram showing a transmission side of a memory input signal.

[Explanation of symbols]

FIX1 ... Fixed value ("low" level) FIX2 ... Fixed value ("high" level) CLK1-3 ... 3-phase missing clock SEL ... Selection signal AD1-1-4, AD2-1-4, AD3-1-4 ... Address value AD1T to AD8T ... Address value ADR2-1 to ADR4-1 to ADR3-1 to 4 ... Address value D1 (f1) to D3 (f3) ... Signals synchronized with frequencies f1 to f3 D1 (f1) to D3 (f1) ... signal synchronized with frequency f1 D1 (f0) to D3 (f0) ... signal synchronized with frequency f0 D (3f0) ... 3 multiple signals CNT1 to 3 address counter (binary counter) FF1, FF2 ... timing circuit SEL1 and SEL2 ... Selection circuit STUFF1 to 3 ... Stuff synchronization circuit MEM1, MEM2 ... Memory circuit MUX ... 3 multiplex circuit

Claims (1)

[Claims] 1. n different frequencies (f1 to fn)
The first digital signal or the n frequencies f1 and the second digital signal which is frame-synchronized is synchronized and multiplexed at a frequency of n × f0 by the stuff multiplexing method, and an n-multiplexed signal is output to the transmission line. An address counter, which is a memory write control signal (address) generating circuit in a stuff synchronization system, which synchronizes each n number of signals with the frequency f on the receiving side again in the receiving section of the n multiplexed signal, The selection signal of the digital signal is connected to the loads of the address counters of the channels 2 to n which are cascaded, and the address of the channel 1 selected at the time of the second digital signal is input to the data of the address counter of the channels 2 to n. Address counter characterized by being connected to a section.