JPH05226641A - High-speed semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a high-speed semiconductor device and manufacturing method thereof which makes it possible to improve high-speed operation property and maintain base resistance small by reducing the capacity between a base and a collector in a vertical high-speed semiconductor device such as HET, maintains the base resistance small, and elevates the reliability of strength. CONSTITUTION:An i-InP spacer layer 11, which is different in composition from an i-In (AlGa) As collector-barrier layer 3 and an n<+>-InGaAs collector- contact layer 2 and besides can be etched selectively and is nearly the same in area as an n<+>-InGaAs emitter layer 6 being made into a mesa shape, is interposed between these i-In (AlGa) As collector-barrier layer 3 and n<+>-InGaAs collector-contact layer existing below n<+>-InGaAs emitter layer 6 in mesa shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to hot electron transistors.
istor: HET), resonant tunneling hot electron transistor (resonant tun)
nelling hot electron trans
istor: RHET, heterojunction bipolar transistor (heterojunction bipol)
The present invention relates to improvement of a vertical high-speed semiconductor device such as an ar transistor (HBT) and a method of manufacturing the same.

At present, a high-speed semiconductor device of this kind has been realized which exhibits considerably high performance.
There are still points to be improved in terms of its high speed.

[0003]

2. Description of the Related Art FIG. 2 is a cutaway side view of an essential part of a HET for explaining a conventional example. In the figure, 1 is semi-insulating property I
nP substrate, 2 n ⁺ -InGaAs collector / contact layer, 3 i-In (AlGa) As collector / barrier layer, 4 n-InGaAs base layer, 5 i-InAl
As emitter / barrier layer, 6 is an n ⁺ -InGaAs emitter layer, 7 is an emitter electrode, 8 is a base electrode, and 9 is a collector electrode.

The following is an example of the main data relating to the illustrated parts. (1) About collector contact layer 2 Thickness: 300 [nm] Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] (2) About collector barrier layer 3 Thickness: 200 [nm]

(3) Base layer 4 thickness: 30 [nm] Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] (4) Emitter / barrier layer 5 thickness: 10 [nm]

(5) About the emitter layer 6 Thickness: 200 [nm] Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] (6) About the emitter electrode 7 Material: Cr / Au Thickness: 20 [nm] / 300 [Nm]

(7) Base electrode 8 Material: Cu / Au or AuGe / Ti / Pt / A
u Thickness: 20 [nm] / 300 [nm] (Cu / Au) 20 [nm] / 100 [nm] / 20 [nm] / 200
[Nm] (AuGe / Ti / Pt / Au) (8) About collector electrode 9 Material: Cu / Au Thickness: 20 [nm] / 300 [nm]

In the HET shown in FIG. 2, the collector barrier layer 3 made of i-In (AlGa) As is present under the base layer 4, and further the collector contact layer 2 is present under the collector barrier layer 3. However, the capacitance between the base and collector has a great influence, which hinders high-speed operation. HET that has tried to reduce the capacitance between the base and collector
Is also proposed.

FIG. 3 shows H for explaining an improved conventional example.
FIG. 3 is a cutaway side view of an essential part showing ET, and the same symbols as those used in FIG. 2 represent the same parts or have the same meanings.

In this conventional example, i-InP is used instead of i-In (AlGa) As as a material for forming the collector / barrier layer 3, and InP is compared with InGaAs when HCl is used as an etchant. By utilizing the fact that the collector barrier layer 3 can be selectively etched, side etching is performed so that the collector barrier layer 3 remains only directly under the emitter layer 6, as shown in the figure. To reduce the capacitance between the base and the collector.

[0011]

Problem to be Solved by the Invention HET seen in FIG.
In this case, the capacitance between the base and the collector is surely reduced, but the depletion layer in the base layer 4 is increased, and this causes a drawback that the base resistance is increased.

That is, even in the HET shown in FIG.
Also in the HET shown in FIG. 3, a depletion layer is formed on the surface of the base layer 4 in the vicinity of the contact with the base electrode 8, but in the HET shown in FIG.
Since the depletion layer is also formed on the back surface of the base layer 4 below the base electrode 8, the base resistance increases.

Moreover, apart from the problem of the base resistance,
The base layer 4 has a thickness of 30 as described above.
Since it is extremely thin at about [nm], it has low rigidity, and if there is a large void below it, it will be easily broken due to impact, and the tip will fall and the collector layer 2 And an accident that short circuit occurs.

The present invention can improve the high-speed operability by reducing the base-collector capacitance in a vertical type high-speed semiconductor device such as HET, and can keep the base resistance small, and at the same time, the strength can be improved. I try to be able to improve the reliability.

[0015]

In a high-speed semiconductor device and a method of manufacturing the same according to the present invention, (1) a mesa-emitter emitter layer (for example, n ⁺ -InGa) is used.
A collector barrier layer (eg, i-In (AlGa) As collector barrier layer 3) and a collector contact layer (eg, n ⁺ -InGa) below the As emitter layer 6).
It is composed of a material having a composition different from that of the collector-barrier layer and the collector-contact layer between the As collector-contact layer 2) and selectively etchable, and has substantially the same area as the mesa-emitter layer. A spacer layer (for example, i-InP spacer layer 11) is interposed, or

(2) A collector layer (eg, n-InGaAs or n-I) below the mesa-emitter layer.
nAlAs) and a collector contact layer (for example, n-InGaAs) between the collector layer and the collector contact layer having a different composition and selectively etchable material. Or a spacer layer (for example, made of i-InP) having substantially the same area as the mesa-shaped emitter layer is interposed.

(3) Collector / contact layer (for example, n
⁺ −InGaAs collector / contact layer 2) and a collector / barrier layer (for example, i-In (AlGa) As collector / barrier layer 3), which are different in composition from the collector / contact layer and the collector / barrier layer. In addition, a required semiconductor layer (for example, n ⁺ -InGaAs collector / contact layer 2, i-InP spacer layer 11, i-) including a spacer layer (for example, i-InP spacer layer 11) composed of a material that can be selectively etched. In (AlGa)
As collector / barrier layer 3, n-InGaAs base layer 4, i-InAlAs emitter / barrier layer 5, n ⁺ -I
nGaAs emitter layer 6) and the like,
From the emitter layer (n ⁺ -InGaAs emitter layer 6) on the front surface side to the collector contact layer (n ⁺ -InGaA)
s collector / contact layer 2) to reach the base electrode contact region (n-In).
A part of the GaAs base layer 4) and a collector electrode contact region (a part of the n ⁺ -InGaAs collector / contact layer 2) are exposed, and then the spacer layer (i-
Or a step of selectively side-etching only the InP spacer layer 11) so as to have substantially the same area as the mesa-shaped emitter layer (n ⁺ -InGaAs emitter layer 6), or ,

(4) Collector / contact layer (for example, n
-InGaAs) and collector layer (eg n)
-InGaAs or n-InAlAs)
A desired semiconductor layer including a collector contact layer and a spacer layer (for example, made of i-InP) which is interposed between the collector contact layer and the collector layer and has a composition different from that of the collector layer and is made of a material which can be selectively etched. The step of forming a stack and stepwise mesa etching from the emitter layer on the surface side to the collector contact layer are performed to expose the base electrode contact region and collector electrode contact region respectively, and then only the spacer layer is selectively formed. And a step of side etching to make the area approximately the same as the mesa-shaped emitter layer.

[0019]

By adopting the above means, the base-collector capacitance existing directly under the base electrode can be sufficiently reduced, and further, the depletion layer extends from both the front and back surfaces of the base layer to increase the base resistance. Since there is nothing, it is possible to further speed up HET and the like, and there is no structure in which only the thin base layer floats in the air alone, and the rigidity of the part where the base is empty becomes high. Therefore, the problem that the base layer is broken due to impact or vibration is solved, and a highly reliable high-speed semiconductor device can be manufactured with high yield.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional side view of an essential part showing a HET which is a kind of high speed semiconductor device for explaining an embodiment of the present invention. The same symbols as those used in FIGS. They represent the same part or have the same meaning. In the figure, 11 is a thin i-I having a thickness of, for example, about 10 nm.
The nP spacer layer is shown.

As described above, even if the spacer layer is interposed between the collector contact layer 2 and the collector barrier layer 3,
The operation as HET is the same. That is, InGaA
energy of the conduction band between s and In (AlGa) As
The band discontinuity value is about 0.25 [eV], and InGa
0.22 [eV] to 0.2 as a discontinuous value between As and InP
It is almost equal to 5 [eV], and does not pose any problem in terms of operation as a HET.

The HET of this embodiment can be manufactured by the steps which are almost the same as those of the conventional HET, and therefore will be briefly described below. (1) Gas-source molecular beam epitaxial growth (ga
s source molecular beam e
Pitaxy: GS-MBE) method is applied to form n ⁺ -InGaAs collector / contact layer 2 i-InP spacer layer 11 In (AlGa) As collector / barrier layer 3 n-InGaAs on the semi-insulating InP substrate 1. A base layer 4 i-InAlAs emitter / barrier layer 5 n ⁺ -InGaAs emitter layer 6 is grown. The thickness of the i-InP spacer layer 11 is 10 [nm], and the data regarding each of the other semiconductor layers is the same as the conventional example described with reference to FIGS. 2 and 3. In addition, the GS-MBE method uses metal organic chemical vapor deposition (m
etalorganic chemical vapor
ur deposition (MOCVD) method may be substituted.

(2) The wafer in which the emitter layer 6 is exposed is subjected to a stepwise mesa etching by applying a usual technique to the electrode contact region of the base layer 4 and the collector contact. The electrode contact area of layer 2 is exposed.

(3) By applying a wet etching method using an HCl aqueous solution as an etchant, i-
The InP spacer layer 11 is side-etched to remove the remaining mesa-shaped region facing the emitter layer 6 and the rest.

(4) The emitter electrode 7, the base electrode 8 and the collector electrode 9 are formed by applying a resist process, a vacuum evaporation method, and a lift-off method in a general lithography technique.

As described above, the high-speed semiconductor device according to the present invention can be easily manufactured, and the side etching of the i-InP spacer layer 11 in the step (3) is performed by controlling the time. , HCl aqueous solution etches InP but not InGaAs or InAlAs, so that it is easy to obtain the configuration shown in FIG.

As is apparent from the above description, the collector-barrier layer 3 and the collector-contact layer 2 below the base electrode 8 are separated, and the base-collector capacitance is reduced. In the case of ion implantation or alloying, the collector-base layer 3 and the collector contact layer 2 are separated from each other, so that the collector-base breakdown voltage is not likely to decrease.

In the above-mentioned embodiment, the description has been made for the HET, but the same can be applied to the RHET and the HBT. For example, in HBT, an n-InGaAs collector layer or an n-InAlAs collector layer, ap ⁺ -InGaA layer on the n-InGaAs collector contact layer.
s base layer, n-InAlAs emitter layer, n ⁺ -In
It has a structure in which a GaAs emitter contact layer is laminated, and the capacitance between the base and collector is HET.
Although it has the same problem as RHET and RHET, i-I
A spacer layer made of nP is used as an n-InGaAs collector.
Contact layer and n-InGaAs or n-InAlA
The same effect can be obtained by interposing it with the s collector layer and by making the area of the spacer layer about the same as that of the mesa-emitter layer.

[0029]

In the high-speed semiconductor device and the method of manufacturing the same according to the present invention, in the case of HET or RHET, it is between the collector-barrier layer and the collector-contact layer below the mesa-shaped emitter layer. A spacer layer having a composition different from those of the above and selectively etchable material and having substantially the same area as the mesa-shaped emitter layer is interposed, and in the case of HBT, the mesa-shaped emitter layer is formed. A spacer layer having a composition different from that of the collector layer and a collector-collector layer below and made of a material capable of being selectively etched and having substantially the same area as the mesa-shaped emitter layer is interposed between the collector layer and the collector-collector layer. Has been inserted.

By adopting the above-mentioned structure, the base-collector capacitance existing immediately below the base electrode can be sufficiently reduced, and further, the depletion layer extends from both the front and back surfaces of the base layer to increase the base resistance. H is because there is no
ET etc. can be further speeded up, and there is no structure in which only the thin base layer is suspended in the air.
Since the rigidity of the portion where the base is vacant is high, the problem that the base layer is broken due to impact or vibration is solved, and a highly reliable high-speed semiconductor device can be manufactured with high yield.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an essential part of a HET, which is a kind of high-speed semiconductor device, for explaining an embodiment of the present invention.

FIG. 2 is a cutaway side view of a main part showing a HET for explaining a conventional example.

FIG. 3 is a side sectional view showing a main part of a HET for explaining an improved conventional example.

[Explanation of symbols]

1 Semi-insulating InP substrate 2 n ⁺ -InGaAs collector / contact layer 3 i-In (AlGa) As collector / barrier layer 4 n-InGaAs base layer 5 i-InAlAs emitter / barrier layer 6 n ⁺ -InGaAs emitter layer 7 Emitter Electrode 8 Base electrode 9 Collector electrode 11 i-InP spacer layer

Claims (4)

[Claims] 1. A collector barrier layer and a collector contact layer below the mesa-emitter layer and between the collector barrier layer and the collector contact layer are different in composition from the collector barrier layer and can be selectively etched. A high-speed semiconductor that operates as a hot electron transistor or a resonant tunneling hot electron transistor, characterized in that a spacer layer that is made of a material and has substantially the same area as the mesa-emitter layer is interposed. apparatus. 2. A collector layer between the collector layer and the collector contact layer below the mesa-emitter layer and a collector contact layer and a material different in composition from the collector contact layer and selectively etchable. A high-speed semiconductor device that operates as a heterojunction bipolar transistor, characterized in that a spacer layer having substantially the same area as the mesa-shaped emitter layer is interposed. 3. A spacer layer interposed between the collector contact layer and the collector barrier layer, the spacer layer having a composition different from that of the collector contact layer and the collector barrier layer and made of a material which can be selectively etched. Including the step of forming required semiconductor layers, and exposing the base electrode contact region and collector electrode contact region by performing stepwise mesa etching from the emitter layer on the surface side to the collector contact layer. And a step of selectively side-etching only the spacer layer so as to have approximately the same area as that of the mesa-emittered emitter layer. 4. A required semiconductor including a collector contact layer interposed between collector contact layers and a spacer layer composed of a material having a composition different from that of the collector layer and selectively etchable. Layer formation process and stepwise mesa etching from the emitter layer on the surface side to the collector contact layer to expose the base electrode contact region and collector electrode contact region respectively, and then select only the spacer layer Side etching is performed so as to have substantially the same area as that of the mesa-emittered emitter layer, and a method for manufacturing a high-speed semiconductor device.