JPH05226619A - Semiconductor integrated circuit device and delay time programming - Google Patents

Abstract

PURPOSE:To provide a delay circuit wherein a desired delay time can be set with small number of MOSTr's by doping a part of a channel to such a degree that a semiconductor integrated circuit device may have such a high threshold voltage that it may not operate at the line voltage and by controlling the effec tive transistor width. CONSTITUTION:Phosphorus or arsenic is injected by ion implantation into a slant-line part 'a' of a PMOS transistor 2 and boron is injected by ion implantation into a slant-line part 'b' of an NMOS transistor 4 and then a channel threshold voltage of the slant parts comes to about 6V and therefore the device comes not to work at the 5V line voltage and then the effective transistor width becomes smaller. Thus, the effective transistor width of the PM0STr 2 and of the NMOSTr 4 is changed due to channel doping and therefore a delay can be made by a one-stage inverter of the PMOSTr 2 and the NM0STr 4. A delay time can be set continuously according to the size of a channel doping region shown by slant lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a master slice type semiconductor integrated circuit device in which a plurality of basic cells including MOS transistors are regularly arranged. For example, a delay circuit, a RAM sense amplifier, a MOS gate array,
MOS composite gate array (semiconductor integrated circuit device in which a part of the semiconductor chip has a gate array structure), P-channel MOS transistor (hereinafter referred to as PMOS) in the basic cell
The present invention relates to a CMOS type or BiCMOS type master slice type semiconductor integrated circuit device including an N-channel type MOS transistor (hereinafter referred to as an NMOS transistor) and an N-channel type MOS transistor.

[0002]

2. Description of the Related Art As a delay circuit used in a semiconductor integrated circuit device, there are various circuits as shown in FIG.
(A) shows an example in which an RC delay circuit is constituted by a capacitor C and a resistor R, and (a) shows it by a circuit diagram using MOS transistors. The example of (B) and the circuit diagram (b) of the MOS transistor thereof is an example of configuring a delay circuit by using the propagation time of a logic gate. In this case, the transistor size is designed so that the predetermined delay time is obtained. The example of (C) and its CMOS circuit (c) is an example applied to a master slice type semiconductor integrated circuit, in which a large number of MOS transistors having the same pattern are arranged in advance and a desired logic circuit is formed by metal wiring. This constitutes a delay circuit.

When designing a semiconductor integrated circuit device, there is a relation that current consumption increases as the operating speed is increased. Therefore, it is necessary to adjust the current supply capability of each transistor in consideration of both speed and current consumption. In the master slice type semiconductor integrated circuit device, a plurality of MOS transistors are connected to adjust the current supply capacity. FIG. 3 shows an example thereof, and FIG. 3A shows one basic cell which is the basis. N1 is an input, N2 is an output, and N3 is a gate. Assuming that the current amount in (A) is 1, it is assumed that two basic cells are used and the wiring is connected as shown in (B) in order to construct a circuit capable of passing half the current. Also, in order to allow 1.5 times the basic current to flow, (C)
6 basic cells are connected by metal wiring as shown in FIG.

[0004]

In the example of the delay circuit, when the RC delay circuit is constructed as shown in FIG. 1 (A), the design must be made according to the delay time. When the delay time of the logic gate is used as in (B), the delay time is determined in the initial design stage and cannot be changed in the subsequent stages.

In the method of connecting a large number of MOS transistors by metal wiring as shown in FIG. 1C, it is impossible to newly add an RC element to form a delay circuit, and the basic MOS transistor size is Since it is determined in advance and the size is determined for the logic gate, a large number of MOS transistors are required and the circuit scale increases. For example, as shown in FIG.
When a delay circuit is configured by connecting inverters composed of OS and NMOS in multiple stages, both PMOS and NMOS have a transistor width of 10 μm and a channel length of 1 μm.
Therefore, the delay time is about 0.5 ns per logic gate, and therefore, in order to construct a delay circuit requiring a delay of 10 ns, 20 stages of logic gates must be connected. Moreover, the delay time can only be adjusted in 0.5 ns increments. As described above, the conventional delay circuit has a problem that the circuit scale becomes large due to the size of the delay and a problem that the delay time cannot be continuously set.

Therefore, the first object of the present invention is to reduce M
It is an object of the present invention to provide a delay circuit which is an OS transistor and can set an arbitrary delay time. A second object of the present invention is to provide a programming method capable of freely setting a delay time after forming a desired logic circuit.

Regarding the current supply capability, if an attempt is made to obtain a desired current supply capability in a master slice type semiconductor integrated circuit device, there is a problem that the number of gates used increases as shown in FIG. Therefore, a third object of the present invention is to reduce the number of gates used and realize an arbitrary current supply capability. A fourth object of the present invention is to set the current supply capacity of the sense amplifier of RAM to a predetermined value.

[0008]

In order to set an arbitrary delay time, the present invention includes at least one delay circuit.
By delaying the delay time by adjusting the effective transistor width of each MOS transistor by channel-doping a part of the channel of each MOS transistor to a threshold voltage that does not operate at the power supply voltage of the semiconductor integrated circuit device. adjust.

In order to set an arbitrary current supply capability, in the present invention, a part of the channel of the MOS transistor is channel-doped to such an extent that the threshold voltage does not operate at the power supply voltage of the semiconductor integrated circuit device. By adjusting the effective transistor width of the MOS transistor, the current supply capacity of the MOS transistor is adjusted. RAM
In the same manner, in the sense amplifier described in (1), a part of the channel of at least one MOS transistor included in the sense amplifier is channel-doped to such an extent that the threshold voltage does not operate at the power supply voltage of the semiconductor integrated circuit device. The effective transistor width of the MOS transistor is adjusted to adjust the current supply capacity of the MOS transistor.

[0010]

When the MOS transistor is ion-implanted for channel doping, the NMOS transistor is implanted with boron at a dose of 1 × 10 ^{12 to} 3 × 10 ¹² / cm ² and an acceleration energy of about 30 KeV.
The threshold voltage of the transistor is 0.7 to 1.0 V, but the ion implantation amount is 4 × 10 ^{13 to} 5 × 10 ¹³ / cm ² ,
If the acceleration energy is about 180 KeV, the NMO
The threshold voltage of the S transistor becomes about 6V, and the latter NMOS transistor does not operate at the power supply voltage of 5V normally used for the operation of the semiconductor integrated circuit device.

Similarly, in a PMOS transistor, when phosphorus or arsenic is ion-implanted into a channel, the implantation amount is 1
0 ¹⁰ to 10 ¹³ / cm ² , acceleration energy 100 to 20
When it is set to 0 KeV, the threshold voltage of the PMOS transistor becomes about 6V, and the PMOS transistor cannot operate with a 5V power supply.

If a part of the channel of a certain MOS transistor included in the delay circuit is subjected to ion implantation (channel doping) for increasing the threshold voltage as described above, the MO of the channel is increased.
The effective transistor width of the S-transistor becomes narrow and the delay time changes. Further, if the effective transistor width is reduced by the above-mentioned ion implantation, the current supply amount is reduced. The effective transistor width can be continuously set to an arbitrary value by changing the ratio of the channel doping for increasing the threshold voltage with respect to the entire channel width.

[0013]

FIG. 4 shows an embodiment in which the present invention is applied to a delay circuit. As shown by the solid line, the PMOS transistor 2 and the NMOS transistor 4 are metal-wired to form a CMOS inverter, and the PMOS transistor 6 and the NMOS transistor 8 are also metal-wired to form a CMOS inverter. These two inverters are connected in series by metal wiring to form a delay circuit. The power supply voltage Vcc is, for example, 5V.

In the PMOS transistor 2, phosphorus or arsenic is implanted into the shaded portion a of 10 ¹⁰ to 10 ¹³
/ Cm ² , and the acceleration energy is 100 to 200 KeV, the ion implantation is performed, the threshold voltage of the shaded channel becomes about 6 V, and the device does not operate with a 5 V power supply, and the effective transistor width is narrowed. In the NMOS transistor 4, boron is ion-implanted into the shaded portion b with an implantation amount of 4 × 10 ^{13 to} 5 × 10 ¹³ / cm ² and an acceleration energy of about 180 KeV, and the threshold value of the channel in the shaded portion The voltage becomes about 6V and the device does not operate with a 5V power supply, and the effective transistor width is narrowed. In this way, the PMOS transistors 2 and N
The effective transistor width of the MOS transistor 4 is changed by channel doping, and the conventional delay of 10 ns shown in FIG. 2 can be realized by the one-stage inverter including the PMOS transistor 2 and the NMOS transistor 4. Further, the delay time can be continuously set by the size of the channel dope region shown by the diagonal lines.

The channel dope can be programmed after the MOS transistor is completed. Therefore, the delay time can be adjusted in the subsequent process. The delay circuit shown in FIG. 4 has a large number of MOS transistors with a preset transistor size.
This is particularly effective in a master slice type semiconductor device in which transistors are arranged.

FIG. 5 shows the MO of the present invention in which the current supply amount is adjusted.
An example applied to an S transistor is shown. In (A), for the P-type or N-type MOS transistor 10, a threshold voltage is applied to a power supply voltage (for example, 5
V), by performing channel doping to make it higher than
Change the transistor width of the MOS transistor,
This changes the current supply capacity. 3A is an example in which the current supply capacity is halved corresponding to FIG. 3B, and what has conventionally required two basic cells is realized by one basic cell. .

FIG. 5B shows the MOS transistors 12 and 1.
4, the MOS transistor 14 is channel-doped so that the threshold voltage becomes higher than the power supply voltage (for example, 5 V) in the shaded portion d so that the transistor width of the MOS transistor 14 becomes 1/2,
By providing metal wiring (shown by the solid line) to the MOS transistors 12 and 14 as shown in the figure, a current supply capacity 3/2 times that of the basic cell is realized. Conventionally, six basic cells are required as shown in FIG. 3C, but FIG.
In (B), it can be realized by two basic cells.

FIG. 6 shows an SR of the present invention for adjusting the current supply capacity.
An example applied to a current mirror type sense amplifier of AM will be described. A region 16 surrounded by a broken line represents a memory cell, and a region 18 surrounded by a broken line represents a sense amplifier. This sense amplifier 18 transmits bit lines BL and BLB (last B
Is a circuit for sensing and amplifying the potential difference (representing an inverted signal). According to the present invention, the MOS transistors M1 to M5 forming the sense amplifier 18 have their channel widths adjusted by channel-doping some of their channels so that the threshold voltage is equal to or higher than the power supply voltage. Generally, if the transistor width is increased to allow a large current to flow, detection can be performed at high speed, but the current consumption also increases. Therefore, the MOS transistors M1 to M5 have their transistor widths adjusted by ion implantation depending on the balance between operating speed and current consumption. Therefore, fine adjustment is possible with the minimum number of used gates. If an attempt is made to adjust the current supply capacity by the conventional master slice method, a large number of basic cells will be needed and the circuit scale will increase. MO
The present invention in which a part of the channel of the S transistor is ion-implanted to change the effective transistor width to adjust the current supply capability can be applied not only to the sense amplifier shown in FIG. 6 but also to various circuits. .

[0019]

In the delay circuit of the present invention, R is newly added for delay.
A desired delay time can be realized without adding the C element. Further, when it is realized by a logic gate, a desired delay time can be realized without increasing the number of stages of the logic gate, so that the circuit scale can be reduced and an arbitrary delay time can be set. It is possible to program at an arbitrary delay time even in the later steps such as design and layout. According to the present invention, the current supply capability of each MOS transistor can be adjusted to an arbitrary value, so that a circuit can be realized with the minimum number of used gates. The present invention can be applied to a custom semiconductor integrated circuit device, of course, but is particularly effective in a master slice type semiconductor integrated circuit device because the number of used gates is small.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional delay circuit.

FIG. 2 is a schematic plan view showing a conventional master slice delay circuit.

FIG. 3 is a schematic plan view showing a method of adjusting a current supply force by a conventional master slice method.

FIG. 4 is a schematic plan view showing a delay circuit according to an embodiment.

FIG. 5 is a schematic plan view showing a circuit in which the current supply capacity is adjusted according to one embodiment.

FIG. 6 is a circuit diagram showing a sense amplifier of an SRAM which is an application example of the present invention.

[Explanation of symbols]

2, 4, 6, 8, 10, 12, 12, 14 MOS transistor 16 Memory cell 18 Sense amplifier

Claims (4)

[Claims] 1. At least one M included in the delay circuit.
The delay time is delayed by adjusting the effective transistor width of the MOS transistor by channel-doping a part of the channel of the OS transistor to a threshold voltage that does not operate at the power supply voltage of the semiconductor integrated circuit device. The semiconductor integrated circuit device is characterized by being adjusted. 2. A channel doping is applied to a part of the channel of the MOS transistor to such an extent that the threshold voltage does not operate at the power supply voltage of the semiconductor integrated circuit device, and the MO is formed.
A delay time programming method comprising adjusting an effective transistor width of an S transistor to program an arbitrary delay time. 3. A channel doping is applied to a part of the channel of the MOS transistor to such an extent that the threshold voltage does not operate at the power supply voltage of the semiconductor integrated circuit device.
A semiconductor integrated circuit device characterized in that the current supply capacity of the MOS transistor is adjusted by adjusting the effective transistor width of the OS transistor. 4. A sense amplifier of a RAM is included, and at least one of the channels of at least one MOS transistor included in the sense amplifier has a channel to such an extent that the threshold voltage does not operate at the power supply voltage of the semiconductor integrated circuit device. A semiconductor integrated circuit device characterized in that a current supply capability of the MOS transistor is adjusted by being doped to adjust the effective transistor width of the MOS transistor.