JPH05225780A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To easily realize large capacity and low power consumption of a device by providing level conversion means which converts the low side level of a bit line to a higher value than that of the low side level of a word line. CONSTITUTION:This device is provided with a level conversion means 12 consisting of transistors Tr8, Tr9 which converts the low side level of bit lines BLZ and BLX to a higher value than that of the low side level of word lines WLphi, WL1, on bit lines BLZ and BLX connected to cells 1a and 1b. Therefore, low side charge stored in a storage capacitors C1 and C2 becomes larger than the low side level of the word line. Owing to the fact, leakage of the storage capacitors via selecting transistors Tr1 and Tr2 do not occur if word lines WL and WL1 are not raised higher than the low side level of the bit line. Therefore, a substrate bias generator is not required, and instead of it, increasing of current consumption can be prevented, while large capacity can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device for storing information by charging / discharging a storage capacitor with a selection transistor.

In recent years, DRAM is required to have low power consumption during operation and standby.

Therefore, it is necessary to reduce the charging / discharging current and delete unnecessary operation circuits as much as possible without reducing the operation margin.

[0004]

2. Description of the Related Art FIG. 4 is a block diagram of a general DRAM. The DRAM includes a memory cell unit 1 that holds data, an address buffer 2a, a predecoder 2b for selecting cells according to an input address signal, a row decoder 3, a column decoder 4a, a sense amplifier 4b, a data input buffer 5, and a data output buffer. 6, a refresh address counter 7 for designating cells to be refreshed,
A mode controller 8, clock generators 9a, 9b, 9c for generating various timing signals, and a substrate bias generator 10 for applying a bias voltage to the substrate.
Etc.

FIG. 5 shows a circuit diagram around a conventional memory cell array. In the figure, 1 indicates a memory cell array.

The memory cell array 1 has bit lines BL_z, B
L_x… And word line WL₀, WL ₁Connected to
It is composed of a plurality of memory cells 1a, 1b, ....

The memory cells 1a and 1b have a storage capacitance C.₁, C
₂, Selection transistor Tr₁, Tr ₂Is made up of
It

The bit lines BL _z and BL _x are connected to the sense amplifier 4
connected to b. Sense amplifier 4b is word line B
L _x ,, BL _z is selected by the row decoder 3 connected to the memory cell 1a, amplifies the output of 1b.

The bit lines BL _z and BL _x are N-channel MOSFETs Tr ₆ and T constituting the row decoder 4a.
The data bus lines DB _x and DB _z are connected via r ₇ .

Reference numeral 13 represents a balancing circuit. The balancing circuit 13 is an N-channel MOSFSTTR ₃ , Tr ₄ , Tr
₅ and holds the bit lines BL _x and BL _z at the balanced voltage V _PR during standby.

As shown in FIG. 6, in the conventional circuit, the level of the bit line is oscillated from the low side level NSA = V _SS to the high side level PSA = V _CC or the step-down level of V _CC . Also, the substrate bias generator 10 is used to make the substrate voltage V _BB negative and the selection transistor T
The V _th of r ₁ is increased to prevent the leak between the storage capacitor and the bit line via the select transistor Tr ₁ .

[0012]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In AM, cell storage capacitances C ₁ and C ₂ and bit lines BL _z and B
The substrate bias generator 10 makes the substrate voltage V _BB negative so as to prevent the leak between L _x through the select transistors Tr ₁ and Tr ₂ . However, as the capacity of DRAM increases, a smaller value is required for charging and discharging the bit line, and it is necessary to operate the substrate bias generator. This substrate bias generator serves as a barrier to lower power consumption. It was

Further, if the number of cells increases and the substrate current I _BB increases, which exceeds the current absorption capability of the substrate bias generator, the increase in the substrate bias voltage causes leakage of the select transistor and other malfunctions of the circuit. There was a problem.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device capable of easily realizing a large capacity and a low power consumption without causing a reduction in an operation margin. ..

[0015]

According to the present invention, a bit line is connected to a storage capacitor via a selection transistor, and the selection transistor is switched by a word line drive signal supplied to the word line to thereby control the bit line. A semiconductor memory device which supplies a generated information signal to a sense amplifier to read information is provided with level conversion means for converting the low level of the bit line to a value higher than the low level of the word line.

[0016]

According to the present invention, since the low-side level of the bit line is set to a value higher than the low-side level of the word line by the level converting means, the low-side charge accumulated in the storage capacitor is also set to the low-side of the word line. Greater than level. Therefore, if the word line does not float above the low level of the bit line, the storage capacity leak via the select transistor does not occur.

Therefore, even if the level of the word line slightly rises due to noise or the like, malfunction does not occur as long as it is below the low level of the bit line.

[0018]

1 is a circuit diagram of an embodiment of the present invention. In the figure, 1 is a cell array, and cell array 1 is a plurality of cells 1.
It is formed by arranging a and 1b.

One cell 1a comprises a storage capacitor C ₁ and a selection transistor Tr ₁ . Further, another cell 1b adjacent to it also has a storage capacitor C ₂ and a selection transistor Tr ₂ like the cell 1a.

Select transistor Tr forming cell 1a
Reference numeral ₁ is an N-channel MOSFET, the gate of which is connected to the word line WL ₀ , the drain of which is connected to the storage capacitance C ₁ and the source of which is connected to the bit line BL _z .

The selection transistor Tr ₂ constituting the cell 1b is composed of an N-channel MOSFET,
Its gate is connected to the word line WL ₁ , its drain is connected to the storage capacitor C ₂ , and its source is connected to the bit line BL _x .

A row decoder 3 is a NAND gate 3a,
Inverter 3n, N-channel MOSFET Tr _{14 to} T
r ₁₆ is connected to the word lines WL ₀ and WL ₁ , respectively, and the FETs Tr ₁₄ to Tr ₁₆ are switching-controlled according to the address signal input to the NAND gate to select the word lines WL ₀ and WL _1. It

Reference numeral 4b represents a sense amplifier. The sense amplifier 4b is made of N-channel MOSFET Tr _11, Tr _13, P-channel MOSFET Tr _10, Tr _12, the bit line BL _z, is connected between the BL _x. In addition, the sense amplifier 4b receives the activation signals PSA,
The activation signal generation circuit 11 which is supplied with NSA and amplifies in accordance with the activation signals PSA and NSA is a P-channel MO.
SFET Tr ₁₇ , Tr ₁₈ , N-channel MOSFET
It consists of Tr ₁₉ and Tr ₂₀ .

Reference numeral 12 represents a level converting means. The level converting means 12 is composed of P-channel MOSFETs Tr ₈ and Tr ₉ .

The FET Tr ₈ is connected between the bit line BL _z and the sense amplifier 4b, and the FET Tr ₉ is connected between the bit line BL _x and the sense amplifier 4b. FE
The ground potential V _SS is applied to the gates of TTr ₈ and Tr ₉ .

The bit line B is formed by the FETs Tr ₈ and Tr _9.
L _x and BL _z are low level outputs V _SS of the sense amplifier 4b
Becomes a voltage (V _SS + V _th ) raised by the threshold voltage V _th of the FETs Tr ₈ and Tr ₉ .

By providing the level converting means 12, P
Channel MOSFET Tr₈, Tr₉Is the bit line BL
_z, BL_xThe low-side amplitude of P-channel FET Tr
V_thIt can be reduced to 1 or less. Because of this, activation
Signal PSA is bias potential V _cdOr blood pressure level, activity
Signal NSA is ground potential V_SSI am trying to become. Obey
The node SA of the sense amplifier 4b_zAnd node SA_xIs
Bias potential V_CCOr step-down level and ground potential
V_SSIs amplified between. Therefore, the information is FET Tr
₆, Tr₇Data bus line DB via_z, DB_xOutput to
Therefore, the ground potential V_SSInformation is output
It Also, the back via of the FET Tr that constitutes the circuit
All N channels are ground potential V_SS, P-channel lotus
All bias potential V_CCAnd the substrate bias
You don't need a nerator

The ground potential V is set by the FETs Tr ₈ and Tr _9.
SS rises by the threshold voltage V _{th of the} FETs Tr ₈ and Tr ₉ , and as a result, the low-side level of the bit lines BL _z and BL _x becomes FET Tr ₂ as shown in FIG.
Threshold voltage V _th .

Therefore, the low level of the bit lines BL _z and BL _x becomes higher than the low level of the word lines WL ₀ and LW ₁ . Therefore, even if the word lines WL ₀ and WL ₁ rise to a low level (non-operation) due to noise or the like, the bit lines BL _z and BL _x do not exceed the low level, and malfunction does not easily occur.

Further, the substrate because it has a structure which is directly connected to the ground potential V _SS, noise generated in the substrate is absorbed by the ground potential V _SS, it can minimize noise.

FIG. 3 shows a circuit diagram of another embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted.

In this embodiment, the gate of the FET Tr ₁₉ is provided between the ground potential V _SS and the FET Tr ₁₉ which serves as a circuit for generating the low level side activation signal NSA of the activation signal generation means 11 by the level conversion means 12. An N-channel MOSFET Tr ₂₁ connected to the source is provided.

FET Tr_{twenty one}Ground potential V_SSIs FE
T Tr_{twenty one}Threshold voltage V _thOnly rise this
Along with the bit line BL_z, BL_xLow side level is F
ETTr_{twenty one}Threshold voltage V_thIt rises by a minute.

Therefore, the bit line is the same as the embodiment shown in FIG.
BL_z, BL_xLow level is word line WL₀, WL₁
Higher than the low level of. Therefore, the word line W
L₀, LW₁Is at low level (when not operating)
Bit line BL _z, BL_xLorebe
Since it will not cross the
It

With such a structure, the number of FETs is 1
Therefore, the number of elements can be reduced.

[0036]

As described above, according to the present invention, since the low level of the bit line becomes larger than the low level of the word line, the accumulated charge in the storage capacitor leaks through the selection transistor. And the substrate bias generator becomes unnecessary. Therefore, it is possible to prevent leakage and increase in current consumption due to the substrate bias generator, and it is possible to prevent malfunction of the circuit due to floating of the substrate voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the embodiment of the present invention.

FIG. 3 is a circuit diagram of another embodiment of the present invention.

FIG. 4 is a block diagram of a DRAM.

FIG. 5 is a circuit diagram of a conventional example.

FIG. 6 is a diagram for explaining an operation of a conventional example.

[Explanation of symbols]

1 cell array 4b sense amplifier 11 activation signal generation means 12 level conversion means V _CC bias potential V _SS ground potential

Claims (3)

[Claims] 1. A bit line (BL_x, BL_z) Is the selected tiger
Register (Q₁, Q ₂) Via the storage capacity (C₁，
C₂) Is connected to the word line (W
L₀, WL₁The word line drive signal supplied to
The bit line (BL_x, BL
_z), The information signal generated in
A bit line (BL_z, BL_x) Low side level
Word line (WL₀, WL₁) Greater than the low side level
It has a level conversion means (12) for converting it into a value.
Semiconductor memory device. 2. The level conversion means (12) includes the selection transistors (Q ₁ , Q ₂ ) and the sense amplifier (4).
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the bit line (BL _x , BL _z ) between and. 3. The semiconductor memory device according to claim 1, wherein the level conversion means (12) is provided in a drive circuit (11) that determines an output signal level of the sense amplifier (4b).