JPH05225119A - Signal level detection system - Google Patents

Abstract

PURPOSE:To provide the signal level detection system which can improve the capability of control processing of an input signal by speeding up processing as to a signal level detection system which inputs signals from plural channels and detects variation in signal level. CONSTITUTION:This system consists of a CPU 1, a memory 4 which is stored temporarily with data, a scan part 5 which fetches the signals from the channels while scanning them, a timer 6 which supplies a scanning period to the scan part 5, a data control part 10 which receives the period signal from the timer 6 and controls data transmission, a 1st data transfer control part 11 which holds data read out of the memory 4, a 2nd data transfer holding part 12 which holds the data from the scan part 5, and a data comparison arithmetic processing part 13 which reads the data out of the 1st and 2nd data transfer holding parts 10 and 11, performs the data comparison arithmetic processing, and supplies the result to the data transfer control part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal level detecting system for inputting signals from a plurality of channels and detecting a change in signal level.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional system. In the figure, 1 is a CPU, 2 is the CPU
A bus to which 1 is connected, 3 is a first memory for storing a control program and the like, and 4 is a second memory for temporarily holding data. For example, a ROM is used as the first memory 3 (hereinafter abbreviated as the memory 1), and a RAM is used as the second memory 4 (hereinafter simply referred to as the memory 2). Reference numeral 5 is a scanning unit that scans and captures signals of a plurality of channels from CH1 to CHn, and 6 is a timer that sets a scanning cycle.

FIG. 5 is a flow chart showing the operation of the conventional system. The operation of the system shown in FIG. 4 will be described with reference to this flowchart. In the figure, the part surrounded by the broken line shows the change detection processing routine.

Now, it is assumed that the timer 6 gives the periodic signal of the nth period. As a result, the input signal of the channel is read from the scanning unit 5 (S1), and the read information is written in the memory 2 (S2). Next, the CPU 1 reads the data of the previous cycle from the memory 2 (S3).

The CPU 1 performs a comparison calculation process between the read previous data and the present data (S4). When the calculation is completed, the calculation data is written in the memory 2 (S
5). The CPU 1 checks whether there is a change between the previous data and the current data from the calculation data (S6). Then, when there is a change, the CPU 1 performs an output signal control process (S7), and shifts to the process of the next cycle.

[0006]

In the above-mentioned conventional system, the control program called change detection processing is utilized to read out the signal level and detect the change in each signal. Therefore, as the number of channels of the input signal increases, the load on the control program increases and the control processing capability of the output signal decreases.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal level detection system capable of speeding up the processing and improving the control processing capability of an input signal. ..

[0008]

FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, 1 is a CPU, 3 is a first memory for storing control programs and the like, 4 is a second memory for temporarily storing data, 5 is a scanning unit for taking in signals from a plurality of channels while scanning, and 6 is A timer for giving a scan cycle to the scan section 5, 10 is a data transfer control section for receiving a cycle signal from the timer 6 and controlling data transfer, and 11 is a first section for holding the data read from the second memory 4. 1 data transfer control unit, 1
Reference numeral 2 denotes a second data transfer holding unit that holds the data from the scanning unit 5, and reference numeral 13 reads the data from the first and second data transfer holding units 11 and 12 to perform data comparison calculation processing. It is a data comparison operation processing unit that gives the result to the data transfer control unit 10.

[0009]

The data of the previous cycle and the data of the current cycle are held in the data transfer control units 11 and 12, respectively, and the comparison processing operation is performed by the data comparison operation processing unit 13 by hardware. As a result, the load of the control program required for the processing can be significantly reduced, the processing can be sped up, and the control processing capability of the input signal can be improved.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. 11 and 12 are DMAs as a data transfer control unit
(Direct memory access) Control unit. 20
Is a driver that outputs the processing result to the outside. Other configurations are the same as those in FIG. The operation of the system configured as described above will be described below.

As processing by the program stored in the memory 1, the period of the timer 6 and the transfer information of the DMA control units 11 and 12 are set. As a result, the timer 6 sends the cycle information to the data transfer control unit 10. Upon receipt of this cycle information, the data transfer control unit 10 validates the data input from the scan unit 5 and causes the DMA control unit 12 to transfer the data input from the scan unit 5 to the data comparison operation processing unit 13. ..

Further, the data transfer control unit 10 is D
The MA control unit 11 is instructed to read the previous period data from the memory 2 and transfer it to the data comparison calculation processing unit 13. In the data comparison calculation processing unit 13, the DMA control unit 1
The two pieces of data input from 1 and 12 are compared and calculated to create change detection data.

The change detection data and the current scan data are processed by the data transfer control unit 10 after the arithmetic processing is completed.
It is written in the memory 2 in accordance with an instruction from the DMA controller 11 to.

FIG. 3 is a flow chart showing the program processing of the system of the present invention. This processing sequence is stored in the memory 1 and is performed by the operation of the CPU 1.

First, when the cycle information from the timer 6 is received, the change detection information written in the memory 2 is read (S1). Then, it is checked whether or not there is a change in the change detection information (S2), and if there is a change, output signal control processing is performed (S3). This output signal is output to the driver 2
It is output to the outside by 0. As can be seen from the above description, the number of steps is significantly smaller than that of the conventional sequence shown in FIG.

[0017]

As described in detail above, according to the present invention, the data from the data transfer control unit that holds the previous data and the present data is provided, and the data provided from these data transfer control units are hard-wired. By performing the comparison processing operation, it is possible to provide a signal level detection system that can speed up the processing and improve the control processing capability of the input signal.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention.

FIG. 3 is a flowchart showing a program process of the system of the present invention.

FIG. 4 is a block diagram showing a configuration example of a conventional system.

FIG. 5 is a flowchart showing the operation of the conventional system.

[Explanation of symbols]

 1 CPU 2 Bus 3 Memory 1 4 Memory 2 5 Scan Unit 6 Timer 10 Data Transfer Control Unit 11 Data Transfer Control Unit 12 Data Transfer Control Unit 13 Data Comparison Operation Processing Unit

Claims (1)

[Claims] 1. A CPU (1), a memory (4) for temporarily storing data, a scan section (5) for taking in signals from a plurality of channels while scanning, and a scan cycle for the scan section (5). A timer (6) for giving and a data transfer control unit (10) for controlling data transfer by receiving a periodic signal from the timer (6).
A first data transfer control unit (11) that holds the data read from the memory (4), a second data transfer holding unit (12) that holds the data from the scan unit (5), These first and second data transfer holding units (10), (1
1) The data from 1) is read out, data comparison operation processing is performed, and the result is the data transfer control section (10).
A signal level detection system configured by a data comparison calculation processing section (13) given to.