JPH05224918A - Self-change code realizing system - Google Patents

Abstract

PURPOSE:To realize the self-change code, and to execute a processing at a high speed by an instruction for executing a value on a register by providing an instruction analyzing part on the register and replacing an instruction train. CONSTITUTION:In the case where an instruction is an instruction executing instruction on a register, an instruction analyzing part 12 rewrites the instruction by the contents of the register and delivers the control to a regular instruction analyzing part, but in the case where the instruction is not the instruction executing instruction on the register, the control goes directly to the instruction analyzing part 12. Since the contents of the register are executed as the instruction, rewriting of a direct instruction train is avoided by using a central processing unit 1 having the instruction analyzing part 12, and it comes not to be a reentrant. By a computer system having an instruction cache, such a problems as nonexecutable is solved, and the processing can be executed softly at a high speed by a self-change code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction execution system on a computer system, and more particularly to an instruction analysis processing system.

[0002]

2. Description of the Related Art Self-modifying code in a conventional computer system is performed by rewriting an instruction sequence. Although this method is highly efficient as a speed-up technology, it has not been used in practice because it is difficult to understand, it is no longer reentrant, and it cannot be executed by a computer system with an instruction cache.

[0003]

The problem to be solved is that the self-modifying code is difficult to use.

[0004]

The present invention is characterized in that an instruction analysis unit is provided on a register to replace an instruction sequence.

[0005]

The present invention will be described in detail with reference to the drawings. FIG. 1 shows the contents of a central processing unit for realizing an embodiment of a self-modifying code realizing system according to the present invention. Referring to FIG. 1, the present invention includes a central processing unit 1 including an instruction reading unit 11, an instruction analyzing unit 12, and an instruction executing unit 13. FIG. 2 shows a flowchart of processing of the instruction analysis unit 12 shown in FIG.

At present, the difficulty of processing an instruction sequence is no longer a problem for general users due to the high-level programming, and it is a problem only for compiler designers and has come to correspond to a conventional microprogram. Also,
Since the high-level language has been achieved, the compiler designers have come to benefit from the speedup widely by considering the speedup by the self-modifying code. The remaining problems are reentrancy and instruction cache. In the self-modifying code implementation method of the present invention, since the contents of the register are executed as an instruction, direct rewriting of the instruction sequence is avoided by using the central processing unit 1 having the instruction analysis unit 12 and two problems are solved. .

The instruction analyzing unit 12 will be described with reference to the instruction analyzing unit flowchart of FIG. The instruction analysis unit 12
When the instruction is the instruction execution instruction on the register, the instruction is rewritten with the contents of the register and the control is passed to the normal instruction analysis unit. However, when the instruction is not the instruction execution instruction on the register, the control is directly performed. , Go to the instruction analysis unit 12. If the instruction analysis unit 12 solves the above-mentioned problem, the speed can be flexibly increased by the self-modifying code.

[0008]

As described above, in the self-modifying code implementation method for the computer system of the present invention, the processing speed is increased by the instruction for executing the value in the register.

[Brief description of drawings]

FIG. 1 shows the contents of a central processing unit for realizing an embodiment of a self-modifying code realizing system according to the present invention.

FIG. 2 is a flowchart showing a process of an instruction analysis unit shown in FIG.

[Explanation of symbols]

 1 Central Processing Unit 11 Instruction Reading Unit 12 Instruction Analysis Unit 13 Instruction Execution Unit

Claims (3)

[Claims] 1. An instruction reading unit for reading an instruction, an instruction analysis unit for analyzing the instruction, and an instruction execution unit for executing the instruction according to a result of analysis of the instruction by the instruction analysis unit. A self-modifying code implementation method implemented by the central processing unit. 2. The self-modifying code realizing method according to claim 1, wherein the instruction analyzing unit is configured to execute the self-modifying code in the form of rewriting an instruction sequence in a computer system, using a value in a register as an instruction. . 3. The self-modifying code realizing method according to claim 1, wherein the instruction reading unit, the instruction analyzing unit, and the instruction executing unit are realized inside the central processing unit with the help of software.