JPH0522143A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the high frequency characteristic of an analog signal input circuit system at the high-speed analog/digital (A/D) converter. CONSTITUTION:By turning an analog signal input part VIN to a distribution factor line, stray capacity provided at the input path is distributed and turned to a fixed impedance. Namely, analog signals are inputted, the two kinds of characteristic impedances Z01 and Z02 are provided at a first distribution factor line 11 equipped with a characteristic impedance Z0, four second distribution factor lines 12, 13, 14 and 15 respectively connected comparator circuit groups 16, 17, 18 and 19 are connected, and the degree of freedom for mask design is improved. Further, terminating resistors 20, 21, 22 and 23 are connected to the respective other terminals of these four distribution factor lines inside the A/D converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter suitable for high speed operation.

[0002]

2. Description of the Related Art Conventionally, a flash type is a typical example of a system suitable for high speed operation in an analog-digital converter. This is a system in which an analog input signal is supplied in parallel to each input of the analog comparators in the power of 2 and the comparison operations are simultaneously performed. For example, 6-bit analog
In the case of a digital converter, an analog input signal is supplied in parallel to the input circuits of 2 6th power, that is, 64 comparators. Therefore, the electrostatic capacitance formed in the input circuit becomes extremely large as the number of bits becomes large, which causes a significant decrease in high speed.

On the other hand, the total extension of the wirings connecting the input circuits in parallel causes a very large transmission delay effect as the number of bits increases, which also causes a great impediment to high speed. Now, even if these circuits are finely formed in an integrated circuit, for example, if the distance between adjacent comparators is 100 microns on average, in a 6-bit analog-digital converter, the total extension of wiring is 640
It becomes 0 micron and 25600 micron for 8-bit type. Assuming stray capacitance per micron and line inductance are 1 femtofarad and 0.1 nanohenry, the total capacitance of the input circuit is 6.4 picofarads for a 6-bit analog-to-digital converter. With 8 bits, it can reach 25.6 picofarads. At the same time, the line inductance becomes 640 nanohenries and 2560 microhenries, respectively. The cutoff frequency when such a large reactance component is present in the input circuit is a low value of about 100 MHz and 20 MHz, and analog cut-off for high speed is possible.
It makes the implementation of digital converters very difficult.

The structure of a conventional analog / digital converter of this type will be described below. FIG. 5 shows a part of the input circuit of the analog-digital converter.
V _IN is a signal input path for a converted signal for the purpose of analog / digital conversion, V _RT is a reference voltage high voltage side input path for comparison, V _RB is a reference voltage low voltage side input path for comparison, and 1 is a comparison Circuits A0, A1, A2, ... A254, A255,
Reference numeral 2 is a reference voltage generating resistor group R for comparison, and 3 is an encoder for encoding the output of each comparison circuit into a digital signal. CLOCK IN is a basic clock signal input path for analog / digital conversion operation, 4 is a driver circuit for supplying a clock signal to each part, EC-OUT is a digital output of the encoder 3, and 5 is a digital output to an external circuit. Is an output circuit for doing so, OUTPUT is a data output, and C _ST is an input capacitance of each comparison circuit 1.

FIG. 6 shows an example of a semiconductor mask layout of the high-speed 8-bit flash type analog-digital converter described above. Here, in order to reduce the attenuation of the input signal due to the filter action of the stray capacitance and the line inductance, the signal input path V _IN is branched into four, and the comparison circuit group 1 is arranged in four rows at the same time. Four
An attempt is made to shorten the total extension per one signal input circuit V _{IN of the} book.

FIG. 7 illustrates the signal input path V _IN portion of this semiconductor mask layout. Signal input path V
_IN is four branched input signal paths IN1, IN2, IN
3 and IN4 are divided and directed to the input terminal of each comparison circuit 1. FIG. 8 shows a circuit diagram of this semiconductor mask layout.

[0007]

However, in the above-mentioned conventional analog-digital converter, as shown in FIG. 8, the input signal paths IN1, IN2, IN3, I are branched.
Since there are 64 comparison circuits connected per N4, the total length is slightly over 6 mm, but the total stray capacitance of the entire signal input path V _IN is not small. Absent. Therefore, although the attenuation of the frequency characteristic at the furthest point of the branched input signal paths IN1, IN2, IN3, IN4 is reduced, this signal input path V _IN
The capacitive load on the external circuit that supplies high-frequency signals is still very heavy.

For example, for a 100 MHz sine wave signal with an amplitude of 1 volt, a capacitance of 25.6 picofarads acts as a reactance of 62.2 ohms,
High frequency current of up to 16 milliamps is wasted. Further, the influence of the capacitance becomes more significant as the frequency becomes higher, so in simple calculation, the reactance for a sine wave signal of 1,000 MHz becomes 6.3 ohms, and the waste of high frequency current becomes 160 milliamperes. ..

The present invention is intended to solve such a conventional problem, and an object thereof is to provide an excellent analog-digital converter capable of improving high frequency characteristics in an analog signal input circuit.

[0010]

In order to achieve the above object, the present invention relates to a first characteristic that is connected to an input terminal of an analog signal intended for digital conversion and maintains an inherent characteristic impedance including the input terminal. Distributed constant line, one end of which is connected to the first distributed constant line, has N types of characteristic impedances, and the combined impedance of the characteristic impedances is equal to the characteristic impedance of the first distributed constant line. 2 distributed constant lines, M group comparison circuit groups in which comparison input terminals are connected to these M second distributed constant lines in a distributed constant manner, and M second distributed constant lines. And a terminating resistance element having one end connected to the other end, a predetermined voltage source connected to the other end, and a resistance value equal to each characteristic impedance of the second distributed constant line. Than it is.

[0011]

According to the present invention, since the stray capacitance of the input path can be dispersed and have a constant impedance by converting the analog signal input path into a distributed constant with the above configuration, a high frequency signal is supplied to the analog signal input path. It is possible to reduce the capacitive load on the external circuit
Since the current load can be reduced even at a high frequency, the conversion operation can be speeded up.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an input circuit of an 8-bit analog-to-digital converter according to an embodiment of the present invention. In FIG. 1, reference numeral 11 is a first distributed constant line which is connected to an input terminal of an analog signal for the purpose of digital conversion and has a constant line width that maintains the characteristic impedance Z ₀ including the input terminal. 12, 1
One end of each of 3, 14, 15 is connected to the first distributed constant line 11, and two types of characteristic impedances Z ₀₁ , Z _{02 are provided.}
And the combined impedance of the characteristic impedances Z ₀₁ and Z ₀₂ is four second distributed constant lines equal to the characteristic impedance Z ₀ of the first distributed constant line 11.
Reference numerals 16, 17, 18, and 19 represent four groups of comparison circuit groups in which comparison input terminals are connected to each of these four second distributed constant lines 12, 13, 14, and 15 in a distributed constant manner. Terminations 20, 21, 22, 23 have one ends connected to the other ends of the four second distributed constant lines 12, 13, 14, 15 and the other ends connected with a predetermined voltage source (not shown). The second distributed constant line 12, which is a resistance element,
The resistance values are equal to the characteristic impedances Z ₀₁ and Z ₀₂ of 13, 14, and 15, respectively. That is, the impedances of the distributed constant lines 12 and 15 and the termination resistance elements 20 and 23 are Z ₀₁ , and the impedances of the distributed constant lines 13 and 14 and the termination resistance elements 21 and 22 are Z ₀₂ .

V _IN is a signal input path connected to an input terminal (not shown) for inputting an analog signal for the purpose of analog / digital conversion, V _RT is an input path for a reference voltage for comparison and a high voltage side, and V _RB is Reference voltage for comparison Low voltage side input path,
R0 to R254 are reference voltage generating resistor groups for comparison, A0 to
A2, Aj~Al, Ap~Ar, A253~A255 comparison circuit, C _ST is an input capacitance of each comparator circuit. Note that FIG. 2 is a simplified illustration of a group of branches and terminations of the input signal path in the above embodiment.

Next, referring to FIG. 1 and FIG.
The operation will be described. Signal input path V_INInput terminal of
Desired specific impedance Z to include₀Characteristic impi equal to
Input to the first distributed constant line 11 having impedance.
The analog signal is connected to this first distributed constant line 11.
The second distributed constant line 12, 13, 14, 15
And proceed. Characteristic impedance Z₀₁Distributed constant line with
Roads 12, 15 and Z ₀₂Distributed line 13,1 with
4 distributed constant lines 12, 13, 14, 15 branching
The combined impedance at the point is the characteristic impedance
Z₀Since it is set to be equal to
Are matched and at least the input signal is
There is little risk of backflow as a reflected wave to the distributed constant line 11.
Yes. In addition, the second distributed constant lines 12, 13, 14, 15
Is each group of 1/4 of the total comparison circuit
While connecting the input capacitance of the comparison circuit of
It is not included as if it is a part of the capacitive component of the distributed line.
To the second distributed constant line 12, 13, 14, 15
Has achieved the characteristic impedance desired by the
No. input path V_INDisperse the stray capacitance of the and constant impedance
Signal input path V_INHigh frequency signal to
It is possible to reduce the capacitive load on the external circuit
It

Assuming that such a circuit is realized by a silicon semiconductor, the line width is a value close to the thickness of the interlayer insulating layer when the characteristic impedance Z ₀ is 50 ohms because the permittivity is close to about 10. Is realized as. In the embodiment shown in FIG. 1, the signal input path V
_The characteristic impedance Z ₀ of the first distributed constant line 11 at _IN and the second distributed constant line 12 behind the branch,
Two types of characteristic impedance Z of 13, 14, and 15
_The following relationship holds between ₀₁ and Z ₀₂ .

1 / Z ₀ = 2 / Z ₀₁ + 2 / Z _{02 In} general, the second distribution constant after the branch is maintained while maintaining the relationship of 1 / Z ₀ = Σ ⁿ (m _j / Z _0j ). The characteristic impedance of the lines 12, 13, 14, 15 can be set freely. Here, n is the type of characteristic impedance, and m is the number of second distributed constant lines having the same characteristic impedance.

FIGS. 3 and 4 show an example of the semiconductor mask layout of the analog-to-digital converter in the above embodiment embodying this situation. The delay times of the second distributed constant lines 12, 13, 14, and 15 are set to be equal to each other, and the return times of the reflected waves are made uniform. The input analog signal input to the first distributed constant line 11 having the characteristic impedance equal to the specific impedance Z ₀ is transferred to the second distributed constant line 12, 1
The energy division by 3,14,15, after propagating through the lines 12, 13, 14, 15 while having an energy corresponding to the respective impedance Z _01, Z _02, respectively impedances Z _01, Z ₀₂ equal resistance Is introduced into the terminating resistance elements 20, 21, 22, and 23 to be converted into heat, so that reflected waves are suppressed.

[0018]

As described above, according to the present invention, the input capacitance which tends to be very large in the analog signal input portion of the analog-digital converter is dispersed over a wide frequency band and has a constant impedance. Since it can be changed to, it is possible to reduce the capacitive load on the external circuit that supplies the high-frequency signal to the analog signal input path, and to reduce the current load even at high frequencies, so the external circuit can easily handle high frequencies. Can be driven to an analog-to-digital converter,
This has the effect that the conversion operation can be made faster. Further, in the semiconductor mask layout of this analog-digital converter, the branched second distributed constant line is limited only to the combined value of the characteristic impedances, and the individual characteristic impedances are completely free. Since the distributed constant line can be provided, there is an advantage that even if the assigned ground pattern in the integrated circuit is a modified one, the comparison circuits can be arranged without being equally divided.

Furthermore, since the terminal ends of the second distributed constant line are each constituted by an independent resistance element,
In terms of mask design, the branched second distributed constant lines do not necessarily have to have the same length, which has the effect of increasing the degree of freedom in design.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input section of an analog-digital converter according to an embodiment of the present invention.

FIG. 2 is a connection diagram of a signal input path in the same embodiment.

FIG. 3 is a layout diagram of an input side of a semiconductor mask layout in the same embodiment.

FIG. 4 is a layout diagram of an output side of a semiconductor mask layout in the same embodiment.

FIG. 5 is a schematic block diagram showing an example of a conventional analog-digital converter.

FIG. 6 is a schematic plan view of a semiconductor mask in the conventional example.

FIG. 7 is a layout diagram on the input side of a semiconductor mask layout in the conventional example.

FIG. 8 is a circuit diagram of an input section in the conventional example.

[Explanation of symbols]

11 First distributed constant line 12, 13, 14, 15 Second distributed constant line 16, 17, 18, 19 Comparison circuit group 20, 21, 22, 23 Termination resistance element V _{IN For} analog-digital conversion Signal input path for converted signal V _RT Reference voltage for comparison High voltage side input path V _RB Reference voltage for comparison Low voltage side input path R0 to R254 Reference voltage generating resistor group for comparison A0 to A255 Comparison circuit C _ST Each comparison circuit Input capacitance of

Claims (1)

Claim: What is claimed is: 1. A first distributed constant line connected to an input terminal of an analog signal intended for digital conversion to maintain an inherent characteristic impedance including the input terminal, and the first distributed constant line. One end is connected to the distributed constant line and has N types of characteristic impedances, and the composite impedance of the characteristic impedances is M second distributed constant lines, and M of these second distributed constant lines are equal to the characteristic impedance of the first distributed constant line. A second group of distributed constant lines to which comparison input terminals are distributedly connected, and one end of each of the M second distributed constant lines connected to the other end of the second group of distributed constant lines. An analog / digital circuit which is connected to a predetermined voltage source at the other end, and which has a terminating resistance element having a resistance value equal to the characteristic impedance of each of the second distributed constant lines. Exchanger.