JPH0522141A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the high frequency characteristic of a analog signal input circuit system at the high-speed analog/digital (A/D) converter. CONSTITUTION:By turning an analog signal input path VIN to a distribution factor line, stray capacity provided at the input path is distributed and turned to a fixed impedance. Namely, analog signals are inputted, a four-times characteristic impedance 4Z0 as large as a characteristic impedance Z0 is provided at a first distribution factor line 11 equipped with the characteristic impedance Z0, and four second distribution factor lines 12, 13, 14 and 15 respectively connected comparator circuit groups 16, 17, 18 and 19 are connected. Further, these four distribution factor lines are gathered to a third distribution factor line 20, and an outside terminating resistor 22 is connected through an outside connecting terminal 21 to this line 20 outside the A/D converter.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter suitable for high speed operation.

[0002]

2. Description of the Related Art Conventionally, a flash type is a typical example of a system suitable for high speed operation in an analog-digital converter. This is a system in which an analog input signal is supplied in parallel to each input of the analog comparators in the power of 2 and the comparison operations are simultaneously performed. For example, 6-bit analog
In the case of a digital converter, an analog input signal is supplied in parallel to the input circuits of 2 6th power, that is, 64 comparators. Therefore, the electrostatic capacitance formed in the input circuit becomes extremely large as the number of bits becomes large, which causes a significant decrease in high speed.

On the other hand, the total extension of the wirings connecting the input circuits in parallel causes a very large transmission delay effect as the number of bits increases, which also causes a great impediment to high speed. Now, even if these circuits are finely formed in an integrated circuit, for example, if the distance between adjacent comparators is 100 microns on average, in a 6-bit analog-digital converter, the total extension of wiring is 640
It becomes 0 micron and 25600 micron for 8-bit type. Assuming stray capacitance per micron and line inductance are 1 femtofarad and 0.1 nanohenry, the total capacitance of the input circuit is 6.4 picofarads for a 6-bit analog-to-digital converter. With 8 bits, it can reach 25.6 picofarads. At the same time, the line inductance becomes 640 nanohenries and 2560 microhenries, respectively. The cutoff frequency when such a large reactance component is present in the input circuit is a low value of about 100 MHz and 20 MHz, and analog cut-off for high speed is possible.
It makes the implementation of digital converters very difficult.

The structure of a conventional analog / digital converter of this type will be described below. FIG. 5 shows a part of the input circuit of the analog-digital converter.
V _IN is a signal input path for a converted signal for the purpose of analog / digital conversion, V _RT is a reference voltage high voltage side input path for comparison, V _RB is a reference voltage low voltage side input path for comparison, and 1 is a comparison Circuits A0, A1, A2, ... A254, A255,
Reference numeral 2 is a reference voltage generating resistor group R for comparison, and 3 is an encoder for encoding the output of each comparison circuit into a digital signal. CLOCK IN is a basic clock signal input path for analog / digital conversion operation, 4 is a driver circuit for supplying a clock signal to each part, EC-OUT is a digital output of the encoder 3, and 5 is a digital output to an external circuit. Is an output circuit for doing so, OUTPUT is a data output, and C _ST is an input capacitance of each comparison circuit 1.

FIG. 6 shows an example of a semiconductor mask layout of the high-speed 8-bit flash type analog-digital converter described above. Here, in order to reduce the attenuation of the input signal due to the filter action of the stray capacitance and the line inductance, the signal input path V _IN is branched into four, and the comparison circuit group 1 is arranged in four rows at the same time. Four
An attempt is made to shorten the total extension per one signal input circuit V _{IN of the} book.

FIG. 7 illustrates the signal input path V _IN portion of this semiconductor mask layout. Signal input path V
_IN is four branched input signal paths IN1, IN2, IN
3 and IN4 are divided and directed to the input terminal of each comparison circuit 1. FIG. 8 shows a circuit diagram of this semiconductor mask layout.

[0007]

However, in the above-mentioned conventional analog-digital converter, as shown in FIG. 8, the input signal paths IN1, IN2, IN3, I are branched.
Since there are 64 comparison circuits connected per N4, the total length is slightly over 6 mm, but the total stray capacitance of the entire signal input path V _IN is not small. Absent. Therefore, although the attenuation of the frequency characteristic at the furthest point of the branched input signal paths IN1, IN2, IN3, IN4 is reduced, this signal input path V _IN
The capacitive load on the external circuit that supplies high-frequency signals is still very heavy.

For example, for a 100 MHz sine wave signal with an amplitude of 1 volt, a capacitance of 25.6 picofarads acts as a reactance of 62.2 ohms,
High frequency current of up to 16 milliamps is wasted. Further, the influence of the capacitance becomes more significant as the frequency becomes higher, so in simple calculation, the reactance for a sine wave signal of 1,000 MHz becomes 6.3 ohms, and the waste of high frequency current becomes 160 milliamperes. ..

The present invention is intended to solve such a conventional problem, and an object thereof is to provide an excellent analog-digital converter capable of improving high frequency characteristics in an analog signal input circuit.

[0010]

In order to achieve the above object, the present invention relates to a first aspect of the present invention, which is connected to an input terminal of an analog signal intended for digital conversion and maintains an inherent characteristic impedance including the input terminal. Distributed constant line, N second distributed constant lines having one end connected to the first distributed constant line and having a characteristic impedance N times the characteristic impedance of the first distributed constant line, and these N distributed constant lines. Of the comparison circuit in which the input terminals for comparison are connected to the second distributed constant line in a distributed constant manner, and characteristics equal to those of the first distributed constant line connected to the other ends of the N second distributed constant lines. A third distributed constant line having an impedance, and an external termination resistance element connected to the third distributed constant line and having a resistance value equal to the characteristic impedance of the third distributed constant line as a predetermined voltage source. Is obtained and an external connection terminal for connecting between.

[0011]

According to the present invention, since the stray capacitance of the input path can be dispersed and have a constant impedance by converting the analog signal input path into a distributed constant with the above configuration, a high frequency signal is supplied to the analog signal input path. It is possible to reduce the capacitive load on the external circuit
Since the current load can be reduced even at a high frequency, the conversion operation can be speeded up.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an input circuit of an 8-bit analog-to-digital converter according to an embodiment of the present invention. In FIG. 1, reference numeral 11 is a first distributed constant line which is connected to an input terminal of an analog signal for the purpose of digital conversion and has a constant line width that maintains the characteristic impedance Z ₀ including the input terminal. 12, 1
One end of each of the third, 14 and 15 is connected to the first distributed constant line 11 and has a characteristic impedance 4Z ₀ which is four times the characteristic impedance of the first distributed constant line 11, and the combined impedance thereof is the characteristic of the first distributed constant line 11. It is four second distributed constant lines that are equal to the impedance Z ₀ . 16, 17, 1
Reference numerals 8 and 19 denote these four second distributed constant lines 12, 1
3, 14 and 15 are comparison circuit groups of four groups in which comparison input terminals are connected in a distributed constant manner. Reference numeral 20 is a third distributed constant line connected to the other ends of the four second distributed constant lines 12, 13, 14, and 15 and having a characteristic impedance Z ₀ equal to that of the first distributed constant line 11. Reference numeral 21 is an external connection terminal of the analog-digital converter connected to the third distributed constant line 20. 22
Is an external termination resistance element having one end connected to the external connection terminal 21 and the other end connected to a predetermined voltage source (not shown), and has a resistance value equal to the characteristic impedance Z ₀ of the third distributed constant line 20. Have.

V _IN is a signal input path connected to an input terminal (not shown) for inputting an analog signal for the purpose of analog / digital conversion, V _RT is an input path for a reference voltage for comparison and a high voltage side, and V _RB is Reference voltage for comparison Low voltage side input path,
R0 to R254 are reference voltage generating resistor groups for comparison, A0 to
A2, A64 to A66, A128 to A130, A253
~A255 comparison circuit, C _ST is an input capacitance of each comparator circuit. Note that FIG. 2 is a simplified illustration of a group of branches and terminations of the input signal path in the above embodiment.

Next, the operation of the above embodiment will be described with reference to FIGS. The analog signal input to the first distributed constant line 11 having the characteristic impedance equal to the desired specific impedance Z ₀ including the input terminal of the signal input path V _IN is input to the second distributed constant line 11 connected to the second distributed constant line 11. The distributed constant lines 12, 13, 14 and 15 are branched and proceed. Since the combined impedance at the branch points of the four distributed constant lines 12, 13, 14, 15 having the characteristic impedance 4Z ₀ is set to be equal to the characteristic impedance Z ₀ , the branch points are matched. Therefore, at least the input signal is unlikely to flow back to the first distributed constant line 11 as a reflected wave. Also, the second
The distributed constant lines 12, 13, 14, and 15 of each of the comparison circuits are one-fourth of the entire comparison circuit, that is, each group 64.
While it signed a comparator circuit each 64 input capacitance of individual equidistant, though to achieve four times the characteristic impedance 4Z ₀ of characteristic impedance Z ₀ with inclusion as if it were part of the capacitive component of the distribution lines There is. Therefore,
Dispersing the stray capacitance of the signal input path V _IN and can be constant impedance, it is possible to reduce the capacity load on the external circuit for supplying a high-frequency signal to the signal input path V _IN.

Assuming that such a circuit is realized by a silicon semiconductor, the line width is a value close to the thickness of the interlayer insulating layer when the characteristic impedance Z ₀ is 50 ohms because the permittivity is close to about 10. Is realized as.

FIGS. 3 and 4 show an example of the semiconductor mask layout of the analog-digital converter in the above embodiment embodying this situation, and the circuit has a very good symmetry. The lengths of the second distributed constant lines 12, 13, 14, and 15 are set to be the same, and the return times of the reflected waves are made uniform. The input analog signal input to the first distributed constant line 11 having the characteristic impedance equal to the specific impedance Z ₀ is
After passing through the distributed constant lines 12, 13, 14, 15 and the third distributed constant line 20, the external constant voltage is guided to the external terminating resistance element 22 through the external connection terminal 21 and converted into heat, so that the reflected wave is suppressed.

[0017]

As described above, according to the present invention, the input capacitance which tends to be very large in the analog signal input portion of the analog-digital converter is dispersed over a wide frequency band and has a constant impedance. Since it can be changed to, it is possible to reduce the capacitive load on the external circuit that supplies the high-frequency signal to the analog signal input path, and to reduce the current load even at high frequencies, so the external circuit can easily handle high frequencies. Can be driven to an analog-to-digital converter,
This has the effect that the conversion operation can be made faster. Further, in the semiconductor mask layout of this analog-digital converter, the branched second distributed constant line is limited only to the combined value of the characteristic impedances, and the individual characteristic impedances are completely free. Since the distributed constant line can be provided, there is an advantage that even if the assigned ground pattern in the integrated circuit is a modified one, the comparison circuits can be arranged without being equally divided.

Furthermore, since the terminating resistor can be connected to the outside of the analog / digital converter through the external connection terminal, impedance matching can be adjusted accurately. Further, the power consumption / heat generation in the external terminating resistor can be designed separately from the analog / digital converter, so that the reliability of the device can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input section of an analog-digital converter according to an embodiment of the present invention.

FIG. 2 is a connection diagram of a signal input path in the same embodiment.

FIG. 3 is a layout diagram of an input side of a semiconductor mask layout in the same embodiment.

FIG. 4 is a layout diagram of an output side of a semiconductor mask layout in the same embodiment.

FIG. 5 is a schematic block diagram showing an example of a conventional analog-digital converter.

FIG. 6 is a schematic plan view of a semiconductor mask in the conventional example.

FIG. 7 is a layout diagram on the input side of a semiconductor mask layout in the conventional example.

FIG. 8 is a circuit diagram of an input section in the conventional example.

[Explanation of symbols]

11 First distributed constant line 12, 13, 14, 15 Second distributed constant line 16, 17, 18, 19 Comparison circuit group 20 Third distributed constant line 21 External connection terminal 22 External termination resistance element V _IN analog Signal input path of converted signal for digital conversion V _RT Reference voltage for comparison High voltage side input path V _RB Reference voltage for comparison Low voltage side input path R0 to R254 Comparison reference voltage generation resistor group A0 to A255 Comparison Circuit C _ST Input capacitance of each comparison circuit

Claims (1)

Claim: What is claimed is: 1. A first distributed constant line connected to an input terminal of an analog signal intended for digital conversion to maintain an inherent characteristic impedance including the input terminal, and the first distributed constant line. N second distributed constant lines having one end connected to the distributed constant line and having a characteristic impedance that is N times the characteristic impedance of the first distributed constant line;
A plurality of comparison circuit groups in which comparison input terminals are connected to each of the second distributed constant lines in a distributed constant manner;
A third distributed constant line connected to the other end of the distributed constant line and having a characteristic impedance equal to that of the first distributed constant line, and a third distributed constant line connected to the third distributed constant line.
An analog-digital converter having an external connection terminal for connecting an external termination resistance element having a resistance value equal to the characteristic impedance of the distributed constant line of FIG.