JPH05219052A - Scrambling circuit - Google Patents

Abstract

PURPOSE:To scramble data by generating a scramble pattern synchronized with a word reference clock and a frame synchronizing signal and multiplying the scramble pattern and input data. CONSTITUTION:An M-series generator consists of a shift register 1 and a linear feedback circuit 2 which input the word reference clock 51, the frame synchronizing signal 52, and a feedback signal 54, and the scramble pattern 53 is outputted by this M-series generator. Further, the scramble pattern 53 and input data 54 are multiplied by a multiplier 3 to scramble the input data 54 into scrambled data 55.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble circuit for randomizing data and restoring it inside a communication device or the like.

[0002]

2. Description of the Related Art A scramble circuit is an effective means for preventing eavesdropping of communication data by a third party and for improving the randomness of transmission data and improving the transmission quality of communication channels. , Widely used.

FIG. 3 shows the structure of a conventional scrambler. In FIG. 3, reference numeral 21 is a counter which outputs a frame address 56 in synchronization with the word reference clock 51 and the frame synchronizing signal 52, and 22 is a scramble pattern 53 which receives the frame address as an input. Is a read-only memory (ROM) for outputting
It is a multiplier which receives the data 54 and the scramble pattern 53 as input, and outputs the data 55 after scramble.

Next, the operation of the above conventional example will be described.
In FIG. 3, the counter 21 is incremented by the word reference clock 51 and reset by the frame synchronizing signal 52 which is valid only for one clock of the word reference clock 51. As a result, the counter 21
Always outputs a constant frame address 56 at a specific position on the frame.

The ROM 22 outputs the scramble pattern data 53 written in advance in accordance with the frame address 56.

The scramble pattern 53 and the input data
The data 54 is multiplied by the multiplier 23, and the scrambled data 54 is output.

As described above, even in the conventional scramble circuit described above, the scramble pattern 53 synchronized with the word reference clock 51 and the frame synchronization signal 52 is generated to generate the data synchronized with the frame. Can be scrambled.

[0008]

However, in the above conventional scramble circuit, when the frame length becomes long, the number of stages of the counter increases, the required memory capacity increases, and the data transmission speed is increased. If it becomes faster, it will be expensive because it needs to use high-speed memory,
And there is a problem that the number of parts is large.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an excellent scramble circuit which realizes a scramble function with a simple structure.

[0010]

In order to achieve the above object, the present invention provides a shift register circuit for inputting a word reference clock, a frame synchronizing signal and a feedback signal and outputting a scramble pattern 53, The scramble pattern from this shift register circuit is input, and the linear feedback circuit that outputs the feedback signal to the shift register circuit, the input data and the scramble pattern are input, and scrambled. And a multiplier for outputting data.

[0011]

Therefore, according to the present invention, the feedback signal 54 from the linear feedback circuit 2 is fed to the shift register circuit 1 which receives the word reference clock 51 and is reset by the frame synchronizing signal 52. By performing feedback, it is possible to configure an M-sequence generator that generates an M-sequence synchronized with the frame synchronization signal 52.

With regard to the sequence length of this M sequence, when the number of stages of the shift register circuit 1 is N, 2 _N -1 M sequences can be generated, and similarly in the state of the shift register circuit 1, 2 _N-. There can be one type of state.

The output of each stage of the shift register circuit 1 is taken out as a scramble pattern 53, so that the scramble pattern 53 synchronized with the N-bit parallel frame synchronizing signal 52 having a sequence length of 2 _N -1. Can be generated.

Further, by multiplying the scramble pattern 53 by the input data 25, the input data 55 can be scrambled.

[0015]

1 is a schematic block diagram showing the configuration of an embodiment of the present invention, in which a word reference clock 51, a frame synchronizing signal 52 and a feedback signal 54 are input and a scramble pattern 53 is output. A shift register circuit 1 and a linear feedback circuit 2 which receives the scramble pattern 53 from the shift register circuit 1 as an input and outputs the feedback signal 54 to the shift register circuit 1 and an input data.
A multiplier 3 is provided, which receives the data 55 and the scramble pattern 53 and outputs scrambled data 56.

FIG. 2 shows a concrete circuit of an embodiment of the present invention. In FIG. 2, reference numeral 11 is an 8-bit shift register circuit, and a word reference clock 51 is input to its clock terminal, and a frame synchronization signal 52 is input to the clear one terminal CLR. 12 is a linear field
This is a feedback circuit, and the exclusive OR elements 12a and 12b for inputting 2 bits of the scramble pattern 53 of the shift register circuit 11 and the outputs of these exclusive OR elements 12a and 12b are used as two inputs to provide a feedback signal. And an exclusive OR element 12c outputting 54. 13 is a scramble pattern 53 output from the shift register 11 and 8-bit parallel input data 5
5 is a multiplier that multiplies with the exclusive OR element 13a
It is composed of 13 h. 14 is a shift register circuit 1
This is a flip-flop for giving an initial value to 1. The frame synchronizing signal 52 is inputted to its D input terminal, and the word reference clock 51 is inputted to its clock input terminal. Similarly, 15 is an OR gate for giving an initial value to the shift register circuit 11. This OR gate 15 outputs the inverted output of Q of the flip-flop 14 and the feedback signal 54 from the linear feedback circuit 12 to 2 The output is input to the IN input terminal of the shift register circuit 11.

Next, the operation of the above embodiment will be described.
In the above embodiment, the logic 2 "is synchronized with the word synchronous clock 51 and is in the period of the cycle of the word synchronous clock 51.
The frame synchronizing signal taking L "is the shift register circuit 11
Is input to the shift register circuit 11, the shift register circuit 11 is reset. In the next one cycle of the word synchronous clock 51, the output of the flip-flop 14 becomes logic "H", so that the shift register 11 is given an initial value. After that, the shift register circuit 11 operates as an M-sequence generator according to the logical expression formed by the linear feedback circuit 12 until the frame synchronizing signal 52 becomes logical "L" again.

In the above embodiment, since the shift register circuit 11 is an 8-bit shift register, the number of possible states is 2 ₈ -1 = 255, and the scrambler of 8-bit parallel data having a sequence length of 255 is available. The pattern 53 is output. This scramble pattern 53 and input data
The data 54 is multiplied by the multiplier 13 to scramble the data, and the scrambled data 55 is obtained.

As described above, according to the above-described embodiment, the M-sequence generator composed of the shift register circuit 11 and the linear feedback circuit 12 has 255 scramble patterns even when the frame length becomes long. Since it is repeatedly generated, the scramble circuit can be configured by the same circuit regardless of the frame length.

[0020]

As is apparent from the above-described embodiment, the present invention comprises a scramble circuit using an M-sequence generator composed of a shift register circuit and a linear feedback circuit and a multiplier. This has an advantage that scrambling can be performed on input data having an arbitrary frame length with a very simple structure.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a scramble circuit according to the present invention.

FIG. 2 is a circuit diagram of a scramble circuit having the configuration of FIG.

FIG. 3 is a schematic block diagram of a conventional scramble circuit.

[Explanation of symbols]

 1 shift register circuit 2 linear feedback circuit 3 multiplier 11 shift register circuit 12 linear feedback circuit 13 multiplier 14 flip-flop 15 OR gate 51 word reference clock 52 frame synchronization signal 53 scramble pattern 54 feedback signal 55 input data 56 scrambled output data

Claims (1)

[Claims] 1. A shift register circuit for inputting a word reference clock, a frame synchronizing signal and a feedback signal and outputting a scramble pattern, and a feedback signal for inputting the scramble pattern to the shift register circuit. And a multiplier for outputting input data and the scramble pattern, and outputting the scrambled data. Scramble circuit.