JPH05218861A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To accelerate the frequency switching of the frequency synthesizer and to realize a high S/N. CONSTITUTION:This frequency synthesizer is provided with a numerical controlled oscillator 3 to integrate a prescribed phase amount increment step value DELTAphiaccording to the timing of a signal obtd. by dividing the output frequency of a VCO (voltage controlled oscillator) 1 by a fixed frequency divider 2 and to output a remainder phi in the case of dividing the value by 2pi radian as a feedback phase signal, phase comparator 6 to output a phase error signal epsilonconcerning a reference phase signal psi obtained by frequency dividing a reference signal fr, and weight synthesizer 11 to enlarge the weight of the signal epsilon through a D/A converter 9 while an average circuit 7 completely calculate an average value <epsilon>, to reduce the weight of the average value <epsilon> through a D/A converter 10 later and to define the value as the controlled voltage of the VCO 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer used for communication equipment, and more particularly to an improvement aimed at speeding up frequency switching operation of a frequency synthesizer capable of arbitrarily setting a highly accurate output frequency.

[0002]

2. Description of the Related Art A phase locked loop (PLL) configuration is a basic configuration widely applied to a frequency synthesizer for obtaining a highly accurate output frequency. P
The LL configuration has a great advantage in terms of circuit scale and frequency accuracy that an output frequency phase-locked with a highly accurate reference oscillation source using a crystal oscillator can be obtained with a relatively small-scale circuit. However, since the PLL configuration is a negative feedback control loop, there is a reciprocal relationship between the signal-to-noise ratio (C / N) of the output of the frequency synthesizer by the PLL configuration and the response speed of the loop. That is, for example, TDM (Tim
When it is necessary to perform high-speed frequency switching for each short burst section, such as in e-Division Multiplex) communication and frequency hopping communication, if the response speed of the frequency switching operation is increased, the band of the system becomes wider and the output There is a problem that C / N decreases. One of the conventionally known methods for solving this problem is a dual mode PLL configuration.

FIG. 11 is a block diagram of a conventionally used dual mode PLL. In the figure, 101 is a voltage controlled oscillator (hereinafter, VCO: Voltage Controlled Oscillator).
), 102 is VC according to the frequency given from the outside.
A variable frequency divider that divides the output f _0ut of _{O 101} , and 103 is a reference oscillator that generates a reference frequency. Reference numeral 104 denotes a phase comparator for comparing the output phases of the variable frequency divider 102 and the reference oscillator 103, which is generally a multiplication process on a binary level by an exclusive OR or the like, and an analog waveform and a binary value by a balanced mixer circuit or the like. The phase comparison function is realized by the multiplication processing with the waveform. Reference numeral 105 removes harmonic components other than the phase comparison value included in the output of the phase comparator 104,
Is a dual-mode loop filter that feeds back to the frequency control voltage input, and is configured by a loop filter that can switch the loop band of the PLL into a wide band and a narrow band two modes according to a mode switching signal input from the outside. .. For the loop filter 105, generally, a third-order or lower-order low-pass filter is used for the reason of system stability, and parameters such as a time constant, a cutoff frequency, or a gain of the low-pass filter are large depending on the mode switching signal. ， Switched to small. In the above configuration, when the frequency of the output f _out is switched, first, the frequency divider corresponding to the frequency to be set (ratio between the frequency to be set and the reference frequency) is given to the variable frequency divider 102, and at the same time, the dual frequency divider is used. By the mode switching signal given to the mode filter 105, the loop time constant is set to be small, the cutoff frequency is set to be large, or the gain is set to be large for a predetermined frequency pull-in time to widen the loop band and perform the pull-in operation at high speed.

Next, when the predetermined frequency pull-in time has elapsed, the polarity of the mode switching signal is inverted to set the loop time constant to a large value, the cutoff frequency to a small value, or the gain to a small value to narrow the loop band. Output stabilization, high C / N
Measure. By skillfully combining these two modes, the above-mentioned problem of the reciprocal relationship between the response speed and the C / N is solved. However, when the conventional dual-mode PLL configuration is actually implemented as hardware,
How to realize the mode switching operation of the dual mode loop filter 105 as ideal becomes a big problem. That is, when switching the parameters of the dual-mode loop filter 105, specifically, it is necessary to control switching of passive elements such as resistors and capacitors or active elements such as transistors and operational amplifiers and circuits by analog switches. Since the control operation involves a rapid charge / discharge of the capacitor and a change in the DC offset voltage due to switching of different semiconductor elements, a discontinuous change occurs in the frequency control voltage of the VCO 101, and after switching to a narrower loop band. The frequency and the phase largely deviate from the target values, which causes a problem of prolonging the phase synchronization.
In order to solve such a problem at the time of switching, another method which does not use the dual mode PLL configuration has been devised in recent years.

According to this method, when the frequency of the synthesizer is switched, first, the frequency control voltage of the VCO corresponding to the frequency of the switching destination is measured in advance and digitalized data is stored, and the stored value is D. A / A converter is applied to the control voltage terminal of the VCO to initialize the coarse frequency adjustment, and at the same time, one of the two inputs (reference oscillator output and variable frequency division output) of the phase comparator is applied to the other. Force preset to match the phase of. With this preset processing, it is possible to realize a phase synchronization state to almost the frequency of the switching destination at the initial stage of frequency switching. (For example, see Taruzawa et al. "Digital Loop Preset Type High-speed Frequency Synthesizer" IEICE Spring National Convention B-820, 1989).

[0006]

However, it is known that in the method by the preset processing, the phase synchronization time after the preset processing is greatly influenced by the coarse adjustment accuracy of the frequency (see the above-mentioned reference). In order to improve the coarse adjustment precision, a means for digitally monitoring the frequency control terminal voltage of the VCO after the phase synchronization pull-in using a D / A converter and learning and storing is required. However, even if this learning and storing means is used, if the ambient temperature changes significantly,
Since a new frequency is forced to be set without prior knowledge of the frequency control terminal voltage by the above learning, the problem that the synchronization pull-in time becomes long cannot be avoided. An object of the present invention is to provide a frequency synthesizer suitable for miniaturization and IC implementation, in which the problems caused by the conventional method are eliminated in overcoming the reciprocal relation of high frequency switching and high S / N ratio. To do.

[0007]

SUMMARY OF THE INVENTION A frequency synthesizer of the present invention comprises a voltage controlled oscillator to which a frequency controlled voltage is input and an output of an oscillation frequency corresponding to the frequency controlled voltage is obtained, and an output of the voltage controlled oscillator is fixed. A fixed frequency divider that performs frequency division, and a numerically controlled oscillator that outputs a remainder φ when the phase amount increase step value Δφ set externally according to the output timing of the fixed frequency divider is integrated and divided by 2π (radian) A reference oscillator for giving a reference frequency of the frequency synthesizer, a counter for outputting a value ψ obtained by dividing the output from the reference oscillator, an output φ from the numerically controlled oscillator and an output ψ from the counter, respectively. Input as the feedback phase signal from the voltage controlled oscillator and the reference phase signal from the reference oscillator,

[Equation 4] And a phase comparator that outputs the phase error signal ε given by
The averaging circuit that outputs ε> and the ε and the <ε> are input, and the predetermined switching time T ₁ when the phase synchronization pull-in response enters the steady state and the calculation of the average value by the averaging circuit is completed is performed. A switching circuit that switches and outputs ε until the time elapses and <ε> after the switching time T ₁ has passed, and the output of the switching circuit and the output of the phase comparator are converted into analog voltage signals. The first and second D / A converters to be converted, and the weight of the output from the first D / A converter are increased, and the weight of the output from the second D / A converter is decreased. And a weighted synthesizer that feeds back the analog-added voltage as the frequency control voltage to the voltage controlled oscillator.

[0008]

【Example】

[Configuration] FIG. 1 is a configuration example diagram showing a first embodiment of a frequency synthesizer according to the present invention. In the figure, reference numeral 1 is a voltage controlled oscillator (VCO), which generates an oscillation frequency f _out corresponding to a frequency control voltage V given from the outside. Reference numeral 2 denotes a fixed frequency divider, which outputs a clock f _CLK (= f _out / P) obtained by fixedly dividing the oscillation output of the VCO 1 to 1 / P (P ≧ 1). 3 is a numerically controlled oscillator (NCO: Numerical Contr)
olled Oscillator), which outputs a value φ obtained by dividing a value obtained by integrating the phase amount increase step value (digital value) Δφ set externally by 2π according to the timing of the input signal (f _{CLK in} FIG. 1). .. Such a function is 2π
This can be easily realized by an accumulator that uses the radian phase value as an overflow value (2 ⁿ , n is a natural number). Four
Is a reference oscillator, which outputs a reference clock that gives the reference frequency f _r of the frequency synthesizer. Reference numeral 5 denotes a counter, which outputs a value (digital value) ψ obtained by dividing the input (f _{r in} FIG. 1). Reference numeral 6 denotes a phase comparator which inputs φ and ψ as a feedback phase signal from the VCO 1 and a reference phase signal from the reference oscillator 4, respectively, and outputs a phase error signal ε (digital value, −π ≦ ε) given by the following equation. ≤π) is output.

[Equation 5] The calculation function of the above formula (1) is 2π as in the case of NCO3.
It can be easily realized by a plurality of adders using the radian phase value as the overflow value.

Reference numeral 7 is an averaging circuit for calculating the average value of the phase error signal ε and outputting the value <ε> stored and held. The averaging method is various digital such as simple averaging and weighted averaging with a forgetting factor. A filtering method can be applied. A switching circuit 8 inputs the phase error signal ε and its average value <ε>, and a predetermined time (hereinafter,
Until T _{1 (} switching time) elapses, ε is switched and then <ε> is switched and output. The switching time T ₁ is the time required for the first phase synchronization pull-in response of the frequency synthesizer of the present invention to reach a steady state.
Shall be set to a value including the calculation time of the average value of ε. Reference numerals 9 and 10 denote D / A converters, which respectively input the output of the switching circuit 8 and the output of the phase comparator 6 (phase error signal) and convert them into analog voltage signals V ′ and V ″, respectively. Increases the weighting of V ′, and V ″
Is a weighting synthesizer that reduces the weighting of the analog signal and performs analog addition. The synthesized output is V as the frequency control voltage V.
Returned to CO1.

Next, FIG. 2 is a block diagram showing a second embodiment of the frequency synthesizer according to the present invention. Most of the components in FIG. 2 are the same as in FIG. 1, but 1'is VCO1.
Is a VCO to which two kinds of frequency control voltages of relatively high gain (large weighting) and low gain (small weighting) are input, respectively, and D / A converters 9 and 10 respectively.
The outputs V'and V "are directly input, and the weighting combination 11 of FIG. 1 is unnecessary. Here, the VCO in the case of FIG.
An example of the configuration of 1'is shown in FIG. FIG. 7 shows an equivalent tuning circuit of the VCO 1 ', where 1-1 is a coil and 1-2 is a capacitor. 1-1 and 1-2 respectively correspond to the inductance and capacitance of the single tuning resonant circuit used for VCO 1 '. 1-3, 1-4 are variable capacitance diodes, 1-3 is connected in parallel to a single tuning resonance circuit consisting of 1-1, 1-2, and 1-3, 1-4
The outputs V'and V "of the D / A converters 9 and 10 are input to the capacitance control voltage terminals of the respective terminals. 1-5 is a resistor,
A 1-port circuit including a capacitor, a coil, etc., having an impedance Z, and a variable capacitance diode 1
-4 is connected in series to the single-tuned resonance circuit and the variable capacitance diode 1-3 according to 1-1 and 1-2.

With the configuration shown in FIG. 7, the oscillation frequency f _out of the VCO 1'is a synthetic circuit including the inductance of the coil 1-1, the capacitor 1-2, the variable capacitance diodes 1-3, 1-4 and the 1-port circuit 1-5. Is determined by the total capacitance of. Therefore, when the absolute value of the impedance Z of the 1-port circuit 1-5 is set sufficiently larger than the absolute value of the impedance of the variable capacitance diode 1-4, the variable capacitance diodes 1-3 and 1-4 have the same capacitance value range. However, the sensitivity of the capacitance of 1-3 (controlled by V ′) to the oscillation frequency is generally larger than that of the capacitance of 1-4 (controlled by V ″). It is possible to realize a VCO 1'that receives two types of frequency control voltages V'and V "of gain (large weighting) and low gain (small weighting), and the effect thereof is the combination of the weighting synthesizer 11 and VCO1 of FIG. It turns out that it is equivalent to.

Next, FIGS. 3 and 4 show a third embodiment and a fourth embodiment of the present invention obtained by modifying the constitutional examples of FIGS. 1 and 2, respectively. All the components of each of FIGS. 3 and 4 are exactly the same as those of FIGS. 1 and 2, respectively,
However, it is only that the outputs of the fixed frequency divider 2 and the reference oscillator 4 are connected to the counter 5 and the NCO 3, respectively.
2 and the case of FIG. That is, in the configurations of FIGS. 3 and 4, the output φ of the NCO 3 becomes the reference phase signal and the output φ of the counter 5 becomes the feedback phase signal.

Further, FIGS. 5 and 6 show fifth and sixth embodiments of the present invention obtained by modifying the configuration examples of FIGS. 1 and 2, respectively. Most of the components of FIGS. 5 and 6 are
1 and 2, respectively, except that a second averaging circuit 70 and a second switching circuit 80 having the same functions as the averaging circuit 7 and the switching circuit 8 are newly added.
70 inputs the output of the phase comparator 6, 80 inputs the output of the phase comparator 6 and the output of 70, and outputs the switched output by the D
The output to the A / A converter 10 is different from the configuration examples of FIGS. 1 and 2, respectively. The switching circuit 80
When the switching time of T is set to T ₂ , T ₂ is set to a value obtained by adding the time until the phase synchronization pull-in response enters the steady state after T ₁ and the time for calculating the average value by the averaging circuit 70. And

[Operation] FIG. 1, FIG. 2, FIG. 3, FIG.
The operation of the configuration example of the present invention shown in FIG. 6 will be described below. First, features common to all the above-described configuration examples of the present invention will be described. All the configuration examples of the present invention are configured by weighted synthesis of the first loop passing through the D / A converter 9 and the second loop passing through the D / A converter 10. The two loops are essentially the same type except for the loop gain, and an equivalent circuit common to both is shown in FIG. In FIG. 8, reference numeral 81 is an addition block corresponding to the phase comparator 6, which inputs the feedback phase signal φ and the reference phase signal ψ and outputs the phase error signal ε based on the equation (1). 82 is a total gain G by the D / A converter 9 or 10 and the weighting coefficient of the two loops.
_An amplification block 83 which gives _A , an amplification block 83 which gives a frequency modulation sensitivity K _V of VCO 1 or 1 ', and an output of 83 is an output frequency f _out of VCO 1 or 1'.

84 is the output frequency f of the VCO 1 or 1 '.
An integration block for converting _out into a phase, 85 is a fixed frequency divider 2 and 1 / (P · Q) frequency division operation of the output phase of VCO 1 or 1'by NCO 3 (Q is an equivalent frequency division number of NCO 3) And an output of the attenuation block corresponds to the feedback phase signal φ. Now, in the equivalent circuit of FIG. 8, φ, ψ,
Since each value of ε changes discretely on the time axis due to the movement of the NCO 3 and the counter 5, these are treated in the Z-transform region and represented by φ (Z), ψ (Z), ε (Z), respectively. ,
The following equation is obtained. Here, the rightmost factor Z ^-1 / (1-Z ^-1 ) on the left side is an integral operator in the Z conversion region. When the equation (2) is transformed and rearranged, the following equation is obtained. φ (Z) = H (Z) · ψ (Z): Response characteristics (3) The following equation is established from the equation (3). ε (Z) = φ (Z) −φ (Z) = (1−H (Z)) φ (Z) ... (6)

Now, when the frequency step input Δf is superimposed on the reference phase signal ψ by the frequency switching control, Therefore, by substituting equations (4) and (7) into equation (6) and rearranging, the following equation is obtained. Therefore, the time series ε (k) of ε is obtained by the inverse Z transformation of the equation (8).
When (k: time series number) is obtained, the following equation is obtained. Therefore, when the loop gain G _L from the expression (9) satisfies the following expression | 1- _GL | <1 ………… (10) That is, 0 < _GL <2 ………… (11) It can be seen that the loop is stable and its order is first order.

The phase comparator 6 in the configuration of the present invention.
Does not include unnecessary harmonic components because it directly detects the phase error amount itself and digitizes it without using non-linear operations such as the multiplication of the periodic waveform found in conventional phase comparators. .. Therefore, in principle, the loop filter for harmonic component removal for improving C / N included in the conventional PLL configuration is not necessary in the configuration of the present invention, and therefore, the synchronous pull-in operation imposed by the loop filter is not necessary. Since it is possible to remove the limitation of speeding up, it is clear that even in the first-order loop, there is a way open to speeding up the response while ensuring a constant C / N value. The above are the basic features common to the first and second loops passing through the D / A converters 9 and 10, respectively. The loop gain G _L of these two loops is determined by the weighting synthesizer 11
Alternatively, it is apparent that the first loop is set to be larger than the second loop due to the effect of the weighted combination by the VCO 1 '.

Now, based on the characteristics of the above two loops, the frequency switching operation in the configuration example of FIG. 1 will be specifically described below. Introduction output frequency f _out
Clarify the setting of. In FIG. 1, the feedback phase signal φ obtained from the NCO 3 is represented by the integrated value of Δφ with an overflow value of 2π radians.

[Outer 1]

[Equation 6] Therefore, the equivalent frequency division Q by NCO3 is

[Equation 7] Is.

A counter 5 for dividing the reference clock
Also counts like NCO3

[Outside 2]

[Equation 8] Is. Therefore, in the phase locked state

[Equation 9] Therefore, by substituting the equations (12) and (14) into the equation (15), To get Since the output frequency f _out of the VCO 1 is f _out = P · f _CLK (17), the following (18) is obtained from the equations (16) and (17).
Get the expression. (18) from the equation, P, N, when a fixed value f _r, the output frequency f _out is seen that uniquely set in relation inversely proportional to [Delta] [phi. The above equations (12) to (18) are similarly established in FIGS. 2, 5 and 6 having the same phase comparison configuration as in FIG.

Next, from the time when the phase amount increase step value Δφ corresponding to the target value (switching destination) of the output frequency f _out given by the above equation (18) is set in NCO3, the target f _out is actually targeted. The phase pull-in operation process until the output phase-synchronized with the value is obtained will be described below. In the configuration in which the first loop and the second loop shown in FIG. 1 are combined by the weighting combiner 11, until Δφ is first set and then the switching time T ₁ of the switching circuit 8 elapses. As for time, both of the above two loops continue to respond in a closed loop. The total closed-loop operation at this time is the same as the response of the first-order loop having a loop gain corresponding to the sum of the loop gains of both, and naturally the first loop having a high loop gain is Play a dominant role. Therefore, the loop gain of the first loop is (11)
By setting an appropriately large value within the range of the equation, a high-speed phase pull-in operation can be performed.

Next, when the switching time T ₁ elapses, the output of the switching circuit 8 is switched from the phase error signal ε from the phase comparator 6 to the memory holding value <ε> of the average value of ε by the averaging circuit 7. Change Here, the switching time T ₁ is set to a value obtained by adding the time until the first response by the two loops enters the steady state to the calculation time of the average value of ε by the averaging circuit 7, The loop of No. 1 is in an open loop state in which the phase error signal ε in the steady state is fixed to its average value <ε>. At this time, the second loop uses the phase error signal inherited when the first loop is set to the open loop state as an initial value, and continues the closed loop operation with a low loop gain. That is, the second loop improves the frequency accuracy by absorbing the deviation of <ε> from the true average value of the phase error signal ε, and the closed loop operation that guarantees a high C / N by the low loop gain. To continue. The above is the phase pull-in operation process at the time of frequency switching in the configuration example of FIG. 1, but in the configuration example of FIG.
Since CO1 'itself includes the function of the weighting combiner 11 of FIG. 1, it is obvious that the same operation as that of FIG. 1 can be obtained.

FIG. 9 shows an actual measurement example of the phase lock pull-in characteristic of the configuration example of FIG. The horizontal axis of FIG. 9 is time (ms), the vertical axis is frequency (50 kHz / scale), which is 451.5 MHz.
Output frequency f _out from -4MHz to 447.5MHz
The actual measurement result when switching in the width of z is plotted. The design values in this case are summarized in Table 1 below.

[Table 1] From Fig. 9, 0.3 ms from the frequency switching setting (left end of the diagram)
After the switching time T ₁ of (millisecond) has elapsed, the first loop, the second loop
It can be confirmed that the frequency is pulled within the range of ± 80 kHz of the target frequency 447.5 MHz by the closed loop operation by weighted synthesis of the loop. After the lapse of T ₁ , as described above, the first loop enters the open loop state in which the holding value <ε> of the average value of the phase error signal ε is used as the control voltage, and the closed loop operation of only the second loop is performed. ,
It can be seen that the frequency fluctuation width due to the phase error signal ε is sharply reduced to within ± 10 kHz. From this experiment, it was confirmed that the phase synchronization pull-in was completed in about 0.6 ms after the frequency switching was set, and the fluctuation width of f _out was converged within 1 kHz.

Next, the setting of the output frequency f _out in the configuration examples of FIGS. 3 and 4 will be clarified. In FIGS. 3 and 4, the output f _CLK of the fixed frequency divider 2 and the output f _r of the reference oscillator 4 are exchanged and connected as compared with the configuration examples of FIGS. 1 and 2. Therefore, the above equations (12) and (13)
The following equations are obtained by exchanging f _CLK and f _r in equations (14) and (16), respectively.

[Equation 10]

[Equation 11]

[Equation 12] On the other hand, also in the configuration examples of FIG. 3 and FIG.
Since equation (7) holds, this equation (17) and the above (1)
From the equation 6) ′, the following equation corresponding to the equation (18) is obtained. From the above (18) 'equation, N, P, when a fixed value f _r, the output frequency f _out is 1, in the configuration of FIG. 2 (1
While the relationship was inversely proportional to Δφ by the equation 8),
It can be seen that the configurations shown in FIGS. 3 and 4 can be uniquely set in a relationship proportional to Δφ. It is obvious that the phase synchronization pull-in operation process in the configurations of FIGS. 3 and 4 is the same as that in the configurations of FIGS. 1 and 2.

Next, the phase pull-in operation process in the configuration example of FIGS. 5 and 6 will be described. In the configurations of FIGS. 5 and 6, the averaging circuit 70 and the switching circuit 80 having the same functions as the averaging circuit 7 and the switching circuit 8 of the first loop are provided in the second loop of the configurations of FIGS. 1 and 2, respectively. In addition, the switching time T ₂ of the switching circuit 80 is set to be equal to or longer than a value obtained by adding the average value calculation time by the averaging circuit 70 to T ₁ . Therefore, the operation from the start of the frequency switching operation to the elapse of the switching time T ₂ by the switching circuit 80 is exactly the same as that in FIGS. 1 and 2, and further in FIGS. 3 and 4. Therefore, when the switching time T ₂ elapses, the first time is already reached.
Is in an open loop state and the second loop is in a steady state with closed loop operation due to low gain. After this point in time, in the configuration of FIGS. 5 and 6, the switching circuit 80 switches the phase error signal ε to the storage value <ε> ′ of the average value of ε output from the averaging circuit 70. The second loop is also in the open loop state. As described above, not only the first loop, but finally the second loop also becomes an open loop state due to the memory holding value <ε> ′, which is largely shown in FIGS. 1, 2, 3, and 4. Different.

As described above, when the entire system is set in the open loop state, the control voltage of VCO 1 or 1'-
There is a case where the closed loop-specific compensation ability for fluctuations in the oscillation frequency characteristics and fluctuations in the power supply voltage is lost, and output frequency drift occurs. However, TDM communication or frequency hopping that performs high-speed frequency switching in each short burst interval. In communication, the drift of the frequency during the burst period is so small as to be negligible, so that the effectiveness of the present invention can be derived.
Here, an actual measurement example of the phase lock pull-in characteristic of the configuration example of FIG. 6 is shown in FIG. The style and design values in FIG. 10 are all the same as those in FIG. 9, and the switching time T ₂ of the switching circuit 80 is set to about 0.6 ms. From the figure, the first loop enters the open loop state at the time when T _{1 has} elapsed, and the frequency fluctuation width is ±
It can be confirmed that the output frequency is reduced within 10 kHz, and the second loop becomes an open loop state at the time when T ₂ elapses, and a highly accurate output frequency with almost no fluctuation is obtained. The above is the operation of the present invention in the configuration examples of FIGS.

Although not shown, FIG. 5 and FIG.
In the same manner as in the configuration examples of FIGS. 3 and 4, the fixed frequency divider 2
And the output of the reference oscillator 4 to the counter 5 and NC, respectively.
It may be configured to connect to O3 (seventh and eighth embodiments). In this case, regarding the setting of the output frequency f _out , Δφ based on the equation (18) ′ is set as in the configurations of FIGS. 3 and 4.
Is required and the phase pull-in operation process is shown in FIG.
It is also obvious that it is exactly the same as the case of the configuration example of FIG.

[0027]

As described above in detail, according to the present invention, since the PLL configuration which directly expresses the phase error amount by the digital numerical value is used, the response of which the constant C / N value is secured can be obtained. Speeding up is possible. Further, since the operations of the first and second loops having the large and small loop gains are digitally switched, there is no discontinuous change in the frequency control voltage of the VCO at the time of switching, and further speedup is achieved. High C
/ N conversion can be achieved. Further, in realizing the present invention, the ICs of most of the circuits except the VCO are
It is possible to reduce the size, and it is easy to reduce the size, power consumption, and cost.

[Brief description of drawings]

FIG. 1 is a configuration example diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration example diagram showing a second embodiment of the present invention.

FIG. 3 is a structural example diagram showing a third embodiment of the present invention by modifying the structural example of FIG.

FIG. 4 is a configuration diagram showing a fourth embodiment of the present invention by modifying the configuration example of FIG.

5 is a structural example diagram showing a fifth embodiment of the present invention by modifying the structural example of FIG. 1. FIG.

FIG. 6 is a structural example view showing a sixth embodiment of the present invention by modifying the structural example of FIG.

7 is an equivalent tuning circuit diagram of the VCO 1'of FIG.

FIG. 8 is an equivalent circuit diagram of a loop for explaining the main points of the present invention.

9 is a diagram showing an example of the phase synchronization pull-in characteristic of FIG.

FIG. 10 is a diagram showing an example of the phase synchronization pull-in characteristic of FIG.

FIG. 11 is a diagram showing a configuration example of a conventional dual mode PLL.

[Explanation of symbols]

1 VCO 2 fixed frequency divider 3 NCO 4 reference oscillator 5 counter 6 phase comparator 7,70 averaging circuit 8,80 switching circuit 9,10 D / A converter 11 weighting synthesizer 81 summing block 82 total gain G _A Amplification block to give 83 Amplification block to give frequency modulation sensitivity K _V 84 Integration block 85 Attenuation block

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9182-5J H03L 7/10 E

Claims (9)

[Claims] 1. A voltage-controlled oscillator to which a frequency control voltage is input to obtain an output of an oscillation frequency corresponding to the frequency control voltage, and a feedback phase signal φ obtained from the output of the voltage-controlled oscillator and a reference phase signal serving as a reference. ψ and are input, and the following equation The phase comparator that outputs the phase error signal ε given by, the averaging circuit that calculates and holds the average value <ε> of the phase error signal ε, and outputs the average value <ε> are input. , Ε until the time T ₁ until the phase lock pull-in response enters a substantially steady state elapses, and after the time T ₁ elapses, <ε
A switching circuit for switching and outputting>, and a weighted combination in which the output of the switching circuit and the ε are input, and a voltage obtained by adding the former weighting higher and the latter weighting lower is added to the voltage controlled oscillator as the frequency control voltage. A frequency synthesizer having means. 2. A voltage-controlled oscillator to which a frequency control voltage is input and an output of an oscillation frequency corresponding to the frequency control voltage is obtained, a fixed frequency divider for fixedly dividing the output of the voltage-controlled oscillator, and the fixed frequency divider. A numerically controlled oscillator that accumulates the phase amount increase step value Δφ set externally according to the frequency output of the frequency divider and outputs the remainder φ when divided by 2π (radian), and a reference for giving the reference frequency of the frequency synthesizer. An oscillator, a counter for outputting a value ψ obtained by dividing the output from the reference oscillator, an output φ from the numerically controlled oscillator and an output ψ from the counter, respectively, a feedback phase signal from the voltage controlled oscillator and the Input as the reference phase signal from the reference oscillator, And a phase comparator that outputs the phase error signal ε given by
The averaging circuit that outputs ε> and the ε and the <ε> are input, and the predetermined switching time T ₁ when the phase synchronization pull-in response enters the steady state and the calculation of the average value by the averaging circuit is completed is performed. A switching circuit that switches and outputs ε until the time elapses and <ε> after the switching time T ₁ has passed, and the output of the switching circuit and the output of the phase comparator are converted into analog voltage signals. The first and second D / A converters to be converted, and the weight of the output from the first D / A converter are increased, and the weight of the output from the second D / A converter is decreased. And a weighted synthesizer for feeding back the analog-added voltage as the frequency control voltage to the voltage controlled oscillator. 3. The frequency synthesizer according to claim 2, wherein the outputs of the fixed frequency divider and the reference oscillator are input to the counter and the numerically controlled oscillator, respectively, and the output ψ of the counter and the output φ of the numerically controlled oscillator are input. 3. The frequency synthesizer according to claim 2, wherein the feedback phase signal and the reference phase signal are input to the phase comparator. 4. The frequency synthesizer according to claim 2, wherein the averaging circuit is a first averaging circuit, and an average value of the phase error signals ε from the phase comparators is calculated and stored <ε A second averaging circuit that outputs>', and the switching circuit as a first switching circuit, and the phase error signal ε from the phase comparator and the output of the second averaging circuit <ε
>', And after the completion of the switching operation by the first switching circuit (switching time T ₁ elapses), the average value by the second averaging circuit until the phase lock pull-in response enters the steady state again. The _second ε is input by switching the ε until the time T _{2 obtained} by adding the calculation time of τ and the <ε> ′ is switched after the time T ₂ has passed. The frequency synthesizer according to claim 2, further comprising: 5. The frequency synthesizer according to claim 3, wherein the averaging circuit is a first averaging circuit, and an average value of the phase error signals ε from the phase comparators is calculated and stored <ε A second averaging circuit that outputs>', and the switching circuit as a first switching circuit, and the phase error signal ε from the phase comparator and the output of the second averaging circuit <ε
>', And after the completion of the switching operation by the first switching circuit (switching time T ₁ elapses), the average value by the second averaging circuit until the phase lock pull-in response enters the steady state again. The _second ε is input by switching the ε until the time T _{2 obtained} by adding the calculation time of τ and the <ε> ′ is switched after the time T ₂ has passed. 4. The frequency synthesizer according to claim 3, further comprising: 6. A voltage controlled oscillator to which two types of frequency control voltages of relatively high gain and low gain are respectively input and an output of an oscillation frequency corresponding to the frequency controlled voltage is obtained, and an output of the voltage controlled oscillator. A fixed frequency divider that performs fixed frequency division, and a numerical control that outputs the remainder φ when the phase amount increase step value Δφ set externally according to the output timing of the fixed frequency divider is integrated and divided by 2π (radian) An oscillator, a reference oscillator for giving a reference frequency of the frequency synthesizer, a counter for outputting a value ψ obtained by dividing the output from the reference oscillator, an output φ from the numerically controlled oscillator and an output ψ from the counter. , The feedback phase signal from the voltage controlled oscillator and the reference phase signal from the reference oscillator, respectively, And a phase comparator that outputs the phase error signal ε given by
The averaging circuit that outputs ε> and the ε and the <ε> are input, and the predetermined switching time T ₁ when the phase synchronization pull-in response enters the steady state and the calculation of the average value by the averaging circuit is completed is performed. A switching circuit that switches and outputs ε until the time elapses and <ε> after the switching time T ₁ elapses, and a voltage obtained by converting the output of the switching circuit into an analog voltage signal is used as the high gain. A first D / A converter that feeds back to the voltage controlled oscillator as a frequency control voltage of the voltage control oscillator, and a voltage obtained by converting the output of the phase comparator into an analog voltage signal as the low gain frequency control voltage. And a second D / A converter which returns to the frequency synthesizer. 7. The frequency synthesizer according to claim 6, wherein the outputs of the fixed frequency divider and the reference oscillator are input to the counter and the numerically controlled oscillator, respectively, and the output ψ of the counter and the output φ of the numerically controlled oscillator are input. 7. The frequency synthesizer according to claim 6, wherein is input to the phase comparator as the feedback phase signal and the reference phase signal, respectively. 8. The frequency synthesizer according to claim 6, wherein the averaging circuit is a first averaging circuit, and an average value of the phase error signals ε from the phase comparators is calculated and stored <ε A second averaging circuit that outputs>', and the switching circuit as a first switching circuit, and the phase error signal ε from the phase comparator and the output of the second averaging circuit <ε
>', And after the completion of the switching operation by the first switching circuit (switching time T ₁ elapses), the average value by the second averaging circuit until the phase lock pull-in response enters the steady state again. The _second ε is input by switching the ε until the time T _{2 obtained} by adding the calculation time of τ and the <ε> ′ is switched after the time T ₂ has passed. 7. The frequency synthesizer according to claim 6, further comprising: 9. The frequency synthesizer according to claim 7, wherein the averaging circuit is a first averaging circuit, and an average value of the phase error signals ε from the phase comparators is calculated and stored <ε A second averaging circuit that outputs>', and the switching circuit as a first switching circuit, and the phase error signal ε from the phase comparator and the output of the second averaging circuit <ε
>', And after the completion of the switching operation by the first switching circuit (switching time T ₁ elapses), the average value by the second averaging circuit until the phase lock pull-in response enters the steady state again. The _second ε is input by switching the ε until the time T _{2 obtained} by adding the calculation time of τ and the <ε> ′ is switched after the time T ₂ has passed. 8. The frequency synthesizer according to claim 7, further comprising: