JPH05218763A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To compensate an input offset voltage due to an unbalanced current caused at a differential input stage by connecting a pinch resistor between a base of a transistor(TR) and a 1st power supply terminal being components of the differential input stage. CONSTITUTION:A collector current IQ2 of a transistor(TR) Q2 is expressed in equation I, where IC1, IC2 are currents of 1st and 2nd constant current sources 6, 7, IQ1-IQ4 are collector currents of TRs Q1-Q4, VBE is a base-emitter voltage of the TRs Q3, Q4 and RP is a resistance of a pinch resistor 8, and a collector current IQ1 of the TR Q1 is expressed in equation II. The relation of equation III is obtained because the relation of IQ3=IQ4 is in existence normally. Let the resistance RP of the resistor 8 be RP=A.beta (A is a proportional coefficient and beta is a current amplification factor), then the equation III is changed into equation IV, and equation V is derived from the equation IV compared with the equation I. When each constant is selected so as to establish the relation expressed in the equation V, the relation of IQ1=IQ2 is established independently of the current amplification factor f3. That is, an offset voltage between input terminals 1, 2 is 0V even when the current amplification factor beta is in dispersion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit using bipolar transistors.

[0002]

2. Description of the Related Art In a conventional differential amplifier circuit, as shown in FIG. 2, input stage transistors Q ₁ and Q ₂ have their bases connected to input terminals 4 and 5, respectively, and their emitters both have a first constant voltage. It is connected to the current source 6. The other terminal of the first constant current source 6 is connected to the second power supply terminal 2. The collectors of both transistors Q ₁ and Q ₂ are transistors Q ₃ and Q that form a current mirror circuit.
_{4 and} the base of the transistor Q ₃ is connected to its collector. Further, the output stage transistor Q ₅ has its base connected to the collector of the transistor Q ₄ of the current mirror circuit, and its collector connected to the second constant current source 7 and the output terminal 3. The other terminal of the second constant current source 7 is connected to the second power supply terminal 2. The emitter of this output stage transistor Q ₅ is
It is connected to the first power supply terminal 1 together with the emitters of the transistors Q ₃ and Q ₄ of the current mirror circuit. That is, the differential amplifier circuit of four transistors Q ₁ to Q ₄
And a differential input stage composed of the constant current source 6 and an output stage composed of the transistor Q ₅ and the constant current source 7.

[0003]

In the above-mentioned conventional differential amplifier circuit, since the output stage load is large with respect to the differential input stage,
Current imbalance occurs in the differential input stage. as a result,
The input offset voltage becomes several mV. Further, there is a problem that the input offset voltage increases when the current amplification factor of the transistor decreases. The description will be given below.

First, the current of the first constant current source 6 is I _C1 , the current of the second constant current source 7 is I _C2, and the current amplification factors β of the respective transistors are all equal. The collector current of the transistor Q ₂ flows through the collector of the transistor Q _{4 and} the base of the transistor Q ₅ . Where transistor Q
_Since the collector current of ₅ is equal to the current I _C2 flowing through the constant current source 7, its base current is I _C2 / β. Therefore,
The collector current of transistor Q ₂ is (I _C2 / β + I _Q4 )
Becomes However, I _Q4 is the collector current of the transistor Q ₄ .

On the other hand, the collector current of the transistor Q ₁ can be expressed as I _Q3 + (I _Q3 + I _Q4 ) / β. However, IQ ₃ is the collector current of the transistor Q ₃ .
However, since I _Q3 = I _Q4 normally, I _C2 = 2 × I
_{If Q3} ≈ I _C1 , then transistor Q ₁ and transistor Q ₂
The collector currents of are the same. However, normally, due to the stability of the amplifier circuit and the output drive capability,
Design so that I _C2 >> I _C1 . Therefore I _C2 / β>
It becomes 2 × I _Q3 / β, and the collector current of the transistor Q ₂ increases. As a result,

[0006]

An input offset voltage of is generated. Furthermore, the above equation is a function of the current amplification factor β,
Becomes lower, I _C2 >> I _Q3 + I _Q4 , so that the input offset voltage ΔV _BE increases.

[0008]

A differential amplifier circuit according to the present invention comprises a PNP type first and second transistor having respective bases connected to respective input terminals and respective emitters connected to each other; A first constant current source connected between the emitters of the first and second transistors and the first power supply terminal, the respective bases are connected to each other, the respective emitters are connected to the second power supply terminal, and the respective collectors are connected to the above. NPN-type third and fourth transistors respectively connected to the collectors of the first and second transistors, the collector of the third transistor and the third transistor
A differential input circuit in which the bases of the transistors are connected, an NPN type fifth transistor in which the collector is connected to the output terminal, the emitter is connected to the second power supply terminal, and the bases are connected to the collectors of the second and fourth transistors. An output stage circuit having a second constant current source connected between the first power supply terminal and the output terminal, the base of the third transistor and the second power supply. It is characterized by connecting a pinch resistor between the terminals.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an optimum embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a circuit diagram of an embodiment of the present invention. Transistors Q ₁ and Q ₂ having their respective bases connected to their respective input terminals and their respective emitters connected to each other, and a first constant current connected between the emitters of these two transistors and the second power supply terminal 2. Source 6,
Connect respective base mutually connects the respective emitters to the first power supply terminal 1, and, and a transistor Q _3, Q ₄ connected to respective collectors to the collectors of the transistors Q _1, Q _2, transistor A differential input circuit in which the collector of Q ₃ and its base are connected, the collector is connected to the output terminal, and the emitter is connected to the first power supply terminal 1.
And a second constant current source 7 connected between the second power supply terminal 2 and the output terminal 3 and a transistor Q ₅ whose base is connected to the collectors of the transistors Q ₂ and Q ₄ .
A pinch resistor 8 is connected between the power supply terminal 1 and the base of the transistor Q ₃ .

Next, the operation will be described. Similarly to the conventional example, the current of the first constant current source 6 is I _C1 and the current of the second constant current source 7 is I _C2 , and the transistors Q ₁ , Q ₂ , Q ₃ , Q _{4 are}
The collector currents of I _Q1 , I _Q2 , I _Q3 and I _Q4 respectively, the base-emitter voltage of transistor Q ₃ and transistor Q ₄ is V _BE , and the resistance value of pinch resistor 8 is R _P
And

First, the transistor Q₂Collector current of
Transistor Q_FourCollector and transistor Q_FiveThe ba
Transistor Q₂Collector current
Is I_Q2= I_Q4＋ I_C2/ Β. On the other hand, transistor Q₁The collector current of
V to the punch resistor 8_BE/ R_PCurrent flows, I_Q1= I_Q3+ (I_Q3＋ I_Q4) / Β + V_BE/ R_P  Becomes Usually I_Q3= I_Q4Therefore, I_Q1= I_Q4+ 2 · I_Q4/ Β / + V_BE/ R_P  Becomes

Since the base diffusion of the pinch resistor is pinched by the emitter diffusion, the current amplification factor β of the NPN transistor is directly proportional to the resistance value of the pinch resistor. Therefore, assuming that the resistance value R _P of the pinch resistor 8 is R _P = A · β (where A is a proportional coefficient),
The above equation becomes I _Q1 = I _Q4 + 2 · I _Q4 / β + V _BE / A · β = I _Q4 + (2 · I _Q4 + V _BE / A) / β. If the constants are selected so that the relation of I _C2 = 2 · I _Q4 + V _BE / A is established by comparing the formula with the formula, the current amplification factor β
The relationship of I _Q1 = I _Q2 holds regardless of the value of. That is,
The offset voltage between the input terminals 1 and 2 becomes 0V even if the current amplification factor β varies due to variations in manufacturing conditions.

For example, I _Q3 = I _Q4 = 5 μA, I _C2 = 1
00 μA, V _BE = 0.675 V, β = 100, R _P = 7
The offset voltage of the conventional differential amplifier circuit is compared with the offset voltage of the present embodiment, assuming 50 kΩ. First, in the case of the conventional example, the collector current of the transistor Q ₁ is I _Q1 = I _Q3 + 2 · I _Q3 /β=5.1 μA. On the other hand, the collector current of the transistor Q ₂ is I _Q2 = I _Q4 + I _C2 /β=6.0 μA. Therefore, from the formula, the offset voltage is

[0014]

Therefore, an offset voltage of 4.2 mV is generated. Considering that the current amplification factor β further decreases to 50, ΔV _BE = 7.7 m
The voltage V becomes V, and the offset voltage also increases as the current amplification factor β decreases.

Next, consider this embodiment. The collector current of the transistor Q ₁ is I _Q1 = 5 μA + 2 × 5 μA / 100 + 0.675 / 750 kΩ = 6.0 μA according to the formula, while the collector current of the transistor Q ₂ is I _Q2 = 5 μA + 100 μA / 100 = 6.0 μA according to the formula, I _Q1 = I _Q2 and offset voltage is 0V
become. Considering when the current amplification factor β decreases to 50, the pinch resistance also decreases in proportion to the current amplification factor β, so that R _P = 375 kΩ and I _Q1 = 5.0 μA +
2 × 5 μA / 50 + 0.675 / 375 kΩ = 7.0 μ
It becomes A. On the other hand, the collector current of the transistor Q ₂ becomes I _Q2 = 5.0 μA + 100 μA / 50 = 7.0 μA, and even if the current amplification factor β decreases, I _Q1 = I _Q2 , so the offset voltage becomes 0V.

Next, a second embodiment of the present invention will be described. FIG. 1B is a circuit diagram of the second embodiment of the present invention. In this embodiment, since the transistor Q ₆ is provided, the base currents of the transistors Q ₃ and Q ₄ can be almost ignored. Therefore, even if the current amplification factors β of the transistors Q ₃ , Q ₄ , and Q ₅ individually vary, only the base current of the transistor Q ₅ needs to be compensated by the pinch resistor 8, so that the offset voltage compensation characteristic is This is an improvement over the first embodiment.

[0018]

As described above, according to the present invention, the input offset voltage caused by the imbalance of the current generated in the differential input stage due to the large load of the output stage with respect to the differential input stage is eliminated. Since the compensation is performed by using the resistor, the input offset voltage becomes almost 0V. Further, even if the current amplification factor β of the transistor varies due to variations in manufacturing conditions, the input offset voltage is maintained at almost zero.

Further, according to the second aspect of the invention, the compensation characteristic of the input offset can be further improved.

[Brief description of drawings]

FIG. 1A is a circuit diagram of a first embodiment of the present invention. FIG. 6B is a circuit diagram of the second embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a conventional differential amplifier circuit.

[Explanation of symbols]

 1 1st power supply terminal 2 2nd power supply terminal 3 output terminal 4 1st input terminal 5 2nd input terminal 6 1st constant current source 7 2nd constant current source

Claims (2)

[Claims] 1. A PNP type first and second transistor in which respective input terminals are connected to respective bases and respective emitters are connected to each other, and the first and second transistors.
A first constant current source connected between the emitter of the transistor and the first power supply terminal, the respective bases are connected to each other, the respective emitters are connected to the second power supply terminal, and the respective collectors are connected to the first and the first power supply terminals. A differential input circuit having NPN type third and fourth transistors respectively connected to the collectors of the two transistors, and connecting the collector of the third transistor and the base of the third transistor; An NPN type fifth transistor having an emitter connected to the output terminal, a base connected to the second power supply terminal and collectors of the second and fourth transistors connected to the second power supply terminal, and connected between the first power supply terminal and the output terminal. A differential amplifier circuit including an output stage circuit having a second constant current source, and a base of the third transistor and the second power supply terminal. Differential amplifier circuit, characterized in that connecting the pinch resistor between. 2. The differential amplifier circuit according to claim 1, wherein a base is connected to a collector of the third transistor,
Connecting the emitter to the base of the third transistor,
A sixth NPN circuit having a collector connected to the first power supply terminal
Differential amplifier circuit having a type transistor.