JPH05218442A - Formation of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce an abnormal oxidation at the step parts of the high-melting point metal film or a high-melting point metal silicide film of a control gate electrode, specially at the end parts in the gate width direction of a charge storage gate electrode, in a semiconductor integrated circuit device provided with an EPROM or an EEPROM using a field-effect transistor, which is formed with the control gate electrode formed using the metal film or the metal silicide film as its main component, as a memory element. CONSTITUTION:In a method of forming a semiconductor integrated circuit device provided with an EPROM or an EEPROM, an oxidation treatment is performed on the upper surface of a control gate electrode 10 of a field-effect transistor, which is a memory element QM, after a process, in which a mask 11 for preventing oxidation (or a mask 12 for impurity transmission use) is deposited on the upper surface of the electrode 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device provided with a non-volatile memory circuit having a field effect transistor having a charge storage gate electrode and a control gate electrode as a memory element. It is related to effective technology.

[0002]

2. Description of the Related Art An electrically erasable non-volatile memory circuit (EE) mounted on a semiconductor memory circuit device or a semiconductor integrated circuit device.
PROM: E lectrically E rasable P rogrammable R e
ad O nly M emory) as a collective erasing method tends to is adopted. The EEPROM that uses the batch erase method is
Since the storage element for storing 1 [bit] of information is composed of one field effect transistor and the occupied area of the storage element is small, it is suitable for high integration (large storage capacity).

The field effect transistor, which is the storage element, has a charge storage gate electrode and a control gate electrode, and a source region and a drain region are formed on both sides of the charge storage gate electrode and the control gate electrode in the gate length direction. Each is composed. The charge storage gate electrode is usually formed of a polycrystalline silicon film. The control gate electrode extends along the upper and side portions of the charge storage gate electrode in the gate width direction, is electrically connected to the word line in the gate width direction, and is integrally formed. Therefore, since the gate electrode and the word line regulate the selection speed of the memory element in each of the information writing operation and the information reading operation, a laminated film having a small resistance value is adopted as the gate electrode material. As the laminated film forming the control gate electrode and the word line, for example, a polycrystalline silicon film and a WSix film having a resistance value smaller than that of the polycrystalline silicon film formed thereon (called a polycide film) are used. It

Each of the source region and the drain region is p
The n-type semiconductor region is formed on the main surface of the type semiconductor substrate or the main surface of the p-type well region. The source area is
Compared to the drain region, the diffusion amount from the gate electrode end to the channel formation region side in the gate length direction (the overlapping area with the charge storage gate electrode) is formed larger, and the overlapping area between the source region and the charge storage gate electrode is It is configured as a tunnel area.

EEPR adopting the above-mentioned batch erase method
The memory element of the OM is formed based on the following manufacturing process.

First, a charge storage gate electrode forming film and a control gate electrode forming film are sequentially laminated on the main surface of a p-type semiconductor substrate. The control gate electrode forming film is formed of a laminated film of a polycrystalline silicon film deposited by the CVD method and a WSix film deposited by the sputtering method or the CVD method.

Next, the WSix film as the control gate electrode forming film is subjected to thermal oxidation treatment to form an oxide film on the surface of the WSix film. This oxide film suppresses the introduction of n-type impurities, particularly As, forming the source region and the drain region into the WSix film, and prevents defects such as peeling of the WSix film above the laminated film.

Next, each of the control gate electrode forming film and the charge storage gate electrode forming film is patterned to form a control gate electrode and a charge storage gate electrode.
The word line is formed in the same step as the step of forming the control gate electrode.

Next, a thermal oxidation process is performed to form an oxide film for impurity transmission on the main surface of each formation region of the source region and the drain region of the p-type semiconductor substrate. This impurity-transmitting oxide film forms the source region and the drain region, respectively.
It is possible to prevent damage to the main surface of the p-type semiconductor substrate, invasion of contaminants, and the like that occur when introducing type impurities.

Next, the control gate electrode and the charge storage gate electrode are used as a main body of an impurity introduction mask, and n-type impurities are ion-implanted into the main surface of each of the formation regions of the source region and the drain region of the p-type semiconductor substrate. For example, As is introduced. Then, each of the control gate electrode, the charge storage gate electrode, and the mask covering the drain region is used as the main body of the impurity introduction mask, and the diffusion coefficient of the diffusion coefficient of the p-type semiconductor region is formed by ion implantation. A large n-type impurity such as P is introduced. This n-type impurity is introduced into the main surface of the p-type semiconductor substrate through the impurity transmitting oxide film.

Next, a thermal diffusion process is performed to stretch and diffuse the introduced n-type impurities to form a source region and a drain region, respectively. Since P having a large diffusion coefficient is introduced as an n-type impurity in the source region and the thermal diffusion process is performed for a relatively long time, the amount of diffusion toward the channel formation region side is increased to form a tunnel region.

[0012]

However, the EEPROM adopting the batch erase method described above does not consider the following points.

(1) EEP adopting the batch erasing method
In the ROM, the control gate electrode of the field effect transistor, which is a storage element, is formed of a laminated film in which a WSix film is laminated on the polycrystalline silicon film for the purpose of reducing the resistance value.
After the deposition, the upper layer WSix film of this laminated film is oxidized by a plurality of oxidation processes such as at least a thermal oxidation process for forming an oxide film on the surface of the WSix film and a thermal oxidation process for forming an oxide film for impurity permeation. It For example, as reported in the following document, the laminated film has a small density at the step portion of the upper WSix film, and the WSix generated during the oxidation treatment.
The film stress causes abnormal oxidation of the WSix film at the step portion. In particular, the field effect transistor, which is the storage element of the non-volatile storage circuit adopting the batch erase method,
It has a two-layer gate structure of a charge storage gate electrode and a control gate electrode, and includes the film thickness of the charge storage gate electrode (and the film thickness of the gate insulating film on the surface thereof) at the end of the charge storage gate electrode in the gate width direction. ) Is formed, abnormal oxidation occurs in the WSix film of the word line at this step. Moreover, one word line is connected to a plurality of storage elements, and at least two stepped portions are generated for each storage element. Therefore, the cross-sectional area of the WSix film of the word line is remarkably reduced at the step portion, and the resistance value of the word line is increased, so that the information reading operation speed of the EEPROM adopting the batch erasing method becomes slow. Further, since the WSix film of the word line is broken at the step portion, the EEPROM adopting the batch erasing method has a malfunction. Regarding the abnormal oxidation at the stepped portion of the laminated film described above, see, for example, Oki Electric R & D, No. 135.
No. 3, Vol. 54 No. 3, pp. 79-84, "CV
D WSix-Polycide Gate Electrode Technology Development ".

(2) EEP adopting the batch erasing method
In the manufacturing process of the ROM, since the control gate electrode and the word line of the field effect transistor which is a memory element use the laminated film formed of the polycrystalline silicon film and the WSix film, as described above, at least the laminated film WSix is formed. The number of steps for forming an oxide film on the surface of the film is increased.

The objects of the present invention are as follows.

(1) A field effect transistor in which a control gate electrode mainly composed of a refractory metal film or a refractory metal silicide film is formed along a sidewall of a charge storage gate electrode and a gate width direction is used as a memory element. In a semiconductor integrated circuit device having an ultraviolet erasable or electrically erasable non-volatile memory circuit, a step portion of the refractory metal film or refractory metal silicide film of the control gate electrode, particularly the end of the charge storage gate electrode in the gate width direction. Provide a technique for reducing abnormal oxidation in parts.

(2) To provide a technique for achieving the above object (1) and increasing the operating speed of a semiconductor integrated circuit device having an ultraviolet erasable or electrically erasable nonvolatile memory circuit.

(3) A technique for achieving the above object (1) and preventing malfunction of a semiconductor integrated circuit device having an ultraviolet erasable or electrically erasable nonvolatile memory circuit is provided.

(4) To provide a technique for achieving the above object (1) and reducing the number of steps in the manufacturing process of a semiconductor integrated circuit device having an ultraviolet erasable or electrically erasable nonvolatile memory circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0021]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) A refractory metal film or refractory metal film formed of a refractory metal film or a refractory metal silicide film along the upper portion of the charge storage gate electrode and the side wall in the gate width direction, or on a polycrystalline silicon film. A field effect transistor in which a control gate electrode in which a silicide film is laminated is formed, and a source region and a drain region are formed on both sides of the charge storage gate electrode and the control gate electrode in the gate length direction is used as a storage element. In the method for forming a semiconductor integrated circuit device having an ultraviolet erasable or electrically erasable nonvolatile memory circuit, the following steps (A) to (D) are provided. (A)
A charge storage gate electrode and a control gate electrode of a field effect transistor, which is a storage element of the nonvolatile memory circuit, are formed on a substrate, and a refractory metal film or a refractory metal silicide film of the control gate electrode is formed on an upper surface thereof. A step of depositing an oxidation-resistant mask, (B) using the mask formed in the step (A) as an oxidation-resistant mask, performing oxidation treatment, and forming a source region and a drain region on the substrate, respectively. A step of forming an oxide film for impurity transmission, (C) using the mask formed in the step (A), and forming in the source region and the drain region of the substrate in the step (B) A step of introducing a predetermined conductivity type impurity by ion implantation through the impurity transmitting oxide film, (D) heat treatment is performed, and the predetermined conductivity type impurity introduced in the step (B) is expanded. Alms to form a respective source region, a drain region.

(2) The step of depositing the oxidation-resistant mask of the step (A) described in the above means (1) includes the upper surface and the side wall of the refractory metal film or refractory metal silicide film of the control gate electrode. And a step of depositing an oxidation resistant mask on each of the formation regions of the source region and the drain region on the substrate.

(3) The heat treatment for forming each of the source region and the drain region in the step (D) described in the above means (1) or means (2) is performed in an atmosphere containing a trace amount of oxygen.

(4) The field effect transistor described in the above-mentioned means (3) is formed as a memory element of a non-volatile memory circuit adopting the collective erasing method, and the field effect transistor of this memory element is of the step (D). Before or after heat treatment is performed in an atmosphere containing a small amount of oxygen, the diffusion amount of the source region into the channel formation region is made larger than that of the drain region, and a tunnel region is formed.

[0026]

According to the above-mentioned means (1), the following operational effects can be obtained. (A) In the method for forming a semiconductor integrated circuit device having a non-volatile memory circuit, the oxide is deposited in the step (A) during the oxidation treatment for forming the impurity-permeable oxide film in the step (B). Since the mask is used as an oxidation-resistant mask and the upper surface of the refractory metal film or refractory metal silicide film of the control gate electrode of the field effect transistor which is a memory element is covered, this refractory metal film or refractory metal silicide film is used. Of the upper surface of the charge storage gate electrode, particularly abnormal oxidation in the stepped region at the end of the charge storage gate electrode in the gate width direction can be reduced. (B) In a method for forming a semiconductor integrated circuit device having a non-volatile memory circuit, when introducing a predetermined conductivity type impurity by the ion implantation in the step (C), the mask deposited in the step (A) is used as an impurity. Since it is used as an introduction mask and covers the upper surface of the refractory metal film or refractory metal silicide film of the control gate electrode of the field effect transistor as a memory element, the refractory metal film or refractory metal of the predetermined conductivity type impurity is used. The introduction into the silicide film is reduced, and as a result, the step of oxidizing the surface of the refractory metal film or the refractory metal silicide film to form an oxide film can be eliminated, and the upper part of the refractory metal film or the refractory metal silicide film can be eliminated. It is possible to reduce surface oxidation, particularly abnormal oxidation in the step region at the end of the charge storage gate electrode in the gate width direction. (C) Since the operational effect (a) and the operational effect (b) are obtained, the control gate electrode (or word line) of the field effect transistor, which is a memory element, is the end portion of the charge storage gate electrode in the gate width direction. It is possible to suppress the reduction of the cross-sectional area in (2) (the resistance value of the word line can be reduced), and the disconnection defect can be reduced.

According to the above-mentioned means (2), the following action and effect can be obtained in addition to the action and effect (1). (A) In a method of forming a semiconductor integrated circuit device having a non-volatile memory circuit, in the same step as the step of depositing the oxidation resistant mask, impurities for transmitting impurities are formed in each of a source region and a drain region on a substrate. Since the mask corresponding to the oxide film can be formed, the number of manufacturing steps can be reduced by the amount corresponding to the step of forming the impurity transmitting oxide film (step (C) of claim 1). (B) In the method for forming a semiconductor integrated circuit device having a non-volatile memory circuit, the refractory metal film or refractory metal silicide film of the control gate electrode is coated with an oxidation resistant mask on the upper surface and side surfaces thereof. It is possible to further reduce the oxidation of the upper surface of the refractory metal film or the refractory metal silicide film, particularly abnormal oxidation in the step region at the end of the charge storage gate electrode in the gate width direction. According to the above-mentioned means (3), the diffusion coefficient of the predetermined conductivity type impurity can be increased and the diffusion coefficient of the predetermined conductivity type impurity can be increased by including a trace amount of oxygen in the atmosphere of the heat treatment of the step (D). Even if the size is increased, since the oxidation resistant mask is formed in the preliminary step (A), oxidation of the upper surface of the refractory metal film or the refractory metal silicide film of the control gate electrode, especially the charge storage gate electrode Abnormal oxidation is suppressed in the step region at the end in the gate width direction.

According to the above-mentioned means (4), the source region of the field effect transistor, which is a storage element of the batch erasing type nonvolatile memory circuit, is subjected to heat treatment for a long time by the amount of forming the tunnel region. Even if this long-time heat treatment is performed, since the oxidation resistant mask is formed in the preliminary step (A), oxidation of the upper surface of the refractory metal film or refractory metal silicide film of the control gate electrode, In particular, abnormal oxidation is suppressed in the step region at the end of the charge storage gate electrode in the gate width direction.

The structure of the present invention will be described below with reference to an embodiment in which the present invention is applied to a semiconductor integrated circuit device having an EEPROM adopting the batch erase method.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and their repeated description will be omitted.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an EEPROM adopting a batch erasing method mounted on a semiconductor integrated circuit device which is an embodiment of the present invention. In FIG. 1, (A) is an EEPROM on the left side.
Shows a cross section of the memory element cut in the gate length direction, a cross section of the high breakdown voltage element of the peripheral circuit in the center, and a cross section of the low breakdown voltage element of the peripheral circuit on the right side. (B) shows a cross section of the memory element taken in the gate width direction.

As shown in FIGS. 1A and 1B, a semiconductor integrated circuit device equipped with an EEPROM adopting a batch erasing method is mainly composed of a p--type semiconductor substrate 1. In the p- type semiconductor substrate 1, a p type well region 2 is formed in a region where an n channel conductivity type field effect transistor is formed, and an n type well region (not shown) is formed in a region where a p channel conductivity type field effect transistor is formed. Composed.

As shown in the left side of FIG. 1A and FIG. 1B, the memory element Q _M is formed on the main surface of the p-type well region 2 in the region defined by the element isolation region. ,
It is composed of an n-channel conductivity type field effect transistor.
The element isolation region is mainly composed of a field insulating film (silicon oxide film) 3 and a p-type channel stopper region 4 formed on the main surface of the p-type well region 2.

The memory element Q _M, that is, the field effect transistor, includes a channel forming region (p-type well region 2), a gate insulating film (tunnel oxide film) 6, a gate insulating film 8, a charge storage gate electrode 7, a control gate electrode 10, The n + type semiconductor region 14 which is the source region, the n + type semiconductor region 13 which is the drain region, and the tunnel region are mainly constituted.

The charge storage gate electrode 7 is formed on the gate insulating film 6, and one end and the other end of the charge storage gate electrode 7 in the gate width direction are respectively formed of the field insulating film 3 as shown in FIG. Extends to the top of the. The charge storage gate electrode 7 is formed in the first layer gate material forming step in the manufacturing process of the collective erasing type EEPROM, and is formed of, for example, a polycrystalline silicon film.

The control gate electrode 10 is formed on the charge storage gate electrode 7 with the gate insulating film 8 interposed therebetween. Each of the one end and the other end of the control gate electrode 10 in the gate width direction is
As shown in FIG. 1B, the word line 10WL is electrically connected and integrally formed. The word line 10WL is
The end portions of the charge storage gate electrode 7, which are peculiar to the two-layer gate electrode structure of the field effect transistor having the charge storage gate electrode 7, are formed along the respective side surfaces of the charge storage gate electrode 7 in the gate width direction. It extends along the steps of.
Each of the control gate electrode 10 and the word line 10WL is formed in the second layer gate material forming step in the manufacturing process. For example, the polycrystalline silicon film 10A and WSix on top thereof are formed.
It is formed of a laminated film (polycide film) in which the films 10B are laminated. In addition to this, the laminated film has MoSi on top of the polycrystalline silicon film.
x film, TaSix film, TiSix film, or other laminated film in which a refractory metal silicide film is laminated, or a W film on a polycrystalline silicon film,
It may be replaced with a laminated film in which refractory metal films such as Mo film, Ta film, and Ti film are laminated. Further, the laminated film may be replaced with a single layer film of the refractory metal silicide film or the refractory metal film.

Each of the control gate electrode 10 and the charge storage gate electrode 7 is patterned by anisotropic etching using the same etching mask together with an oxidation resistant mask (11) which will be described later, so-called overlapping cutting. ..

N + type semiconductor region 1 which is the source region
4. The n + type semiconductor region 13 serving as the drain region is formed on the p type well region 2 on both sides of the charge storage gate electrode 7 and the control gate electrode 10 in the gate length direction.
Is formed on the main surface portion of, and is self-aligned with the charge storage gate electrode 7 and the control gate electrode 10. The n + type semiconductor region 14 which is the source region is formed to have a larger diffusion amount (junction depth) toward the channel formation region side than the n + type semiconductor region 8 which is the drain region. The charge storage gate electrode 7 on the channel formation region side of the n + type semiconductor region 14
The duplicated portions of each form a tunnel region.

The n + type semiconductor region 13 which is the drain region of the field effect transistor which is the memory element Q _M is connected to the data line (DL) 20 through the connection hole 19 formed in the interlayer insulating film 18. The data line 20 is formed in the first layer wiring material forming step in the manufacturing process, and is formed mainly of, for example, either an aluminum film or an aluminum alloy film. The aluminum alloy film is an aluminum film to which at least one of Cu that improves migration resistance and Si that improves alloy spike resistance is added. A final protective film 21 is formed on the data line 20.

A mask 11 that can be used for at least oxidation resistance is formed on the upper surfaces of the control gate electrode 10 of the field effect transistor that is the memory element Q _M and the WSix film 10B of each of the word lines 10WL. This mask 11 is formed on the upper surface of the WSix film 10B as described above.
In particular, the surface of the step region at the end of the charge storage gate electrode 7 in the gate width direction can be covered, and abnormal oxidation in this region can be reduced. Further, the mask 11 removes the WSix film 10B due to the ion implantation of an element having a relatively large atomic weight in the WSix film 10B, for example, an n-type impurity (for example, As) forming a source region or a drain region. It can be prevented. The mask 11 is formed of, for example, a silicon oxide film deposited by a CVD method without subjecting the WSix film 10B to oxidation treatment, and is formed to have a film thickness of about 50 to 200 [nm]. Further, the mask 11 may be formed of any of a silicon oxide film deposited by a sputtering method, a silicon nitride film deposited by a CVD method, and a silicon nitride film deposited by a sputtering method.

Further, the control gate electrode 10 and the word line 10WL of the field effect transistor which is the memory element Q _M.
Impurity transmitting masks 12 are formed on the upper surface of each WSix film 10B in the region where the mask 11 is interposed, the source region, and the drain region. The impurity transmitting mask 12 reduces damage to the main surface of the p-type well region 2 that occurs when n-type impurities forming the source region and the drain region are introduced by ion implantation, and the p-type well region is also formed. It is possible to prevent the entry of pollutants into the inside. further,
The impurity transmission mask 12 covers the side surface (and upper surface) of the WSix film 10B of the control gate electrode 10 and is also used as an oxidation resistant mask. The impurity transmission mask 12 is formed of, for example, a silicon oxide film deposited by a CVD method and has a film thickness of about 10 to 50 [nm]. Further, the impurity transmission mask 12 may be formed of any one of a silicon oxide film deposited by a sputtering method, a silicon nitride film deposited by a CVD method, and a silicon nitride film deposited by a sputtering method, like the mask 11. ..

The high breakdown voltage element Q _H of the peripheral circuit of the EEPROM adopting the batch erasing method is formed on the main surface of the p type well region 2 in the region defined by the element isolation region, and has the n-channel conductivity type field effect. Composed of transistors. The field effect transistor, which is the high breakdown voltage element Q _H , is mainly composed of a channel formation region (p-type well region 2), a gate insulating film 5, a gate electrode 7, a source region and a drain region. Although not limited to this, the gate electrode 7 is formed in the same manufacturing process as the charge storage gate electrode 7 of the field effect transistor which is the memory element Q _M. Each of the source region and the drain region has a low impurity concentration n-type semiconductor region 15 and a high impurity concentration n + -type semiconductor region 17, respectively.
Composed of. In other words, the field effect transistor is a high-voltage element Q _H is composed of LDD (L ightly D oped D rain ) structure. A side wall spacer 16 is formed on the side wall of the gate electrode 7 in the gate length direction.

The low voltage element Q _L of the peripheral circuit is configured on the main surface of the p-type well region 2 in the region defined around the element isolation region, formed of an n-channel conductivity type field effect transistor. The field effect transistor is a low breakdown voltage element Q _L, a channel formation region (p-type well region 2), the gate insulating film 9, a gate electrode 10, composed mainly of a source region and a drain region. Gate electrode 10
Is formed in the same manufacturing process as the control gate electrode 10 of the field effect transistor which is the memory element Q _M , although not limited thereto. Each of the source region and the drain region has a low impurity concentration n-type semiconductor region 15 and a high impurity concentration n.
It is composed of a + type semiconductor region 17. In other words, the field effect transistor is a low breakdown voltage element Q _L is composed of the LDD structure.

Next, the EE adopting the above-mentioned batch erase method.
A method of forming a semiconductor integrated circuit device having a PROM will be briefly described with reference to FIGS. 2 to 11 (sectional views of relevant parts showing each step of the manufacturing process).

First, the p-type well region 2 and the n-type well region are formed on the main surface of the p-type semiconductor substrate 1. After that, the field insulating film 3 and the p-type channel stopper region 4 are formed on the main surface of the inactive region of the p-type well region 2, and the field insulating film is formed on the main surface of the inactive region of the n-type well region (not shown). The film 3 is formed. Hereinafter, the method of forming the field effect transistor in the n-type well region will be omitted.

Next, as shown in FIG. 2, the gate insulating film 5 is formed on the main surface of the active region of the p-type well region 2. As the gate insulating film 5, a silicon oxide film formed by, for example, a thermal oxidation method is used in order to secure high withstand voltage characteristics, and this silicon oxide film is formed with a film thickness of about 20 to 50 [nm].

Next, in the formation region of the memory element Q _M ,
The gate insulating film 5 is removed, and as shown in FIG. 3, a gate insulating film 6 is newly formed in the region where the gate insulating film 5 is removed. Since the gate insulating film 6 is used as a tunnel oxide film, for example, a silicon oxide film that is oxidized at about 800 [° C.] is used and is formed to have a film thickness of about 8 to 12 nm.

Next, as shown in FIG. 4, the charge storage gate electrode 7A is formed on the gate insulating film 6 in the formation region of the memory element Q _M , and the gate insulating film 5 is formed on the formation region of the high breakdown voltage element Q _H. Each of the gate electrodes 7 is formed. Charge storage gate electrode 7 formed in the formation region of the storage element Q _M
In the step A, the gate width dimension is fixed and the gate length dimension is not fixed in this step. As described above, each of the charge storage gate electrode 7A and the gate electrode 7 is formed of a polycrystalline silicon film deposited by the CVD method, for example, 100 to
It is formed with a film thickness of about 200 [nm].

Next, as shown in FIG. 5, a gate insulating film 8 is formed on the entire surface of the substrate including the upper surface of the charge storage gate electrode 7A in the formation region of the memory element Q _M. Although not limited to this structure, the gate insulating film 8 is not limited to the charge storage gate electrode 7
It is formed of a laminated film in which a silicon oxide film 8A obtained by oxidizing the surface of A, a silicon nitride film 8B deposited by a CVD method or a sputtering method, and a silicon oxide film 8C obtained by oxidizing the silicon nitride film 8B are sequentially laminated. The gate insulating film 8 is formed to have a film thickness of about 15 to 40 [nm] when converted to a silicon oxide film.

Next, of the gate insulating film 8, the gate insulating film 8 in the formation region of the memory element Q _M is left and the other gate insulating films 8 are removed. Thereafter, as shown in FIG. 6, in the formation region of the low voltage element Q _L, a gate insulating film 9 on the main surface of the active region of the p-type well region 2.
The gate insulating film 9 is formed of a silicon oxide film oxidized by a thermal oxidation method and has a film thickness of about 10 to 30 [nm].

Next, a polycrystalline silicon film is formed on the entire surface of the substrate including the surface of the gate insulating film 8 in the formation region of the memory element Q _M and the surface of the gate insulating film 9 in the formation region of the low breakdown voltage element Q _L. 10A, the WSix film 10B, and the mask 11 are sequentially laminated. The polycrystalline silicon film is deposited by, for example, the CVD method,
It is formed with a film thickness of about 100 to 200 [nm]. WS
The ix film 10B is deposited by, for example, a CVD method or a sputtering method, and is formed to have a film thickness of about 100 to 200 [nm]. The mask 11 is formed under the above-mentioned conditions. By forming this mask 11, the step of forming an oxide film on the surface of the WSix film 10B by an oxidation treatment can be omitted.

Next, as shown in FIG. 7, the mask 11, the WSix film 10B, the polycrystalline silicon film 10A, the gate insulating film 8 and the charge storage gate electrode 7A are sequentially patterned in the formation region of the memory element Q _M. The charge storage gate electrode 7, the control gate electrode 10, the word line 10WL,
Each of the masks 11 is formed. The patterning is R
It is performed by overlapping cutting using anisotropic etching such as IE. Patterning is performed in a region of the memory element Q _M, the low voltage element Q _L, in the formation region of each of the high-voltage element Q _H is not performed.

When the patterning is performed,
In the formation region of the memory element Q _M , the gate insulating film (tunnel oxide film) 6 is over-etched to have a film thickness of about half. The gate insulating film 6 having the reduced thickness cannot secure the function as an oxide film for transmitting impurities.

Next, as shown in FIG. 8, the side surface of the WSix film 10B of the control gate electrode 10 in the formation region of the memory element Q _M , the surface of the formation region of the source region, and the surface of the formation region of the drain region are respectively removed. An impurity transmitting mask 12 is formed over the entire surface of the substrate including the mask. The impurity transmitting mask 12 is formed under the above-mentioned conditions. By forming the impurity transmitting mask 12, the step of forming the impurity transmitting mask by the oxidation treatment can be omitted.

Next, as shown in FIG. 9, in the formation region of the memory element Q _M , the mask 11, the control gate electrode 10 and the charge storage gate electrode 7 are used as the main body of the impurity introduction mask, and the p-type well region 2 is formed. An n-type impurity is introduced into the main surface of the n-type semiconductor region 13 to form n + -type semiconductor regions 13 used as the source region and the drain region, respectively. As the n-type impurity, for example, As is used and is introduced by ion implantation through the impurity transmitting mask 12. The introduction of n-type impurities is performed without using an impurity introduction mask formed of a photoresist film, that is, so-called maskless.

Next, in the forming region of the low voltage element Q _L, WSix film 10B, subjected to patterning in each of the polycrystalline silicon film 10A, thereby forming the gate electrode 10.

Next, as shown in FIG. 10, the memory element Q _M
In the region where the source region of the field effect transistor is formed, the n-type impurity 14n is introduced to form the n + -type semiconductor region 14 which is the source region. n-type impurity 14n
Is introduced through the impurity transmission mask 12 by ion implantation using P, which has a higher diffusion rate than As described above. When introducing the n-type impurity 14n, the mask 11,
The gate electrode 10, the photoresist film shown by the alternate long and short dash line, etc. are used as an impurity introduction mask.

Since the n-type impurity 14n is diffused by stretching after being introduced, and the diffusion rate of the n-type impurity 14n itself is high and heat treatment is performed for a relatively long time, the n + -type semiconductor region which is the source region. 14 has a large diffusion amount toward the channel formation region side. The overlapping region between the n + type semiconductor region 14 and the charge storage gate electrode 7 is used as a tunnel region. Further, the heat treatment may be performed in a nitrogen gas or argon gas atmosphere containing a trace amount of oxygen.
In this case, a slight amount of oxygen contained in the atmosphere can accelerate the diffusion rate of the n-type impurities.

The n + type semiconductor region 1 which is the source region
When the step of forming 4 is completed, the field effect transistor which is the memory element Q _M is almost completed.

Next, in the formation regions of the low breakdown voltage element Q _L and the high breakdown voltage element Q _H , the low impurity concentration n-type semiconductor region 15, the side wall spacer 16, and the high impurity concentration n + type semiconductor region 17 are formed. Form each one. This n +
When forming a type semiconductor region 17 is completed, the low voltage element Q _L, field effect transistors of each of the high-voltage element Q _H is almost completed.

Next, the interlayer insulating film 18, the connection hole 19, the wiring 20, and the final protective film 21 are sequentially formed to complete the semiconductor integrated circuit device having the EEPROM adopting the batch erasing method.

The semiconductor integrated circuit device having the EEPROM adopting the batch erasing method configured as described above has the following effects.

(1) The control gate electrode 10 is formed along the upper portion of the charge storage gate electrode 7 and the side wall in the gate width direction. The charge storage gate electrode 7 and the control gate electrode 10 are formed.
Of the source region (n + type semiconductor region 14) and drain region (n + type semiconductor region 1) on both sides in the gate length direction of
3) In the method of forming a semiconductor integrated circuit device having an EEPROM adopting the collective erasing method, in which the field effect transistor in which each is formed is a storage element Q _M , the following steps (A) to (D) are performed. Prepare (A) The EEP
The charge storage gate electrode 7 and the control gate electrode 10 of the field effect transistor, which is the storage element Q _M of the ROM, are formed on the substrate, and WSix of the control gate electrode 10 is formed.
A step of depositing an oxidation resistant mask 11 (or an impurity transmission mask 12) on the upper surface of the film 10B, (B) using the mask 11 formed in the step (A) as an oxidation resistant mask, and performing an oxidation treatment. And (C) using the mask 11 formed in the step (A) to form an impurity-transmitting oxide film in each of the formation regions of the source region and the drain region on the p-type well region 2. a step of introducing a predetermined conductivity type impurity into the source region and the drain region of the p-type well region 2 by ion implantation through the impurity transmitting oxide film formed in the step (B); and (D) heat treatment. And a predetermined conductivity type impurity introduced in the step (B) is stretched and diffused to form a source region and a drain region. With this configuration, the following operational effects can be obtained. (A) In the method of forming a semiconductor integrated circuit device having an EEPROM, the mask 11 deposited in the step (A) is removed during the oxidation treatment for forming the impurity-permeable oxide film in the step (B). Since the upper surface of the WSix film 10B of the control gate electrode 10 of the field effect transistor which is the memory element Q _M is covered by using it as an oxidation resistant mask, the upper surface of the WSix film 10B is oxidized, particularly the charge storage gate electrode 7 is oxidized. It is possible to reduce abnormal oxidation in the step region at the end in the gate width direction. (B) In a method of forming a semiconductor integrated circuit device having an EEPROM, when introducing a predetermined conductivity type impurity by the ion implantation in the step (C), the mask 11 deposited in the step (A) is used as an impurity introduction mask. Since the upper surface of the WSix film 10B of the control gate electrode 10 of the field effect transistor, which is the storage element Q _M , is covered, the WS of the predetermined conductivity type impurity is used.
The introduction into the ix film 10B can be reduced, and as a result, the step of oxidizing the surface of the WSix film 10B to form an oxide film can be eliminated, and the oxidation of the upper surface of the WSix film 10B, especially the gate width of the charge storage gate electrode 7 can be eliminated. It is possible to reduce abnormal oxidation in the step region at the end in the direction. (C) Since the operational effect (a) and the operational effect (b) are obtained, the control gate electrode 10 (or word line 10WL) of the field effect transistor, which is the memory element Q _M , is the gate of the charge storage gate electrode 7. It is possible to suppress the reduction of the cross-sectional area at the end portion in the width direction (the resistance value of the word line 10WL can be reduced), and the disconnection defect can be reduced.

(2) The step of depositing the oxidation-resistant mask 11 of the step (A) described in the above means (1) is performed by the upper surface of the WSix film 10B of the control gate electrode 10, the side wall and the source region, and the drain. This is a step of depositing the impurity transmission mask 12 in each formation region of the regions. With this configuration, the following operational effects can be obtained. (A) EEPROM
In the method for forming a semiconductor integrated circuit device including:
Since a mask corresponding to the impurity-transmitting oxide film can be formed in each of the source region and drain region forming regions of the p-type well region 2, the step of forming the impurity-transmitting oxide film (the step (C of the means (1) (C)). )), The number of manufacturing steps can be reduced. (B) In the method of forming a semiconductor integrated circuit device having an EEPROM, the control gate electrode 10
Since the upper surface and the side surface of the WSix film 10B are covered with the impurity transmitting mask 12, the upper surface of the WSix film 10B is oxidized, particularly, the abnormal oxidation in the step region of the end of the charge storage gate electrode 7 in the gate width direction. Can be further reduced.
(C) The impurity transmission mask 12 is formed by a deposition method, and has a thin film thickness that is substantially equal to the film thickness formed on the surface of each of the source region and the drain region, and the charge storage gate electrode 7 and the control gate electrode 10. because it is formed on the side wall of each of, it can prevent the offset structure of the field effect transistor is a storage element Q _M.

(3) The heat treatment for forming each of the source region and the drain region in the step (D) described in the above means (1) or means (2) is performed in an atmosphere containing a trace amount of oxygen. With this configuration, by containing a trace amount of oxygen in the atmosphere of the heat treatment of the step (D), the diffusion coefficient of the predetermined conductivity type impurity can be increased, and even if the diffusion coefficient of the predetermined conductivity type impurity is increased, Since the oxidation resistant mask 11 (or the impurity transmission mask 12) is formed in the step (A), the oxidation of the upper surface of the WSix film 10B of the control gate electrode 10, especially the gate width of the charge storage gate electrode 7 is performed. The abnormal oxidation in the step region at the end in the direction is suppressed.

(4) The field effect transistor described in the above-mentioned means (3) is an EEPROM adopting a collective erasing method.
Of the storage element Q _M , the field effect transistor of the storage element Q _M is subjected to heat treatment in an atmosphere containing a slight amount of oxygen before or after the step (D), and the drain region (1
As compared with 3), the diffusion amount of the source region (14) into the channel formation region is increased, and a tunnel region is formed. With this configuration, the EEPRO adopting the batch erasing method
The source region of the field effect transistor, which is the memory element Q _M of _M , is subjected to the heat treatment for a long time due to the formation of the tunnel region, but even if the heat treatment for a long time is performed, the prediction step (A) is performed. Since the oxidation resistant mask 11 is formed by
Oxidation of the upper surface of the WSix film 10B of the control gate electrode 10, especially abnormal oxidation in the stepped region at the end of the charge storage gate electrode 7 in the gate width direction can be suppressed.

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to EEPROMs other than the EEPROM adopting the batch erase method.

The present invention also provides an ultraviolet erasable nonvolatile memory.
Memory circuit (EPROM:ErasableProgrammableRead
OnlyMa semiconductor memory circuit device having an emory) or
It can be applied to semiconductor integrated circuit devices.

[0070]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

(1) A field effect transistor in which a control gate electrode mainly composed of a refractory metal film or a refractory metal silicide film is formed along the upper portion of the charge storage gate electrode and the side wall in the gate width direction is used as a memory element. In a semiconductor integrated circuit device having an ultraviolet erasable or electrically erasable non-volatile memory circuit, a step portion of the refractory metal film or refractory metal silicide film of the control gate electrode, particularly the end of the charge storage gate electrode in the gate width direction. The abnormal oxidation in the part can be reduced.

(2) In addition to the effect (1), the operation speed of the semiconductor integrated circuit device provided with the ultraviolet erasable or electrically erasable nonvolatile memory circuit can be increased.

(3) In addition to the effect (1), it is possible to prevent malfunction of the semiconductor integrated circuit device having the ultraviolet erasable or electrically erasable nonvolatile memory circuit.

(4) In addition to the effect (1), it is possible to reduce the number of steps in the manufacturing process of the semiconductor integrated circuit device having the ultraviolet erasable or electrically erasable nonvolatile memory circuit.

[Brief description of drawings]

FIG. 1A is a cross-sectional view of a main part of a nonvolatile memory circuit adopting a batch erasing method mounted in a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 1B shows the nonvolatile memory circuit. FIG. 13 is a cross-sectional view of another region of a memory element.

FIG. 2 is a sectional view of an essential part in a first step of a manufacturing process of the semiconductor integrated circuit device.

FIG. 3 is a sectional view of an essential part in a second step.

FIG. 4 is a sectional view of an essential part in a third step.

FIG. 5 is a sectional view of a main part in a fourth step.

FIG. 6 is a sectional view of a main part in a fifth step.

FIG. 7 is a sectional view of an essential part in a sixth step.

FIG. 8 is a sectional view of an essential part in a seventh step.

FIG. 9 is a sectional view of an essential part in an eighth step.

FIG. 10 is a sectional view of an essential part in a ninth step.

FIG. 11 is a sectional view of a key part in a tenth step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Well region, 5, 6, 8, 9 ... Gate insulating film, 7 ... Gate electrode, 10 ... Gate electrode, 10
A ... Polycrystalline silicon film, 10B ... WSix film, 10WL ... Word line, 13, 14, 15, 17 ... Semiconductor region, 11,
12 ... Mask.

Claims (4)

[Claims] 1. A refractory metal film or refractory metal silicidation film formed on a polycrystalline silicon film or a refractory metal film or refractory metal silicidation film along a sidewall of a charge storage gate electrode and a gate width direction. A field effect transistor in which a control gate electrode in which films are stacked is formed, and a source region and a drain region are formed on both sides of the charge storage gate electrode and the control gate electrode in the gate length direction is used as a storage element. In a method for forming a semiconductor integrated circuit device including an ultraviolet erasable or electrically erasable non-volatile memory circuit,
The following steps (A) to (D) are provided. (A) A charge storage gate electrode and a control gate electrode of a field effect transistor which is a memory element of the nonvolatile memory circuit are formed on a substrate, and a refractory metal film or refractory metal silicide film of the control gate electrode is formed on the substrate. A step of depositing an oxidation resistant mask on the surface, (B) using the mask formed in the step (A) as an oxidation resistant mask, performing an oxidation treatment, and performing a oxidation treatment on each of the source region and the drain region on the substrate. Forming an oxide film for impurity transmission in the formation region, (C) using the mask formed in the process (A), and forming the source region and the drain region of the substrate in each formation region, the step (B) The step of introducing a predetermined conductivity type impurity by ion implantation through the impurity transmitting oxide film formed in step (D), heat treatment is performed, and the predetermined conductivity type impurity introduced in the step (B) is attracted. Subjected to enlargement diffusion, forming a respective source region, a drain region. 2. The step of depositing an oxidation resistant mask of step (A) according to claim 1, wherein the refractory metal film or the refractory metal silicide film of the control gate electrode has an upper surface,
This is a step of depositing an oxidation resistant mask on the sidewalls and on the formation regions of the source region and the drain region on the substrate. 3. The heat treatment for forming each of the source region and the drain region in the step (D) according to claim 1 or 2 is performed in an atmosphere containing a trace amount of oxygen. 4. The field effect transistor according to claim 3 is formed as a memory element of a non-volatile memory circuit adopting a batch erasing method, and the field effect transistor of the memory element is formed before or after the step (D). After that, heat treatment is performed in an atmosphere containing a small amount of oxygen to increase the amount of diffusion of the source region into the channel formation region as compared with the drain region, so that a tunnel region is formed.