JP4244902B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to an electrically writable nonvolatile semiconductor memory device and a manufacturing method thereof, and is suitable for application to, for example, an EPROM.

  A nonvolatile memory composed of a two-layer gate such as an EPROM is formed on a semiconductor substrate together with a capacitor and other transistors.

  A manufacturing process of a conventional EPROM is shown in FIGS. 10 to 15, and the manufacturing process of the EPROM will be described based on these drawings. This figure shows the case where the EPROM is formed on the same substrate as the capacitor and the MOS transistor.

  First, as shown in FIG. 10A, after p-type impurities and n-type impurities are implanted and diffused in a p-type Si substrate 51 to form a P well 51a and an N well 51b, a selective oxidation method is used. A field oxide film 52 is formed.

  Then, as shown in FIG. 10B, a dummy oxide film 53 is formed on the entire surface of the wafer, and the residual stress layer on the surface of the Si substrate 51 during selective oxidation is removed.

  Subsequently, the dummy oxide film 53 is removed, and an EPROM first gate oxide film 54 is formed as shown in FIG. Then, for adjusting the Vt of the EPROM, a p-type or n-type impurity is selectively implanted into the surface of the Si substrate 51 in the EPROM region.

  Next, after forming a first polysilicon film 55 as shown in FIG. 11B, the polysilicon film 55 is patterned by photoetching as shown in FIG. The polysilicon film 55 is left on the entire surface, and the capacitor lower electrode 56 is formed.

  Thereafter, as shown in FIG. 12B, a dielectric film 57 is formed so as to cover the surfaces of the polysilicon film 55 and the lower electrode 56 remaining in the EPROM region.

  Then, after removing a portion of the dielectric film 57 formed on the surface of the Si substrate 51, an oxide film is formed on the entire surface of the wafer as shown in FIG. A film 58 is formed.

  Subsequently, an impurity for adjusting the Vt of the n-channel MOS transistor is transmitted through the gate oxide film 58 and selectively injected into the MOS transistor region, and then a second polysilicon film 59 is formed on the entire surface of the wafer. To do.

  Then, as shown in FIG. 13B, the second and first polysilicon films 59 and 55 are simultaneously patterned by photoetching to form an EPROM control gate 60a and a floating gate 60b.

  Subsequently, as shown in FIG. 14A, the second-layer polysilicon film 59 is patterned by photoetching to form the upper electrode 61 of the capacitor and the gate 62 of the MOS transistor.

  Thereafter, a gate protection film 64 is formed on the entire surface of the wafer by thermal oxidation.

  In order to improve the writing speed of the EPROM, the overlap length between the drain and the floating gate 60bc needs to be longer than the overlap length between the gate 62 and the drain of the n-channel MOS transistor. As shown in FIG. 14B, source and drain formation regions 65a are formed only in the EPROM first. In this step, the source and drain impurities are implanted before forming the sidewall film in the LDD structure, or the heat treatment is performed to increase the diffusion length after the impurity implantation for forming the source and drain.

  Subsequently, as shown in FIG. 15 (a), the source and drain 65b of the n-channel MOS transistor are formed by ion implantation, and further impurities are implanted in the EPROM region so as to overlap the source and drain 65a. To.

  Thereafter, as shown in FIG. 15B, after an interlayer insulating film 66 is formed by CVD, a flattening process of the interlayer insulating film 66 is performed, and contact holes for drawing out electrodes are further formed in the interlayer insulating film 66. After forming 66a, the wiring 67 and the protective film 68 for protecting the elements are formed to complete the EPROM.

  Through such a manufacturing process, an EPROM is formed together with a capacitor and an n-channel MOS transistor.

  In this EPROM, a floating gate 60b is formed by the first polysilicon film 55, and a control gate 60a is formed by the second polysilicon film 59. The control gate 60a is formed on the floating gate 60b. It is an arranged configuration.

  Conventionally, the EPROM is formed based on the above-described manufacturing process, but there is a process that is required only for the formation of the EPROM, which increases the manufacturing process.

  Specifically, the first gate oxide film forming step shown in FIG. 11A, the impurity implantation step for Vt adjustment of EPROM performed thereafter, and the first polysilicon film 54 shown in FIG. 11B are formed. A process for removing the floating gate isolation portion of the EPROM, a photoetching process for forming the control gate 60a and the floating gate 60b shown in FIG. 13B, a source and drain forming process shown in FIG. Required only for EPROM formation.

  A single-layer gate type memory cell is known in which the lower electrode of a capacitor is composed of an n-type impurity diffusion layer in a substrate. According to this method, it is possible to form an EPROM without adding a process. However, in this single-layer gate method, the diffusion layer is used as a control gate electrode, so the voltage applied at the time of writing is limited by the avalanche breakdown voltage of the diffusion layer. This is not preferable because the floating gate potential cannot be expected to increase significantly due to the influence of the parasitic capacitance formed between the diffusion layer and the substrate.

  In order to solve the problem of the single-layer gate system, a method of forming a diffusion region to be a control gate using an SOI substrate and insulating it from the surroundings by trench isolation has been proposed in Patent Document 1, This method is not preferable because it requires not only an expensive SOI wafer as a raw wafer but also an additional process for trench isolation.

  Further, in Patent Document 2, it is proposed to adopt an FRAM structure using a ferroelectric between the gates. For forming the FRAM, for forming a ferroelectric film and removing the ferroelectric film. Therefore, it is not preferable because of the processing technique.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile semiconductor memory device capable of reducing the manufacturing process of the nonvolatile semiconductor memory device and reducing the manufacturing process.
JP-A-7-147340 Japanese Patent Laid-Open No. 5-21307

  In order to achieve the above object, the following technical means are adopted.

In the first aspect of the present invention, the control gate (5) is formed on the field insulating film (2), and the floating gate (10) is disposed on the control gate via the insulating film (7). In addition, the control gate extends from the control gate to the gate insulating film (8a), the outer periphery of the control gate is covered with the floating gate, and the floating gate window opened at the inner peripheral position of the control gate. A contact hole is formed in the portion. According to such a configuration, the area sandwiched between the control gate and the floating gate can be increased as compared with the case where the floating gate is arranged at the inner peripheral position of the control gate.

Since the nonvolatile semiconductor memory device having such a configuration can use a process that is necessary only for the formation of the nonvolatile memory as a process for forming other elements, the nonvolatile semiconductor memory device The manufacturing process can be reduced. Specifically, when the nonvolatile memory is formed on the semiconductor substrate together with the capacitor and the MOS transistor, the nonvolatile semiconductor memory device is formed with the configuration described in claim 4 .

The invention according to claim 2 is characterized in that the floating gate is covered with a thermal oxide film having a thickness of 40 nm or more. As described above, by covering the floating gate with the thermal oxide film having a thickness of 40 nm or more, it is possible to prevent the charge retained in the floating gate from being lost and to prevent the charge retention rate from being lowered.

The invention according to claim 3 is characterized in that the floating gate is coated with a laminated film including a thermal oxide film and a non-doped oxide film, and the same effect as in claim 2 can be obtained.

  In addition, the code | symbol in the above-mentioned parenthesis shows the correspondence with the specific means of embodiment description later mentioned.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below.

  FIG. 1A shows a layout of an EPROM according to an embodiment of the present invention, and FIG. 1B shows a cross-sectional view taken along the line XX in FIG. However, in FIG. 1A, only the electrodes, wirings, and the like are shown in the layout, and the electrodes are indicated by diagonal lines.

  Hereinafter, the structure of the EPROM will be described with reference to FIG.

  As shown in FIGS. 1A and 1B, a field oxide film 2 is formed on a Si substrate 1 as a semiconductor substrate. The field oxide film 2 has a partially opened structure, and a first gate film 8a of EPROM is formed on the Si substrate 1 in the opened part.

  On the field oxide film 2, a control gate 5 composed of a first polysilicon film 4 is formed. On the control gate 5, a floating gate 10 composed of a second polysilicon film 9 is formed via a second gate film. The floating gate 10 extends from the control gate 5 to the first gate film 8a.

  Specifically, as shown in FIG. 1A, a capacitor is formed in which a floating gate 10 having an area smaller than that of the control gate 5 is disposed on the control gate 5 having a substantially quadrangular shape. And a region B that constitutes an NMOS transistor in which a part of the floating gate 10 is extended to the outside of the control gate 5 and reaches the first gate film 8a.

  Sources and drains 15 are disposed on both sides of the floating gate 10 located on the first gate film 8a. The source and drain 15 are not shown in FIG. 1B, but are arranged on the front side and the other side in FIG. 1B, respectively.

  Further, as shown in FIG. 1B, a gate insulating film 7 is formed on the control gate 5, and an interlayer insulating film 16 is further formed on the gate insulating film 7. A contact hole 16a communicating with the control gate 5 is formed in the interlayer insulating film 16, and the electric wiring 17 is electrically connected to the control gate 5 through the contact hole 16a. Yes.

  As described above, in the EPROM according to the present embodiment, the control gate 5 is constituted by the first polysilicon film 4 and the floating gate 10 is constituted by the second polysilicon film 9. The floating gate 10 is arranged.

  The writing and reading operations of this EPROM can be performed in the same manner as the two-layer gate method using general hot channel electron injection.

  An actual usage pattern of this EPROM is shown in FIG. FIG. 2 shows a trimming circuit for resistance value correction performed after manufacturing the device, and EPROMs are used as the switching memories PROMTr1 to Trn.

  A plurality (n in this figure) of resistors R are connected in series on the input side of the circuit whose resistance value is corrected by the trimming circuit, and one end of the EPROM is connected to each resistor R connection site. ing. The other end side of the EPROM is connected to the output side of the circuit to be corrected.

  In such a trimming circuit, when a desired resistance value for correcting the resistance value of the circuit is set, by turning on PROMTr at a position corresponding to the resistance value and turning off PROMTr at other positions, The resistance value is variable from R to nR [Ω], and the resistance value of the circuit is corrected. For example, if the resistance value (n−1) × R [Ω] is necessary, if the n−1th PROMTr is set to data “1” and the other is set to data “0”, the resistance value of the trimming circuit is ( n-1) × R [Ω].

  In this way, by finely adjusting the analog characteristic value after the completion of the semiconductor device manufacturing, it is possible to correct to the optimal analog value after confirming the variation factor that occurs during the manufacturing process.

  The manufacturing process of the EPROM configured as described above is shown in FIGS. 3 and 4, and the manufacturing process of the EPROM will be described based on these drawings. However, here, description will be made together with the manufacturing process of the capacitor formed on the silicon substrate together with the EPROM and the one-layer gate MOS transistor. In the following drawings, the EPROM region in which the EPROM is formed, and the capacitor region in which the capacitor is formed And a MOS transistor region in which a MOS transistor is formed.

[Step shown in FIG. 3 (a)]
First, the P well 1a and the N well 1b are formed on the Si substrate 1. Then, a field oxide film 2 is formed by a LOCOS oxidation method, and elements formed in each region are separated.

[Step shown in FIG. 3B]
Next, after forming the dummy oxide film 3 on the silicon substrate, the first polysilicon film 4 is grown on the entire surface of the wafer.

[Step shown in FIG. 3 (c)]
After the dummy oxide film 3 is removed, a photoresist (not shown) having a predetermined region opened is disposed on the polysilicon film 4. Then, the polysilicon film 4 is patterned using the photoresist as a mask. As a result, the control gate 5 is formed in the EPROM region, and the lower electrode 6a is left in the capacitor region.

  Thereafter, the control gate 5 and the lower electrode 6a are oxidized to form a gate insulating film 7 on these surfaces.

  A first gate film 8a is formed on the Si substrate 1 in the EPROM region by thermal oxidation, and a gate oxide film 8b is formed on the Si substrate 1 in the MOS transistor region.

  Note that the thermal oxidation step for forming the gate insulating film 7 shown in the step of FIG. 3C can be combined with the thermal oxidation step for forming the gate oxide film and the first gate film 8a. . By combining the use in this way, the manufacturing process can be simplified.

[Step shown in FIG. 4 (a)]
Thereafter, a second polysilicon film 9 is formed on the entire wafer surface including the gate oxide film 8b and the first gate film 8a.

[Step shown in FIG. 4B]
Next, the polysilicon film 9 is patterned by photoetching to form a floating gate 10 in the EPROM region, an upper electrode 11 in the capacitor region, a gate 12 in the MOS transistor region, and between the capacitor region and the EPROM region. A resistor 13 is formed.

  At this time, although not shown, the floating gate 10 and the gate 12 have the same width in the direction perpendicular to the drawing sheet. By doing in this way, coupling ratio can be controlled by the area and film thickness of the part which overlaps with the control gate 5 among the floating gates 10. FIG.

  Thereafter, thermal oxidation is performed to form a protective oxide film 14 on the surfaces of the floating gate 10, the upper electrode 11, the gate 12, and the polysilicon resistor 13. The thickness of the oxide film 14 needs to be optimized from the viewpoint of charge retention of the EPROM and the hot carrier lifetime of the n-MOS transistor. Therefore, when the relationship between the thickness of the protective oxide film 14 of the floating gate 10 and the charge loss defect rate was examined, the result shown in FIG. 5 was obtained. As shown in this figure, it is preferable that the thickness of the protective oxide film 14 is about 40 nm or more in order to make the charge loss defect rate substantially zero.

  Note that a non-doped oxide film between a thermal oxide film and a doped film such as BPSG or PSG to be formed later as the interlayer insulating film 16 may be deposited and interposed.

[Step shown in FIG. 4 (c)]
Subsequently, after an interlayer insulating film 16 is formed on the entire surface of the wafer by CVD, a process for planarizing the interlayer insulating film 16 is performed. Then, contact holes 16a, 16b, and 16c are formed in the interlayer insulating film 16 by photoetching, and then the electric wiring 17 is patterned. Thereby, the electric wirings 17a, 17b, and 17c are electrically connected to the floating gate 10, the upper electrode 11, and the like through the contact holes 16a, 16b, and 16c. In the case of a multilayer wiring structure in which a plurality of wiring layers are formed, an interlayer insulating film formation, a wiring layer patterning process, and the like are further performed.

  Thereafter, the entire surface of the wafer is covered with a protective film 18 to complete the nonvolatile semiconductor memory device including the EPROM.

  Thus, in the present embodiment, the control gate 5 is constituted by the first polysilicon film 4 and the floating gate 10 is constituted by the second polysilicon film 9, and therefore the following effects can be obtained.

  First, since the control gate 5 is formed of the first-layer polysilicon film 4, the patterning of the control gate 5 can be combined with the patterning of the lower electrode of the capacitor.

  Further, it is not necessary to perform photoetching for separating the floating gate 10 after forming the first polysilicon film 4.

  Further, as shown in FIG. 4A, the first gate electrode forming step can be used as the gate oxide film forming step in the MOS transistor region, the impurity implantation step for adjusting the Vt of the MOS transistor, and the EPROM The impurity implantation process for adjusting Vt can also be used.

  Further, it is not necessary to increase the overlap length between the control gate 5 and the source / drain 15 (see FIG. 1) in the EPROM with respect to the overlap length between the gate, the source and the drain of the MOS transistor. The drain formation step can be used as the source and drain formation step of the MOS transistor.

  As described above, a plurality of processes required only for forming the EPROM can be used in common with processes for forming other elements, so that the number of manufacturing processes can be reduced.

  As a reference, an example of the EPROM characteristic in this embodiment is shown.

  FIG. 6 shows an example of write characteristics at a control gate voltage of 12 V and a drain voltage of 8 V, and shows the relationship between the write time [Sec] and the Vt shift amount [V] (Vt after write−initial Vt). In addition to an example of EPROM data in this embodiment, as a comparison target, data of a conventional two-layer gate system and a single-layer gate system in which the sizes of active transistors are made uniform are shown in the drawing.

  As shown in this figure, it can be seen that the EPROM in this embodiment has a performance comparable to that of an existing EPROM, and is significantly superior in writing as compared with a single-layer gate type.

  FIG. 7 shows the charge retention life, which is an important characteristic for a nonvolatile raw memory. The data in this figure is an estimated value at 10% charge loss.

  As shown in this figure, it is recognized that the EPROM shown in the present embodiment has a slightly different life from the existing EPROM having a two-layer gate structure, but is required as a general nonvolatile memory. The specifications (85 ° C, 10 years) are fully met.

  As described above, the EPROM according to the present embodiment can achieve characteristics comparable to those of the conventional two-layer gate type EPROM in both writing and charge retention life.

  A memory capable of electrical writing using a tunnel current is proposed in Japanese Patent Publication No. 62-500625 as a memory having a structure substantially similar to that of the present embodiment. It is essential to reduce the thickness of the dielectric film, and the charge retention characteristics can be degraded. For this reason, it can be said that the EPROM in this embodiment is superior to a memory using a tunnel current in terms of charge retention characteristics.

(Second Embodiment)
In this embodiment, the layout of the control gate 5 and the floating gate 10 is changed with respect to the first embodiment, and the other structures and manufacturing processes are the same as those in the first embodiment. Only the layout of the floating gate 10 will be described.

  FIG. 8A shows a layout of the control gate 5 and the floating gate 10 in the present embodiment, and FIG. 8B shows a cross-sectional view taken along line YY of FIG. 8A.

  As shown in FIG. 8A, in the region A, the area of the floating gate 10 is larger than the area of the control gate 5, and the periphery of the control gate 5 is covered with the floating gate 10. Yes. As shown in FIG. 8B, the floating gate 10 is opened on the inner periphery of the control gate 5, and the control gate 5 is electrically connected to the electric wiring 17a with the opened region as a window. Connected.

  According to such a configuration, the area where the floating gate 10 and the control gate 5 overlap, that is, the capacitance between the floating gate 10 and the control gate 5 is kept equal to that of the first embodiment, and The area required for the cell can be reduced as compared with the configuration.

  Further, in such a configuration, it is not necessary to etch the second-layer polysilicon film 9 on the end portion of the control gate 5, so that an etching residue of the polysilicon film 9 is generated on the side surface of the control gate 5. The problem can be eliminated.

(Third embodiment)
In the present embodiment, a case where a salicide structure is employed for a MOS transistor or the like will be described.

  The salicide structure is used to reduce the contact resistance between the electrode or diffusion layer of the MOS transistor and the electric wiring.

  For example, when a process for forming a salicide structure is introduced during the manufacturing process of the first embodiment, the salicide process is performed after the formation of the protective oxide film 14 shown in FIG. Specifically, after forming the protective oxide film 14, the portion of the protective oxide film 14 disposed on the electrodes 10, 11, 12 is removed, and a Ti film or the like is further deposited on the entire surface of the wafer. It is considered that a process of siliciding the Ti film by heat treatment is performed.

  However, since the protective oxide film 14 on the floating gate 10 is removed, a silicide film is formed up to the surface of the floating gate 10. When the floating gate 10 has a salicide structure as described above, charges are released from the floating gate 10 that holds charges, and the charge retention rate of the EPROM is lowered.

  For this reason, in this embodiment, the salicide structure is adopted by the following manufacturing process. The manufacturing process of this salicide structure is shown in FIG. 9, and will be described based on this drawing. In addition, about the process similar to 1st Embodiment, description is abbreviate | omitted with reference to FIG.3 and FIG.4.

  First, similarly to the first embodiment, the process shown in FIG. 4B is performed, and the protective oxide film 14 is formed on the surfaces of the electrodes 10, 11, 12. Then, the following steps are performed.

[Step shown in FIG. 9A]
The portion of the protective oxide film 14 disposed on the upper electrode 11 in the capacitor region and the gate 12 in the MOS transistor region is removed by photoetching. At this time, the protective oxide film 14 located on the floating gate 10 is not removed.

  As a result, the upper electrode 11 and the gate 12 are exposed.

[Step shown in FIG. 9B]
Next, a Ti film 30 is formed on the entire surface of the wafer. Thereby, the upper electrode 11 and the gate 12 are in contact with the Ti film 30. At this time, since the floating gate 10 is covered with the protective oxide film 14, the floating gate 10 is not in contact with the Ti film 30.

[Step shown in FIG. 9C]
When heat treatment is performed, the Ti film 30 in contact with each electrode undergoes a silicidation reaction, and a silicide film 31 is formed on the surfaces of the upper electrode 11 and the gate 12. At this time, since the floating gate 10 is not in contact with the Ti film 30, the silicide film 31 is not formed on the surface of the floating gate 10.

  Thereafter, the unreacted portion of the Ti film 30 is removed to complete the salicide structure.

  Thereafter, similarly to the first embodiment, the process shown in FIG. 4C is performed to complete the nonvolatile semiconductor memory device including the EPROM.

  In this way, by preventing the silicide film 31 from being formed on the surface of the floating gate 10, it is possible to prevent a decrease in the charge retention rate of the EPROM.

It is EPROM to which one embodiment of the present invention is applied, (a) is a diagram showing a layout of EPROM, (b) is a cross-sectional view taken along the line XX of (a). It is a figure which shows the specific usage example of EPROM shown in FIG. It is a figure which shows the manufacturing process of EPROM shown in FIG. It is a figure which shows the manufacturing process of EPROM following FIG. It is a figure which shows the relationship between a protective oxide film and a charge omission defect rate. It is a figure which shows the write-in characteristic of EPROM in this embodiment. It is a figure which shows the electric charge retention lifetime of EPROM in this embodiment. It is EPROM in 2nd Embodiment, (a) is a figure which shows the layout of EPROM, (b) is YY arrow sectional drawing of (a). It is a figure which shows the manufacturing process of EPROM which employ | adopted the salicide structure in 3rd Embodiment. It is a figure for demonstrating the manufacturing process of the conventional EPROM. It is a figure which shows the manufacturing process of EPROM following FIG. FIG. 12 is a diagram showing an EPROM manufacturing process following FIG. 11; FIG. 13 is a diagram showing an EPROM manufacturing process following FIG. 12. It is a figure which shows the manufacturing process of EPROM following FIG. It is a figure which shows the manufacturing process of EPROM following FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Si substrate 1a P well 1b N well 2 Field oxide film 4 First layer polysilicon film 5 Control gate 6 Lower electrode 7 Gate protective film 8a First gate film 8b Gate oxide film 9 Second layer polysilicon film 10 Floating gate 11 Upper electrode 12 Gate 13 Polysilicon resistor 14 Protective oxide film 16 Interlayer insulating film 16a to 16c Contact hole 17a to 17c Electrical wiring 18 Protective film 30 Ti film

Claims (4)

A semiconductor substrate (1), a field oxide film (2) formed on the semiconductor substrate and having an opening in a predetermined region, and the semiconductor substrate exposed from the opening of the field oxide film The formed gate insulating film (8a), the control gate (5) formed on the field oxide film , the insulating film (7) formed on the control gate, and the insulating film through the insulating film A floating gate (10) disposed on the control gate and extending from the control gate to the gate insulating film, and an outer periphery of the control gate are covered with the floating gate, An interlayer insulating film (16) formed to cover the floating gate and the control gate, and formed on the interlayer insulating film Is a contact hole (16a) which communicates with the control gate, the contact hole is formed in the inner circumference the floating gate of the window portion which is opened to the position of the control gate, through the contact hole, wherein A non-volatile semiconductor memory device comprising an electrical wiring (17a) electrically connected to a control gate. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate is covered with a thermal oxide film having a thickness of 40 nm or more. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the floating gate is coated with a laminated film including a thermal oxide film and a non-doped oxide film. A two-layered nonvolatile memory having a floating gate (10) and a control gate (5) on a semiconductor substrate (1), and a two-layered capacitor having an upper electrode (11) and a lower electrode (6) In the non-volatile semiconductor memory device formed with the above, the memory region in which the non-volatile memory is formed and the capacitor region are separated by a field oxide film (2) formed on the semiconductor substrate, The memory region includes an opening formed in the field oxide film, a gate insulating film (8a) formed on the semiconductor substrate, and the control region formed on the field oxide film in the memory region. (5), an insulating film (7) formed on the control gate, and the controller through the insulating film. And a floating gate (10) extending from the control gate to the gate insulating film. The outer periphery of the control gate is the floating gate. The capacitor region is provided with the lower electrode formed on the field oxide film and the upper electrode formed on the lower electrode, the control gate and the lower electrode Nonvolatile, characterized in that the electrode is formed of the same first electrode layer (4), and the floating gate and the upper electrode are formed of the same second electrode layer (9). Semiconductor memory device.

Images