JPH05216953A - Logic simulation method and logic simulator - Google Patents

Abstract

PURPOSE:To shorten signal value tracing processing time in logic simulation and to shorten the logic designing period of a semiconductor logic integrated circuit, as to a logic simulation method and a logic simulator. CONSTITUTION:A trace element connection part 7 connects a trace element to the output terminal of a certain logic element desired to be traced in logic circuit data. An event assignment part 10 assigns each event to each logic element or each trace element. A logic circuit element part 11 calculates the signal change of the output terminal of each logic element based on the event assigned to each logic element and registers the calculated respective signal change as a new event. When the event is assigned to an arbitrary trace element and the event is different from a signal value retained for the trace element, a trace element part 12 outputs the event as trace information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method and a logic simulator for verifying whether or not a semiconductor logic integrated circuit is correctly designed when designing the semiconductor logic integrated circuit.

With the recent increase in the scale of semiconductor logic integrated circuits, logic design work is verified and logic simulation is performed in order to know the state of signals inside the circuit. Recently, as the number of internal logic elements has increased due to the increase in the scale of semiconductor logic integrated circuits, the number of logic elements whose signal values should be traced, or the state inside the circuit which should be traced, has increased. The time required for is increasing.

Therefore, it is necessary to shorten the logic simulation time by speeding up the trace processing.

[0004]

2. Description of the Related Art In a conventional event-driven logic simulator, in order to trace the signal value of the output terminal of an internal logic element which constitutes a semiconductor logic integrated circuit, the trace data shown in FIG. The table 71 is created, and the current time signal value data table 72 shown in FIG. 9 is created. In the current time signal value data table 72, all the nets that connect the respective logic elements of the logic circuit data are registered with the addresses as net numbers (for example, N1, N2, ...), and stored in the storage area corresponding to each net. Stores the signal value data at the internal time at that time. By designating all the logic elements whose signal values should be traced, the trace data table 71 stores the net numbers of the nets of the output terminals of those logic elements and the latest trace signal value data of the nets. ..

FIG. 5 shows a process at one time of a conventional event-driven logic simulator. First, in step 40, the event process shown in FIG. 7 is executed, and in step 41
Strobe processing is performed to compare the expected value with the simulation result. In the next step 42, after the trace processing for notifying the outside of the apparatus of the detection of the signal change shown in FIG. 7, the internal time is updated in step 43 to the time obtained by adding a certain time to the internal time at that time. When the updated internal time is not the end time, the processing of steps 40 to 43 is repeatedly executed.

In the event processing, as shown in FIG. 6, in step 50, it is judged whether or not there is a signal change of the input signal, that is, the external signal data. If there is an input signal, the input signal is treated as an event in step 51. While registering, "1" is added to the count value of the event counter in step 52.

In step 53, it is determined whether or not there is an event to be processed at the present time, that is, there is a change in the input signal or the internal signal of the LSI. Then, when it is determined that there is an event to be processed in step 53, "1" is subtracted from the count value of the event counter in step 54, and the signal change calculation by the event is performed in step 55 to generate after the current time. The change in the internal signal of the LSI is calculated. In step 56, it is determined whether the signal value has changed, that is, whether an event has occurred. If it is determined that an event has occurred, the event that occurred is registered in step 57, and the event occurs in step 58. "1" is added to the count value of the counter. Steps 53 to 58 are repeatedly executed by the number of events to be processed at the current time.

In the trace processing, as shown in FIG. 7, first, in step 60, the initial value of the trace counter is set to "0", and in the next step 61, the number of data in the trace data table 71 shown in FIG. Enter "n".

Next, in step 62, "1" is added to the trace counter value, and in step 63, the trace counter value and the number of data "n" are compared. If it is determined that the trace counter value is less than or equal to the data number "n", step 64
Proceed to. In step 64, the first net number and the past output signal value (latest trace signal value data) in the trace data table 71 indicated by the trace counter value are searched, and the current time signal value data table 72 is searched for the current net number. The signal value is searched and it is determined whether or not the past output signal value and the current signal value match.

When it is determined in step 64 that the past output signal value and the present signal value do not match, the process proceeds to step 65, and the present signal value is substituted into the past signal value area corresponding to the net number in the trace data table 71. Then, in the following step 66, the first contents of the trace data table 71, that is, the net number and the past output signal value are output, and the process returns to step 62. If it is determined in step 64 that the past output signal value and the current signal value match, the process returns to step 62.

In step 62, "1" is added to the trace counter value, and the processes in steps 62 to 66 are repeatedly executed until the trace counter value becomes "n", and past output is performed for each net in the trace data table 71. The net number at which the signal value and the current signal value do not match and the past output signal value after rewriting are output.

If it is determined in step 63 that the trace counter value is larger than the number of data "n", step 6
Then, the processing is terminated.

[0013]

However, in the above conventional trace processing, for each net designated in the trace data table 71, the current signal value is searched from the current time signal value data table 72, and the past output of the net is performed. It takes a great deal of effort to compare the signal value with the retrieved current signal value and to output the signal only when they do not match. The trace processing time for this may reach 50% to 70% of the total simulation time,
This trace processing has a problem that the processing speed of the logic simulation is reduced.

The present invention has been made to solve the above problems, and it is an object of the present invention to shorten the signal value trace processing time in a logic simulation and shorten the logic design period of a semiconductor logic integrated circuit.

[0015]

In order to achieve the above object, a first invention is to provide logic circuit data of an LSI composed of a plurality of logic element data, net data, etc. and input to this LSI to check its operation. Input the external signal data, and assign the signal change of the external signal data or the signal change of the output terminal of each logic element at the internal time at that time to the input terminal of each corresponding logic element as an event, and the internal time at that time Based on each event in, the signal change of each logic element that occurs after the internal time is calculated, and the calculated signal change of the output terminal is registered as a new event after a predetermined time from the internal time at that time. , A logic simulator that traces a signal change at the output terminal of a predetermined logic element and then sequentially updates the internal time at that time. In Deployment method, it sets the trace elements to the output terminal for a predetermined logic element to be traced in the logic circuit data,
An event is assigned to each trace element in the same way as each logic element, and when the event assigned to an arbitrary trace element differs from the signal value held in that trace element, that event is assigned to that trace element. The trace information of the logic element to be output is output.

A second aspect of the present invention is a logic circuit data storage unit for storing logic circuit data of an LSI consisting of a plurality of logic element data, net data, etc., and external signal data for inputting to this LSI to check its operation. An external signal data storage unit that stores the internal time, an internal time management unit that manages the internal time in the logic simulation, and an external signal input that inputs a signal change of the external signal data at the internal time managed by the internal time management unit. A circuit section, a trace element connecting section for connecting a trace element to an output terminal of a predetermined logic element to be traced in the logic circuit data based on external trace element setting data, the logic circuit data and the trace element connecting section Input the trace element data connected by the The external signal data of is input and the signal change of the external signal data at the internal time at that time managed by the internal time management unit or the signal change of the output terminal of each logic element is used as an event, and Based on the event, the signal change of the output terminal of each logic element that occurs after that internal time is calculated, and the calculated signal change of each output terminal is calculated by the predetermined signal propagation delay value from the internal time at that time. An event processing circuit unit for registering as a new event, and a signal change output circuit unit for outputting the processing result of the event processing circuit unit are provided, and the event processing circuit unit is provided with each logic element or each trace corresponding to each event. When an event is assigned to each logic element by the event assigner that assigns to the input terminal of the element and the event assigner, The signal change of the output terminal of each logic element that occurs after that internal time is calculated based on the input signal, and the calculated signal change of each output terminal is calculated from the internal signal at that time by a predetermined signal propagation delay value. When an event is assigned to a trace element by the logic circuit element section to be registered as a new event and the event assignment section, and that event is different from the signal value held in the trace element, the event is traced. And a trace element section for outputting as trace information of a logic element corresponding to the element.

[0017]

According to the first and second inventions, a trace element is connected to the output terminal of a predetermined logic element to be traced in logic circuit data, an event is assigned to each trace element, and the event is assigned to the trace element. When the signal value is different from the held signal value, the event is output as the trace information of the logic element corresponding to the trace element. Therefore, it becomes possible to trace the signal value of a large number of logic elements while reducing the signal value trace processing time, the logic simulation time is shortened, and the logic design period of the semiconductor logic integrated circuit is shortened.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. For convenience of explanation, FIGS.
The same reference numerals are given to the same configurations as those and the description thereof is partially omitted.

As shown in FIG. 1, the logic simulator 1
Is a logic circuit data file 2 as a logic circuit data storage unit, an external signal data file 3 as an external signal data storage unit, an internal time management unit 4, an external signal input circuit unit 5, an event processing circuit unit 6, a trace element connection. And a signal change output circuit section 8 and the like, so as to execute a logic simulation of an LSI based on the logic circuit data of the logic circuit data file 2 and the external signal data of the external signal data file 3. It has become.

The logic circuit data file 2 stores LSI logic circuit data composed of a plurality of logic element data and net data. FIG. 4 shows an example of logic circuit data 20, which includes logic elements 21 to 24 and nets N1 to N.
It is composed of 6 etc. The external signal data file 3 stores external signal data, strobe signal data, and the like, which are input to the LSI and used to check the operation thereof.

The internal time management unit 4 is an internal time at that time in the logic simulation (hereinafter, referred to as current time).
The current time is output to the external signal input circuit unit 5, the event processing circuit unit 6, and the signal change output circuit unit 8. When the internal time management unit 4 finishes the event processing by the event processing circuit unit 6 and the signal output processing by the signal change output circuit unit 8 at the internal time at that time, a time obtained by adding the current time to the current time at that time by a fixed time. It is supposed to be updated.

The external signal input circuit section 5 inputs the signal change of the external signal data corresponding to the current time, that is, the rising or falling edge, based on the current time managed by the internal time management section 4. Event processing circuit unit 6
Output to.

The trace element connection unit 7 connects the trace element to the output terminal of a predetermined logic element to be traced in the logic circuit data based on the trace element setting data input from the outside using a keyboard or the like. Is becoming That is, when the logic element 24 is designated as the logic element to be traced in the logic circuit data 20 shown in FIG. 4, the net N of the output terminal of the logic element 24 is designated.
The trace element 25 is connected to 5.

The event processing circuit section 6 is the event allocation section 1
0, a logic circuit element section 11, a trace element section 12 and the like. The event processing circuit section 6 inputs the logic circuit data and the trace element data connected by the trace element connecting section 7, and also inputs the external signal data from the external signal input circuit section 5. Then, the event processing circuit unit 6 uses the signal change of the external signal data or the signal change of the output terminal of each logic element at the internal time at that time managed by the internal time management unit 4 as an event, and at the internal time at that time. Based on each event, the signal change of the output terminal of each logic element that occurs after that internal time is calculated, and the calculated signal change of each output terminal is delayed by a predetermined signal propagation delay value from the internal time at that time. It will be registered as a new event of.

That is, the event allocating section 10 regards the signal change of the external signal data or the signal change of the output terminal of each logic element at the internal time when managed by the internal time management section 4 as an event, and corresponds each event. Assign to the input terminal of logic element or each trace element.

The logic circuit element section 11 is the event allocation section 10
Based on each event assigned to each logic element, calculate the signal change of the output terminal of each logic element that occurs after that internal time, and calculate the calculated signal change of each output terminal from the internal time at that time. Register as a new event after a predetermined signal propagation delay value.

The trace element section 12 is the event allocation section 10.
When an event is assigned to an arbitrary trace element by, when the event is different from the signal value held in the trace element, the event is output as the trace information of the logic element corresponding to the trace element.

When the event processing circuit unit 6 finishes processing all the events to be processed at the current time stored in the internal time management unit 4, the signal change output circuit unit 8 outputs the processing result by the event processing circuit unit 6. And the expected value are compared with the strobe processing, and the trace processing is executed and the trace list 9 is output.

Next, the one-time processing executed by the logic simulator 1 configured as described above will be described with reference to FIG. 2. The event processing circuit section 6 executes the event processing in step 30, and during the event processing. At, the trace processing is executed by the trace element unit 12. Then, the signal change output circuit section 8 executes the strobe processing in step 41, and thereafter, in step 43, the internal time management section 4 updates the internal time to a time obtained by adding a fixed time.

FIG. 3 shows the event processing of the event processing circuit section 6. First, in step 50, the input signal,
That is, it is determined whether or not there is a signal change in the external signal data, and when there is an input signal, the input signal is registered as an event in step 51, and "1" is added to the count value of the event counter in step 52. .. Steps 50 to 52 are repeatedly executed by the number of input signals.

Then, in step 53, it is determined whether or not there is an event to be processed at the current time, that is, there is a change in the input signal or the internal signal of the LSI. If it is determined in step 53 that there is an event to be processed, step 54
And subtract "1" from the count value of the event counter,
In the next step 31, it is determined whether the event corresponds to a logic element or a trace element.

When it is determined in step 31 that the event corresponds to the logic element, in step 55, the signal change calculation according to the event is performed to calculate the internal signal change of the LSI occurring after the current time. Step 5
In step 6, it is determined whether or not an event has occurred, that is, whether or not there is an internal signal change. If it is determined that an event has occurred, the event that has occurred is registered in step 57 and the count value of the event counter is set to " 1 ”is added.

When it is determined in step 31 that the event corresponds to the trace element, in step 32 the signal value of the event has changed from the signal value held in the trace element, that is, , If it is determined that the signal value has changed, the event is held in the trace element in step 33, and the event is used as trace information of the logic element corresponding to the trace element. It outputs to the signal change output circuit unit 8.

Therefore, for example, an event is assigned to the trace element 25 shown in FIG. 4, the signal value of the assigned event is "1", and the signal value held by the trace element 25 is "0". Sometimes, the signal value “1” is held in the trace element 25, and the signal value “1” is output as the trace information of the logic element 24.

Steps 53, 54, 31, 55-5
8 and steps 32 and 33 are repeatedly executed by the number of events to be processed at the current time. As described above, in this embodiment, the trace element connection unit 7 connects the trace element to the output terminal of the predetermined logic element to be traced in the logic circuit data based on the trace element setting data from the outside. Further, the event processing circuit section 6 is provided with a trace element section 12, and when an event is assigned to an arbitrary trace element by the event assigning section 10 and the event is different from the signal value held in the trace element, the trace element section 12 is provided. By 12, the event is output as the trace information of the logic element corresponding to the trace element.

Therefore, like the trace processing in the conventional logic simulation, the trace data table 7
The signal value trace processing time is reduced by operating the signal change output circuit section 8 only when the logic element to be traced causes a signal change without performing the trace processing on the data of all the logic elements to be traced in 1. At the same time, it becomes possible to trace the signal values of a large number of logic elements, which makes it possible to speed up the logic simulation, thereby shortening the logic design period of the semiconductor logic integrated circuit.

In the present embodiment, the trace element unit 12 determines whether or not the signal value of the event assigned to each trace element has changed from the signal value held in the trace element. The signal change output circuit unit 8 may make this determination.

In the present embodiment, the trace element connecting portion 7 connects the trace element to the output terminal of the predetermined logic element to be traced. However, the trace element is previously connected to the output terminal of the logic element to be traced in the logic circuit data. You may use the logic circuit data which set.

[0039]

As described in detail above, according to the present invention,
There is an excellent effect that the signal value trace processing time in the logic simulation can be shortened and the logic design period of the semiconductor logic integrated circuit can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a logic simulator according to an embodiment.

FIG. 2 is a flowchart showing processing of a logic simulator at one time according to an embodiment.

FIG. 3 is a flowchart showing event processing according to an embodiment.

FIG. 4 is a diagram showing an example of logic circuit data.

FIG. 5 is a flowchart showing processing of a conventional logic simulator at one time.

FIG. 6 is a flowchart showing conventional event processing.

FIG. 7 is a flowchart showing conventional trace processing.

FIG. 8 is a flowchart showing a trace data table.

FIG. 9 is a diagram showing a current time signal value data table.

[Explanation of symbols]

2 Logic circuit data file as logic circuit data storage unit 3 External signal data file as external signal data storage unit 4 Internal time management unit 5 External signal input circuit unit 6 Event processing circuit unit 7 Trace element connection unit 8 Signal change output circuit Part 10 Event allocation part 11 Logic circuit element part 12 Trace element part

Claims (2)

[Claims] 1. An external signal at an internal time at that time, by inputting logic circuit data of an LSI composed of a plurality of logic element data and net data, and external signal data for inputting to this LSI to check its operation. Each logic element that occurs after the internal time based on each event at the internal time at that time is assigned to the input terminal of each corresponding logic element by assigning a data signal change or a signal change at the output terminal of each logic element as an event. After registering the calculated signal change of the output terminal as a new event after a predetermined time from the internal time at that time, and tracing the signal change of the output terminal of the predetermined logic element, In the logic simulation method in which the internal time at that time is sequentially updated, A trace element is set to the output terminal of a predetermined logic element to be connected, an event is assigned to each trace element in the same manner as each logic element, and the event assigned to an arbitrary trace element is the trace element concerned. The logic simulation method is characterized in that, when the signal value is different from the signal value held in, the event is output as trace information of the logic element corresponding to the trace element. 2. A logic circuit data storage section (2) storing logic circuit data of an LSI, which is composed of a plurality of logic element data and net data, and external signal data for inputting to this LSI and checking its operation. The external signal data storage unit (3), the internal time management unit (4) that manages the internal time in the logic simulation, and the signal of the external signal data at the internal time managed by the internal time management unit (4) An external signal input circuit section (5) for inputting a change, and a trace element connection section for connecting a trace element to an output terminal of a predetermined logic element to be traced in the logic circuit data based on external trace element setting data ( 7), and inputting the logic circuit data and the trace element data connected by the trace element connection unit (7) Together,
External signal data from the external signal input circuit section (5) is input, and the signal change of the external signal data or the signal change of the output terminal of each logic element at the internal time at that time managed by the internal time management section (4). Is defined as an event, and the signal change of the output terminal of each logic element that occurs after that internal time is calculated based on each event at the internal time at that time, and the calculated signal change of each output terminal is calculated at that time. An event processing circuit section (6) for registering as a new event after a predetermined signal propagation delay value from the internal time, and a signal change output circuit section (8) for outputting the processing result of the event processing circuit section (6). An event allocating unit (10) for allocating the event processing circuit unit (6) to an input terminal of each corresponding logic element or each trace element, When an event is assigned to each logic element by the vent assignment unit (10), the signal change of the output terminal of each logic element occurring after the internal time is calculated based on the event and the calculated output terminal is calculated. Logic circuit element section (11) for registering the signal change of as a new event after a predetermined signal propagation delay value from the internal time at that time
When an event is assigned to an arbitrary trace element by the event assigning section (10) and the event is different from the signal value held in the trace element, the event is assigned to the logic element corresponding to the trace element. A logic simulator comprising a trace element section (12) for outputting as trace information.