JPH0521661A - Semiconductor chip module - Google Patents

Semiconductor chip module

Info

Publication number
JPH0521661A
JPH0521661A JP17273591A JP17273591A JPH0521661A JP H0521661 A JPH0521661 A JP H0521661A JP 17273591 A JP17273591 A JP 17273591A JP 17273591 A JP17273591 A JP 17273591A JP H0521661 A JPH0521661 A JP H0521661A
Authority
JP
Japan
Prior art keywords
semiconductor chip
heat sink
cap
chip module
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17273591A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP17273591A priority Critical patent/JPH0521661A/en
Priority to CA002072377A priority patent/CA2072377A1/en
Priority to AU18698/92A priority patent/AU651461B2/en
Priority to US07/909,206 priority patent/US5387815A/en
Priority to EP19920111721 priority patent/EP0522563A3/en
Priority to KR1019920012280A priority patent/KR930003335A/en
Publication of JPH0521661A publication Critical patent/JPH0521661A/en
Priority to US08/301,431 priority patent/US5525548A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors

Abstract

PURPOSE:To provide a semiconductor chip module which is small in number of parts and excellent in heat dissipating properties. CONSTITUTION:A board 2 where a wiring section is formed, a semiconductor chip 6 so mounted that its circuit surface faces the wiring section, a heat sink 3 whose one edge comes into contact with the surface of the semiconductor chip 6 opposite to its circuit surface, and a cap 4 which is provided with a hole through which the other edge of the heat sink 3 is exposed outside and envelops the semiconductor chip 6 are provided. An insulating film 9 is formed on a prescribed region of the board 2 located around the semiconductor chip 6, and at least, a metal film is formed both on the inner wall of the hole concerned and on the surface of the heat sink 3 inserted into the cap 4, and bonding agent is filled into the spaces between these metal films and also between the tip of the heat sink 3 and the semiconductor chip 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はコンピュータや通信な
ど、信号処理の高速化が要求される分野に適用できる半
導体チップモジュール(マルチチップモジュール、シン
グルチップモジュール)に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip module (multichip module, single chip module) applicable to a field requiring high speed signal processing such as computers and communications.

【0002】[0002]

【従来の技術】電子機器の機能の大規模・高速化が求め
られるにつれて、論理LSIのゲート当りの遅延時間は
数百psと高速化してきた。それに対して、プリント基板
上に多数のDIPやプラグインパッケージを搭載する従
来の実装形態では高速化したLSIの性能を十分に発揮
させることが困難になってきた。その為に、1枚のセラ
ミック基板上に多くのチップを搭載し、高速性能を有す
る高密度実装したマルチチップモジュール方式が開発さ
れ実用されている(LSIハンドブック、第1版、pp.4
15-416、電子通信学会、1984年)。
2. Description of the Related Art With the demand for large-scale and high-speed functions of electronic devices, the delay time per gate of a logic LSI has been increased to several hundred ps. On the other hand, in the conventional mounting mode in which a large number of DIPs and plug-in packages are mounted on the printed circuit board, it has become difficult to sufficiently exert the performance of the accelerated LSI. For this reason, a multi-chip module system, in which many chips are mounted on one ceramic substrate and which has high-speed performance and high-density mounting, has been developed and put into practical use (LSI Handbook, 1st edition, pp.4).
15-416, IEICE, 1984).

【0003】従来技術としては、ピストンをバネにより
半導体チップに接触させて冷却板に放熱させる構造が知
られている(“Materials/Processing Approaches to P
haseStabilization of Thermally Conductive Pastes
” pp.713-717 、IEEE TRANSACTIONS OF COMPONENTS,H
YBRIDS. AND MANUCFACTURING TECHNOLOGY,VOL.13,NO.4,
DECEMBER1990)。
As a conventional technique, a structure is known in which a piston is brought into contact with a semiconductor chip by a spring to radiate heat to a cooling plate (“Materials / Processing Approaches to P”).
haseStabilization of Thermally Conductive Pastes
Pp.713-717, IEEE TRANSACTIONS OF COMPONENTS, H
YBRIDS. AND MANUCFACTURING TECHNOLOGY, VOL.13, NO.4,
DECEMBER1990).

【0004】[0004]

【発明が解決しようとする課題】しかし、ピストンを用
いた半導体チップモジュールは、部品点数が多く、コス
トが極めて高くなるという欠点があった。
However, the semiconductor chip module using the piston has a drawback that the number of parts is large and the cost is extremely high.

【0005】そこで本発明は、少ない部品点数で、良好
な放熱設計ができる半導体チップモジュールを提供する
ことを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor chip module capable of a good heat dissipation design with a small number of parts.

【0006】[0006]

【課題を解決するための手段】上記課題を達成するため
に、本発明に係る半導体チップモジュールは配線部が形
成された基板と、配線部に回路面を向けて実装された半
導体チップと、半導体チップの回路面と反対側で一端部
が接触したヒートシンクと、ヒートシンクの他端部を外
部に露出させる穴が形設され前記半導体チップを内包し
たキャップとを備えて構成され、基板は半導体チップの
周辺部近傍に位置する所定領域に絶縁膜が形成され、少
なくとも穴の内壁およびキャップの内部に挿入されるヒ
ートシンクの表面に金属膜が形成され、金属膜間に接着
剤が埋め込まれていると共にヒートシンクの先端部と前
記半導体チップの間に接着剤が埋め込まれていることを
特徴とする。
In order to achieve the above object, a semiconductor chip module according to the present invention includes a substrate on which a wiring portion is formed, a semiconductor chip mounted on the wiring portion with its circuit surface facing, and a semiconductor. The semiconductor chip is provided with a heat sink whose one end is in contact with the side opposite to the circuit surface of the chip, and a cap which has a hole for exposing the other end of the heat sink to the outside and encloses the semiconductor chip. An insulating film is formed in a predetermined area near the peripheral part, a metal film is formed on at least the inner wall of the hole and the surface of the heat sink to be inserted inside the cap, and an adhesive is embedded between the metal films and the heat sink is formed. An adhesive is embedded between the tip of the semiconductor chip and the semiconductor chip.

【0007】[0007]

【作用】本発明に係る半導体チップモジュールによる
と、ヒートシンクはキャップ穴の内壁に強固に固着さ
れ、発熱が比較的に大きい半導体チップから発生した熱
は接着剤を介して効率良くヒートシンクの一端部に熱伝
導され、一端部から他端部(低温部)に伝導する。この
熱伝導によって、熱はキャップの外部に導かれ、キャッ
プの外で発散される。また、溢れた接着剤は絶縁膜上に
落ちるので、基板の配線部には接触しない。
According to the semiconductor chip module of the present invention, the heat sink is firmly fixed to the inner wall of the cap hole, and the heat generated from the semiconductor chip, which generates a relatively large amount of heat, efficiently reaches one end of the heat sink through the adhesive. It is thermally conducted and is conducted from one end to the other end (low temperature portion). By this heat conduction, heat is guided to the outside of the cap and radiated outside the cap. Further, the overflowing adhesive drops on the insulating film, and thus does not contact the wiring portion of the substrate.

【0008】[0008]

【実施例】以下、本発明の一実施例について、添付図面
を参照して説明する。なお、説明において同一要素には
同一符号を用い、重複する説明は省略する。図1は本発
明の一実施例としてマルチチップモジュールの外観を示
す斜視図であり、図2は実施例に係るマルチチップモジ
ュールをヒートシンクに沿って切断した縦断面図であ
る。
An embodiment of the present invention will be described below with reference to the accompanying drawings. In the description, the same elements will be denoted by the same reference symbols, without redundant description. FIG. 1 is a perspective view showing an appearance of a multi-chip module as one embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view of the multi-chip module according to the embodiment cut along a heat sink.

【0009】本実施例に係るマルチチップモジュール
は、下部基板1、上部基板2、ヒートシンク3、キャッ
プ4を含んで構成されている。下部基板1はアルミナ材
で形成され、その側面からは上部基板2により構成され
た電気回路と接続した複数のリードピン7が延びてい
る。また、上部基板2は低誘電率絶縁材料で形成され、
例えば、熱抵抗3℃/W、サーマルバイヤを併用した3
インチ角のポリイミド多層配線構造を使用することがで
きる(“銅ポリイミド多層配線基板”、HYBRIDS 、Vol.
7, No.1, pp.10-12 参照)。
The multi-chip module according to this embodiment comprises a lower substrate 1, an upper substrate 2, a heat sink 3 and a cap 4. The lower substrate 1 is made of an alumina material, and a plurality of lead pins 7 connected to the electric circuit constituted by the upper substrate 2 extend from the side surface of the lower substrate 1. The upper substrate 2 is made of a low dielectric constant insulating material,
For example, 3 with thermal resistance of 3 ° C / W and thermal via
Inch-square polyimide multi-layer wiring structure can be used (“Copper-polyimide multi-layer wiring board”, HYBRIDS, Vol.
7, No.1, pp.10-12).

【0010】下部基板1は上部基板1より大きい平板で
構成され、この上面に上部基板2が積み重ねた状態で固
定されている。上部基板2が重なっていない下部基板1
の上面にはキャップ4の縁部が覆い被せられている。し
たがって、キャップ4と下部基板1により、上部基板2
は内包された状態になっている。
The lower substrate 1 is composed of a flat plate larger than the upper substrate 1, and the upper substrate 2 is fixed in a stacked state on the upper surface thereof. Lower substrate 1 where upper substrate 2 does not overlap
The edge of the cap 4 is covered on the upper surface of the. Therefore, with the cap 4 and the lower substrate 1, the upper substrate 2
Is in a contained state.

【0011】上部基板2の表面には電極が露出してお
り、これらの電極と接続する半導体チップ5、6が搭載
されている。半導体チップ5、6は、例えば10mm角
ICチップになっており、ワイヤボンディング法あるい
はフェースダウン実装法(フリップチップ実装法)によ
って、上部基板2の表面に形成された電極と接続してい
る。図1及び図2では、半導体チップ5はワイヤボンデ
ィング法で実装されたICチップを示し、半導体チップ
6はフェースダウン実装法で実装されたICチップを示
す。したがって、半導体チップ5の回路面はキャップ4
に面し、半導体チップ6の回路面は上部基板2に面す
る。上部基板2の上面にはCuからなる配線部8が形成
されており、この配線部8に半導体チップ6がバンプb
を介して実装されている。ここで重要なことは、半導体
チップ6の周辺部の近傍に位置する上部基板2の所定領
域に絶縁膜9が形成されている点である。詳細は後述す
る。
Electrodes are exposed on the surface of the upper substrate 2, and semiconductor chips 5 and 6 connected to these electrodes are mounted. The semiconductor chips 5 and 6 are, for example, 10 mm square IC chips, and are connected to the electrodes formed on the surface of the upper substrate 2 by a wire bonding method or a face-down mounting method (flip chip mounting method). 1 and 2, the semiconductor chip 5 is an IC chip mounted by the wire bonding method, and the semiconductor chip 6 is an IC chip mounted by the face-down mounting method. Therefore, the circuit surface of the semiconductor chip 5 has the cap 4
, The circuit surface of the semiconductor chip 6 faces the upper substrate 2. A wiring portion 8 made of Cu is formed on the upper surface of the upper substrate 2, and the semiconductor chip 6 is bumped on the wiring portion 8 by the bump b.
Has been implemented through. What is important here is that the insulating film 9 is formed in a predetermined region of the upper substrate 2 located near the peripheral portion of the semiconductor chip 6. Details will be described later.

【0012】キャップ4は、例えば厚さ1mmのコバー
ル(kovar )で蓋状に形成されており、比較的に発熱量
の大きい半導体チップ6の搭載位置と対応した位置に、
例えば内径6〜8mm程度の穴4aが形設されている。
この穴4aにヒートシンク3の一端部が挿入される。通
常、穴4aは入口と出口は同一径で形成されるが、出口
と入口の径の大きさを変えてもよい。
The cap 4 is formed, for example, in the shape of a lid of kovar having a thickness of 1 mm, and is provided at a position corresponding to the mounting position of the semiconductor chip 6 which generates a relatively large amount of heat.
For example, a hole 4a having an inner diameter of 6 to 8 mm is formed.
One end of the heat sink 3 is inserted into this hole 4a. Normally, the hole 4a has the same diameter at the inlet and the outlet, but the diameters of the outlet and the inlet may be changed.

【0013】ヒートシンク3は熱伝導率の高い材料(A
l、CuW、AlN、CBN、ダイヤモンドなど)で形
成され、挿入部と放熱部で構成されている。挿入部は上
述した穴4aに挿入しやすい形状になっており、例えば
棒状になっている。また、放熱部はキャップ4の外部に
晒されるので、自然冷却されやすいように表面積が大き
くなる構造になっており、例えば円盤状になっている。
その為、キャップ4の内部への挿入が簡易であり、半導
体チップ6の上面に接触させることが容易であり、か
つ、キャップ4の外部に半導体チップ6からの熱を効率
良く逃がすことができる。ヒートシンク3のキャップ4
に挿入された一端部には表面に金属膜がコーティングさ
れており、その表面および半導体チップ6とヒートシン
ク3の先端部の間にはハンダが付着している(図2参
照)。
The heat sink 3 is made of a material (A
1, CuW, AlN, CBN, diamond, etc.) and is composed of an insertion part and a heat dissipation part. The insertion portion has a shape that facilitates insertion into the hole 4a described above, and has, for example, a rod shape. Further, since the heat radiating portion is exposed to the outside of the cap 4, it has a structure having a large surface area so as to be easily cooled naturally, and has a disk shape, for example.
Therefore, the insertion into the inside of the cap 4 is easy, the upper surface of the semiconductor chip 6 can be easily contacted, and the heat from the semiconductor chip 6 can be efficiently dissipated to the outside of the cap 4. Heat sink 3 cap 4
A metal film is coated on the surface at one end inserted into the substrate, and solder is attached to the surface and between the semiconductor chip 6 and the tip of the heat sink 3 (see FIG. 2).

【0014】次に、図3を参照して、ヒートシンクの取
付け構造例を説明する。図3は、絶縁膜が形成された上
部基板に実装された半導体チップとヒートシンクの取付
け構造を示す。同図(a)はヒートシンクの挿入方向に
沿って切断した縦断面図、同図(b)は同図(a)のA
−A´線で切断した半導体チップの平面図である。絶縁
膜9は半導体チップ6の周辺部に沿って矩形状に配置さ
れている。絶縁膜9の材料は上部基板2が銅ポリイミド
で形成されている場合にはポリイミド材、SiO2 で形
成でき、その膜厚は上部基板2を形成する銅ポリイミド
材の膜厚が薄い場合には3μm程度以上であることが望
ましい。3μm程度以上の膜厚にすることにより、ハン
ダの熱によってピンホールが発生または拡大し配線がシ
ョートすることを防止することができる。
Next, an example of a heat sink mounting structure will be described with reference to FIG. FIG. 3 shows a mounting structure of a semiconductor chip and a heat sink mounted on an upper substrate on which an insulating film is formed. The figure (a) is a longitudinal sectional view cut along the insertion direction of the heat sink, and the figure (b) is the section A of the figure (a).
FIG. 6 is a plan view of the semiconductor chip taken along the line A ′. The insulating film 9 is arranged in a rectangular shape along the peripheral portion of the semiconductor chip 6. The material of the insulating film 9 can be formed of a polyimide material or SiO 2 when the upper substrate 2 is formed of copper polyimide, and its film thickness can be formed when the thickness of the copper polyimide material forming the upper substrate 2 is small. It is desirable that the thickness is about 3 μm or more. By setting the film thickness to about 3 μm or more, it is possible to prevent the occurrence of pinholes or enlargement due to the heat of the solder and the short circuit of the wiring.

【0015】また、キャップの穴4aの内壁にはメタル
mがコーティングされ、この穴4aに挿入されるヒート
シンク3の一端部の表面にもメタルmがコーティングさ
れている。ヒートシンク3およびキャップ4にコーティ
ングされるメタルmは、ハンダsに対して、ぬれ易い
(wettable)性質を有するので、ボイド(気泡)のない
ハンダ接合が可能になり、キャップ4を十分に気密封止
することができる。例えば、Sb/Pb系ハンダを使用
する場合にはAgSn、AgPdなどのメタルを使用す
ると好ましい。
The inner wall of the hole 4a of the cap is coated with metal m, and the surface of one end of the heat sink 3 inserted into this hole 4a is also coated with metal m. Since the metal m coated on the heat sink 3 and the cap 4 has a property of being easily wettable with respect to the solder s, it is possible to perform soldering without voids (air bubbles), and the cap 4 is hermetically sealed. can do. For example, when Sb / Pb-based solder is used, it is preferable to use a metal such as AgSn or AgPd.

【0016】なお、半導体チップ6とヒートシンク3の
先端部の間におけるハンダsの埋め込みは、ヒートシン
ク3と穴4aの内壁の間から液状のハンダsを流し込む
ことにより達成できる。ハンダsの材料としては、B
i、Cd、Inを加えた低温ハンダを使用することがで
きる。この場合、ヒートシンク3を加熱しておき、ハン
ダsを流れ易くしてもよい。
The embedding of the solder s between the semiconductor chip 6 and the tip of the heat sink 3 can be achieved by pouring liquid solder s from between the heat sink 3 and the inner wall of the hole 4a. The material of the solder s is B
A low temperature solder added with i, Cd and In can be used. In this case, the heat sink 3 may be heated to facilitate the flow of the solder s.

【0017】このように、実施例に係るマルチチップモ
ジュールによると、放熱を要する(発熱量が大きい)半
導体チップだけにヒートシンクが装着されているので、
選択的に、効率良く、マルチチップモジュールの放熱が
可能になっている。
As described above, according to the multi-chip module of the embodiment, since the heat sink is mounted only on the semiconductor chip that requires heat dissipation (large heat generation amount),
Selectively and efficiently, it is possible to dissipate heat from the multi-chip module.

【0018】この場合、ヒートシンクは1個の半導体チ
ップに対して1個装着され、ヒートシンクの一端部は挿
入方向に長さの調節ができる構造になっているので、基
板面からの高さが異なる複数の半導体チップが基板に実
装された場合でも、個々の半導体チップにヒートシンク
が確実に装着される。
In this case, one heat sink is attached to one semiconductor chip, and the length of one end of the heat sink is adjustable in the insertion direction, so that the height from the substrate surface is different. Even when a plurality of semiconductor chips are mounted on the substrate, the heat sink is surely attached to each semiconductor chip.

【0019】また、個々の半導体チップに対して個別的
にヒートシンクが装着されるので、フェイスダウン法で
実装された半導体チップ、及びワイヤボンディング法で
実装された半導体チップが混在したマルチチップモジュ
ールに適用することができ、実用性が高い。
Further, since the heat sink is individually attached to each semiconductor chip, it is applied to a multi-chip module in which semiconductor chips mounted by the face-down method and semiconductor chips mounted by the wire bonding method are mixed. It is possible and highly practical.

【0020】次に、本実施例に係るマルチチップモジュ
ールの製造方法を説明する。図3に示す取付け構造を有
するマルチチップモジュールは、半導体チップ5、6が
実装され、絶縁膜9が形成された基板2、予め穴4aの
内壁にメタルmがコーティングされたキャップ4および
予め一端部にメタルmがコーティングされたヒートシン
ク3を準備した後、例えば、 下部基板1に固定され
た上部基板2の上面をキャップ4で内包する工程、
ヒートシンク3の一端をキャップの穴4に挿入し、その
先端を半導体チップ6の上面に接触させる工程、 ヒ
ートシンク3と半導体チップ6が接触した状態で、キャ
ップの穴4aの内壁とヒートシンク3の隙間に大量の液
状ハンダsを注入することにより、半導体チップ6に至
るようにヒートシンク3の一端部にハンダsを付着さ
せ、ヒートシンク3をキャップ4に固定すると共にキャ
ップ4を気密封止する工程を経てパッケージ化される。
Next, a method of manufacturing the multichip module according to this embodiment will be described. The multi-chip module having the mounting structure shown in FIG. 3 includes a substrate 2 on which semiconductor chips 5 and 6 are mounted, an insulating film 9 is formed, a cap 4 in which the inner wall of the hole 4a is previously coated with metal m, and one end portion is previously formed. After preparing the heat sink 3 coated with the metal m, the process of encapsulating the upper surface of the upper substrate 2 fixed to the lower substrate 1 with the cap 4,
A step of inserting one end of the heat sink 3 into the hole 4 of the cap and bringing the tip thereof into contact with the upper surface of the semiconductor chip 6, in a state where the heat sink 3 and the semiconductor chip 6 are in contact with each other, a gap between the inner wall of the hole 4a of the cap and the heat sink 3 By injecting a large amount of liquid solder s, the solder s is attached to one end of the heat sink 3 so as to reach the semiconductor chip 6, the heat sink 3 is fixed to the cap 4, and the cap 4 is hermetically sealed. Be converted.

【0021】この場合、液状のハンダsを注入する際、
ヒートシンク3の一端部はヒートシンク3の自重により
半導体チップ6と自動的に接触した状態になっているの
で、簡単にキャップ4にヒートシンク3を固定すること
ができる。
In this case, when pouring liquid solder s,
Since one end of the heat sink 3 is automatically in contact with the semiconductor chip 6 due to its own weight, the heat sink 3 can be easily fixed to the cap 4.

【0022】また、液状のハンダsはヒートシンク3と
キャップの穴4aの内壁に隙間なく埋め込まれるので、
キャップ4を気密封止することができる。特に、上部基
板2としてポリイミド/Cuなどの薄膜多層基板を用い
る場合、ポリイミド自体に吸湿性があるので、気密封止
が重要になってくる。
Further, since the liquid solder s is embedded in the heat sink 3 and the inner wall of the hole 4a of the cap without a gap,
The cap 4 can be hermetically sealed. Particularly, when a thin film multilayer substrate such as polyimide / Cu is used as the upper substrate 2, since the polyimide itself has a hygroscopic property, hermetic sealing becomes important.

【0023】さらに、ヒートシンク3の先端部もメタル
コーティングされているので、ハンダsの自重によりヒ
ートシンク3の先端部と半導体チップ6の間隙にハンダ
sが埋め込まれ、半導体チップ6とヒートシンク3の間
の接触面積の増大化、熱抵抗の低減化が図れる。
Further, since the tip of the heat sink 3 is also metal-coated, the weight of the solder s fills the gap between the tip of the heat sink 3 and the semiconductor chip 6 with the weight of the solder s. The contact area can be increased and the thermal resistance can be reduced.

【0024】この場合、メタルコーティングをヒートシ
ンク3の先端部に施すことなく、半導体チップ6とヒー
トシンク3の間の接触面積の増大化、熱抵抗の低減化が
図れ、熱放散性に優れたマルチチップモジュールを製造
することができる。
In this case, the contact area between the semiconductor chip 6 and the heat sink 3 can be increased and the thermal resistance can be reduced without applying a metal coating to the tip of the heat sink 3, and a multi-chip excellent in heat dissipation is obtained. The module can be manufactured.

【0025】また、ハンダsを注入する際、過剰な量で
あるために半導体チップ6の上面からこぼれ落ちるハン
ダは、上部基板2の絶縁膜9によって受け止められるの
で、上部基板2の配線部8に流れることにより配線不良
が生じることはない。
Further, when the solder s is injected, the solder spilled from the upper surface of the semiconductor chip 6 due to an excessive amount is received by the insulating film 9 of the upper substrate 2, so that the wiring portion 8 of the upper substrate 2 is covered. Wiring does not cause defective wiring.

【0026】なお、本発明は上記実施例に限定されるも
のではない。本実施例では、ワイヤボンディング法で実
装された半導体チップ及びフェイスダウン法で実装され
た半導体チップを含み、フェイスダウン法で実装された
半導体チップにヒートシンクを装着したマルチチップモ
ジュールを一例として説明したが、単一の半導体チップ
を搭載した半導体チップモジュールに適用することがで
き、また、ヒートシンクが装着されないフリップチップ
を含んでもよい。さらに、キャップの穴の形状は円形に
限らず、ヒートシンクの一端部とほぼ同形であれば方形
でも多角形でもよい。
The present invention is not limited to the above embodiment. In this embodiment, the multi-chip module including the semiconductor chip mounted by the wire bonding method and the semiconductor chip mounted by the face-down method, and the heat sink mounted on the semiconductor chip mounted by the face-down method has been described as an example. The present invention can be applied to a semiconductor chip module mounting a single semiconductor chip, and may include a flip chip to which a heat sink is not mounted. Further, the shape of the hole of the cap is not limited to the circular shape, and may be a square shape or a polygonal shape as long as it is substantially the same as one end of the heat sink.

【0027】[0027]

【発明の効果】本発明は、以上説明したように構成され
ているので、マルチチップモジュール及びシングルチッ
プモジュールにも適用でき、部品点数が少なく、良好な
放熱設計が可能な熱放散性に優れた半導体チップモジュ
ールを提供することができる。
Since the present invention is configured as described above, it can be applied to a multi-chip module and a single-chip module, has a small number of parts, and is excellent in heat dissipation capable of good heat dissipation design. A semiconductor chip module can be provided.

【0028】また、本発明をマルチチップモジュールに
適用したときには、フェイスダウンボンディングの高さ
によるバラツキを許容することができ、信頼性が向上す
る。
Further, when the present invention is applied to a multi-chip module, variations due to the height of face-down bonding can be allowed, and reliability is improved.

【0029】さらに、半導体チップの周辺部近傍の基板
に絶縁膜が形成されているので、多量の接着剤の注入に
よる配線不良を防止できる。
Further, since the insulating film is formed on the substrate in the vicinity of the peripheral portion of the semiconductor chip, wiring failure due to injection of a large amount of adhesive can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係るマルチチップモジュー
ルの外観を示す斜視図である。
FIG. 1 is a perspective view showing an appearance of a multi-chip module according to an embodiment of the present invention.

【図2】本発明の一実施例に係るマルチチップモジュー
ルをヒートシンクに沿って切断した縦断面図である。
FIG. 2 is a vertical cross-sectional view of a multi-chip module according to an embodiment of the present invention cut along a heat sink.

【図3】本発明の一実施例に係るマルチチップモジュー
ルに使用できるヒートシンクの取付け構造例を示す縦断
面図である。
FIG. 3 is a vertical cross-sectional view showing a mounting structure example of a heat sink that can be used in a multi-chip module according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…下部基板、2…上部基板、3…ヒートシンク、4…
キャップ、5、6…半導体チップ、7…リードピン、8
…配線部、9…絶縁膜、b…バンプ、m…メタル、s…
ハンダ。
1 ... Lower substrate, 2 ... Upper substrate, 3 ... Heat sink, 4 ...
Cap, 5, 6 ... Semiconductor chip, 7 ... Lead pin, 8
... Wiring part, 9 ... Insulating film, b ... Bump, m ... Metal, s ...
Solder.

Claims (1)

【特許請求の範囲】 【請求項1】 配線部が形成された基板と、前記配線部
に回路面を向けて実装された半導体チップと、前記半導
体チップの回路面と反対側で一端部が接触したヒートシ
ンクと、前記ヒートシンクの他端部を外部に露出させる
穴が形設され前記半導体チップを内包したキャップとを
備えて構成され、 前記基板は半導体チップの周辺部近傍に位置する所定領
域に絶縁膜が形成され、少なくとも前記穴の内壁および
前記キャップの内部に挿入されるヒートシンクの表面に
金属膜が形成され、前記金属膜間に接着剤が埋め込まれ
ていると共に前記ヒートシンクの先端部と前記半導体チ
ップの間に接着剤が埋め込まれていることを特徴とする
半導体チップモジュール。
Claim: What is claimed is: 1. A substrate on which a wiring portion is formed, a semiconductor chip mounted on the wiring portion with a circuit surface facing, and one end of the semiconductor chip on the side opposite to the circuit surface. And a cap that encloses the semiconductor chip and has a hole that exposes the other end of the heat sink to the outside, and the substrate is insulated in a predetermined region located near the periphery of the semiconductor chip. A film is formed, a metal film is formed on at least the inner wall of the hole and the surface of the heat sink to be inserted inside the cap, and an adhesive is embedded between the metal films, and the tip of the heat sink and the semiconductor are formed. A semiconductor chip module in which an adhesive is embedded between chips.
JP17273591A 1991-07-12 1991-07-12 Semiconductor chip module Pending JPH0521661A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP17273591A JPH0521661A (en) 1991-07-12 1991-07-12 Semiconductor chip module
CA002072377A CA2072377A1 (en) 1991-07-12 1992-06-25 Semiconductor chip module and method of manufacturing the same
AU18698/92A AU651461B2 (en) 1991-07-12 1992-06-30 Semiconductor chip module
US07/909,206 US5387815A (en) 1991-07-12 1992-07-06 Semiconductor chip module
EP19920111721 EP0522563A3 (en) 1991-07-12 1992-07-09 Semiconductor chip module and method of manufacturing the same
KR1019920012280A KR930003335A (en) 1991-07-12 1992-07-10 Semiconductor chip module and manufacturing method
US08/301,431 US5525548A (en) 1991-07-12 1994-09-09 Process of fixing a heat sink to a semiconductor chip and package cap

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17273591A JPH0521661A (en) 1991-07-12 1991-07-12 Semiconductor chip module

Publications (1)

Publication Number Publication Date
JPH0521661A true JPH0521661A (en) 1993-01-29

Family

ID=15947348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17273591A Pending JPH0521661A (en) 1991-07-12 1991-07-12 Semiconductor chip module

Country Status (1)

Country Link
JP (1) JPH0521661A (en)

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