JPH0547967A - Semiconductor chip module - Google Patents

Semiconductor chip module

Info

Publication number
JPH0547967A
JPH0547967A JP3199558A JP19955891A JPH0547967A JP H0547967 A JPH0547967 A JP H0547967A JP 3199558 A JP3199558 A JP 3199558A JP 19955891 A JP19955891 A JP 19955891A JP H0547967 A JPH0547967 A JP H0547967A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chips
heat
heat sink
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3199558A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP3199558A priority Critical patent/JPH0547967A/en
Priority to AU20775/92A priority patent/AU657774B2/en
Priority to CA002075593A priority patent/CA2075593A1/en
Priority to EP19920113478 priority patent/EP0528291A3/en
Publication of JPH0547967A publication Critical patent/JPH0547967A/en
Priority to US08/232,346 priority patent/US5525835A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the heat dissipation property of a semiconductor chip module by a method wherein each one end of heat sinks is brought into contact to the central parts of the upper surfaces of semiconductor chips mounted in such a way that circuit surfaces are faced upward and an insulative thermal compound material is filled in the chips all over the surfaces of the chips in such a way as to come into contact to both of the chips and the heat sinks. CONSTITUTION:Holes 2a are bored at positions, which correspond to the mounting positions of face up type semiconductor chips 4 and face down type semiconductor chips 4a, on a chip 2. Each one end part of heat sinks 3 is inserted in the holes 2a and is brought into contact to the surfaces of the chips 4 and 4a. Moreover, an insulative thermal compound material 1 is filled in the chips 4 almost all over the surfaces of the chips 4 in such a way as to come into contact to both of the chips 4 and the sinks 3. Accordingly, heat which is generated in the center parts of the chips and I/O circuits on the peripheral parts of the chips 4 is transferred to the sinks 3 via the material 1. Thereby, a good heat dissipation design becomes possible and the heat resistance of a semiconductor chip module can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、コンピュータや通信な
どの信号処理の高速化が要求される分野に適用できるマ
ルチチップモジュール、シングルチップモジュールなど
の半導体チップを搭載した半導体チップモジュールに関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip module having a semiconductor chip such as a multi-chip module or a single chip module, which is applicable to a field requiring high speed signal processing such as computer and communication. ..

【0002】[0002]

【従来の技術】電子機器の機能の大規模化および高速化
が求められるにつれ、論理LSIゲート1個当りの遅延
時間は数百psと高速化してきた。それに対して、プリ
ント基板上に多数のDIPやプラグインパッケージを搭
載する従来の実装形態では高速化したLSIの性能を十
分に発揮させることが困難になってきた。そのために、
1枚のセラミック基板上に多くのチップを高密度に搭載
し、高速性能なマルチチップモジュールが開発され実用
されている(LSIハンドブック、第1版、pp.41
5−416、電子通信学会、1984年)。
2. Description of the Related Art With the demand for large-scale and high-speed functions of electronic devices, the delay time per logic LSI gate has been increased to several hundreds ps. On the other hand, in the conventional mounting mode in which a large number of DIPs and plug-in packages are mounted on the printed circuit board, it has become difficult to sufficiently exert the performance of the accelerated LSI. for that reason,
A high-speed multi-chip module has been developed and put into practical use by mounting many chips on one ceramic substrate at high density (LSI Handbook, 1st edition, pp. 41).
5-416, The Institute of Electronics and Communication Engineers, 1984).

【0003】図5に示されるように、このようなマルチ
チップモジュール方式等において、半導体チップをフェ
イスアップで実装した場合には、図5に示すように半導
体チップ4で発生した熱をX方向となる基板10側に逃
していた。半導体チップモジュールは、この放熱動作に
より熱抵抗による性能悪化を防いでいた。
As shown in FIG. 5, when a semiconductor chip is mounted face-up in such a multi-chip module system, heat generated in the semiconductor chip 4 is directed in the X direction as shown in FIG. It was missed to the side of the substrate 10. The semiconductor chip module has prevented the performance deterioration due to thermal resistance due to this heat radiation operation.

【0004】[0004]

【発明が解決しようとする課題】しかし、発生した熱を
パッケージ側に逃す方法のみでは、必ずしも十分な放熱
を行うことができず、半導体チップモジュールの性能は
序々に悪化し、故障率も高くなり、長期間の使用が不可
能になるという欠点があった。そこで本発明は、性能の
悪化が生じない良好な放熱設計ができる半導体チップモ
ジュールを提供することを目的とする。
However, sufficient heat dissipation cannot always be achieved only by the method of releasing the generated heat to the package side, the performance of the semiconductor chip module gradually deteriorates, and the failure rate increases. However, there was a drawback that it could not be used for a long time. Therefore, an object of the present invention is to provide a semiconductor chip module capable of a good heat dissipation design without deterioration of performance.

【0005】[0005]

【課題を解決するための手段】本発明に係る半導体チッ
プモジュールは、配線部が形成されている半導体基板
と、いわゆるフェイスアップですなわち回路面が上向き
になるように実装されて、この配線部上に配置された1
個または複数個の半導体チップと、この半導体チップの
上面中央部に一端部が対向したヒートシンクと、このヒ
ートシンクの他端部を外部に露出させる孔が穿設され、
半導体チップを全て内包するキャップと、半導体チップ
とヒートシンクの両方に接触するように絶縁性のサーマ
ルコンパウンド材を半導体チップのほぼ全面にわたって
充填したことを特徴としている。
A semiconductor chip module according to the present invention is mounted in a so-called face-up manner on a semiconductor substrate on which a wiring portion is formed, that is, a circuit surface faces upward, and the semiconductor chip module is mounted on the wiring portion. Placed in
A plurality of or a plurality of semiconductor chips, a heat sink whose one end faces the center of the upper surface of the semiconductor chip, and a hole for exposing the other end of the heat sink to the outside are formed.
It is characterized in that a cap enclosing all the semiconductor chips and an insulative thermal compound material are filled almost all over the semiconductor chip so as to contact both the semiconductor chip and the heat sink.

【0006】[0006]

【作用】本発明に係る半導体チップモジュールによれ
ば、フェイスアップ型の半導体チップから発生した熱は
半導体チップの上面に接触したヒートシンクの一端部か
ら他端部に伝導する。この熱伝導によって、熱はキャッ
プの外部に導かれ、キャップの外で発散される。
According to the semiconductor chip module of the present invention, the heat generated from the face-up type semiconductor chip is conducted from one end of the heat sink contacting the upper surface of the semiconductor chip to the other end. By this heat conduction, heat is guided to the outside of the cap and radiated outside the cap.

【0007】特に、絶縁性のサーマルコンパウンド材を
半導体チップのほぼ全面にわたって充填しているので、
比較的発熱量の多いI/O回路が配置されている半導体
チップ周辺部に発生する熱をサーマルコンパウンド材を
介して、ヒートシンクに伝導させることができる。
Particularly, since the insulating thermal compound material is filled almost all over the semiconductor chip,
The heat generated in the peripheral portion of the semiconductor chip where the I / O circuit, which generates a relatively large amount of heat, is arranged can be conducted to the heat sink via the thermal compound material.

【0008】[0008]

【実施例】図1は本発明の実施例に係るサーマルコンパ
ウンド材を図示省略した半導体チップモジュールの外観
を示す斜視図であり、図2は図1に示された半導体チッ
プモジュールをII II´で切断した時の断面図であ
る。また、図3は本発明の方式を説明するための図であ
り、ヒートシンク3の先端部と半導体チップ4とサーマ
ルコンパウンド材1の接触状態を示すものである。下部
基板10は、例えばアルミナ材で形成され、その側面か
らは上部基板6の上に構成された電気配線と接続した複
数のリードピン5が延びている。上部基板6は低誘電率
絶縁材料で形成され、例えば、熱抵抗3℃/W、サマー
バイヤを併用した3インチ角のポリイミド多層配線構造
を使用することができる(“銅ポリイミド多層配線基
板”、HYBRIDS、VOL.7,No.7,pp.
10−12参照)。
1 is a perspective view showing an appearance of a semiconductor chip module in which a thermal compound material according to an embodiment of the present invention is omitted, and FIG. 2 is a view showing the semiconductor chip module shown in FIG. It is sectional drawing at the time of cutting. Further, FIG. 3 is a diagram for explaining the method of the present invention, and shows the contact state of the tip of the heat sink 3, the semiconductor chip 4, and the thermal compound material 1. The lower substrate 10 is made of, for example, an alumina material, and a plurality of lead pins 5 connected to the electrical wiring formed on the upper substrate 6 extend from the side surface of the lower substrate 10. The upper substrate 6 is formed of a low dielectric constant insulating material, and for example, a 3-inch square polyimide multilayer wiring structure having a thermal resistance of 3 ° C./W and a summer bayer can be used (“copper polyimide multilayer wiring substrate”, HYBRIDS). , VOL.7, No.7, pp.
10-12).

【0009】また、下部基板10は、上部基板6よりも
大きい平板で構成され、この下部基板10の上面に上部
基板6が積み重なった状態で固定されている。上部基板
6が重なっていない下部基板10の上面にはキャップ2
の縁部が覆い被せられている。したがって、キャップ2
と下部基板10により上部基板6は内包された状態にな
っている。上部基板6の表面には電極が露出しており、
これらの電極と接続するようにフェイスアップ型半導体
チップ4およびフェイスダウン型半導体チップ4aが図
のように搭載されている。フェイスアップ型半導体チッ
プ4は、文字通り、回路面が上向きになっており、ボン
ディングワイヤ法により上部基板6の配線と電気的に接
続されている。また、フェイスダウン型半導体チップ4
aは、回路面が下側になるようにダイボンディング法等
により上部基板6の配線と電気的に接続されている。
The lower substrate 10 is composed of a flat plate larger than the upper substrate 6, and the upper substrate 6 is fixed on the upper surface of the lower substrate 10 in a stacked state. A cap 2 is provided on the upper surface of the lower substrate 10 where the upper substrate 6 does not overlap.
The edges of are covered. Therefore, the cap 2
The upper substrate 6 is contained by the lower substrate 10. The electrodes are exposed on the surface of the upper substrate 6,
A face-up type semiconductor chip 4 and a face-down type semiconductor chip 4a are mounted as shown so as to be connected to these electrodes. The face-up type semiconductor chip 4 literally has a circuit surface facing upward and is electrically connected to the wiring of the upper substrate 6 by a bonding wire method. In addition, the face-down type semiconductor chip 4
“A” is electrically connected to the wiring of the upper substrate 6 by a die bonding method or the like so that the circuit surface is on the lower side.

【0010】また、キャップ2は、例えば、厚さ1mm
のコバールで蓋状に形成されていて、フェイスアップ型
半導体チップ4およびフェイスダウン型半導体チップ4
aの搭載位置と対応した位置に、例えば直径30〜50
μmぐらいの孔2aが穿設されている。これらの穿孔2
aにヒートシンク3の一端部が挿入される。これらのヒ
ートシンク3は熱導電率の高い材料であるAlやCuW
からなり、挿入部と放熱部で構成されている。挿入部
は、上記の穿孔2aに挿入しやすい、例えば棒状となっ
ている。また、放熱部は、自動冷却されやすいように表
面積が大きくなる構造で、例えば、円盤上になってい
る。この放熱部は多段になるほど、冷却速度が速くな
る。ヒートシンク3は、このような構成になっているの
でキャップ2の内部への挿入が容易であり、キャップ2
の外部へフェイスアップ型半導体チップに発生した熱を
効率良く逃がすことができる。フェイスアップ型半導体
チップ4からヒートシンク3に熱を効率よく伝えるため
に、ヒートシンク3と半導体チップ4面の接触方法は、
面接触とするのが望ましい。したがって、半導体チップ
4の上面が平面になっている場合、ヒートシンク3の挿
入部の先端は平面になっているのが望ましい。
The cap 2 has a thickness of 1 mm, for example.
Formed in a lid shape by Kovar, and is a face-up type semiconductor chip 4 and a face-down type semiconductor chip 4
At a position corresponding to the mounting position of a, for example, a diameter of 30 to 50
A hole 2a of about μm is formed. These perforations 2
One end of the heat sink 3 is inserted in a. These heat sinks 3 are made of a material having high thermal conductivity such as Al or CuW.
It is composed of an insertion part and a heat dissipation part. The insertion portion has a rod shape, for example, which can be easily inserted into the perforation 2a. Further, the heat radiating portion has a structure having a large surface area so as to be easily automatically cooled, and is, for example, a disk. The cooling speed increases as the number of stages of the heat radiation unit increases. Since the heat sink 3 has such a structure, it can be easily inserted into the inside of the cap 2,
The heat generated in the face-up type semiconductor chip can be efficiently dissipated to the outside of the. In order to efficiently transfer heat from the face-up type semiconductor chip 4 to the heat sink 3, the contact method between the heat sink 3 and the semiconductor chip 4 surface is
Surface contact is desirable. Therefore, when the upper surface of the semiconductor chip 4 is flat, the tip of the insertion portion of the heat sink 3 is preferably flat.

【0011】また、サーマルコンパウンド材1が各フェ
イスアップ型半導体チップ4のほぼ全面にわたって充填
されている。熱放射性を良くするためである。ボンディ
ングワイヤ8とヒートシンク3の接触は極力避けたいの
で、ヒートシンク3は半導体チップ4の中央部にしか接
触できない。したがって、キャップ2外部に逃げる熱は
主にヒートシンク3の接触する中央部で発生した熱で、
周辺部のI/O回路に発生する熱は十分にヒートシンク
3に吸収されず基板側に逃げる。一般に、周辺部のI/
O回路は発熱量が多いため、この部分の熱を効果的に逃
すことは極めて重要である。そこで、本実施例のよう
に、フェイスアップ型半導体チップ4のほぼ全面にわた
って絶縁性のサーマルコンパウンド材1を充填すれば、
半導体チップ4の中央部だけでなく、周辺部I/O回路
に発生する熱も絶縁性のサーマルコンパウンド材1を介
して、ヒートシンク3に伝導させることができる。サー
マルコンパウンド材1は絶縁性なので、半導体チップ4
の全面に充填されて、ボンディングワイヤ8に接触して
も何ら性能上の問題は起こらない。絶縁性のサーマルコ
ンパウンド材1は、例えば、微粉末のダイヤモンドや立
方相窒化ほう素(CBN)を大量に含むエポキシ樹脂な
どで構成されている。
Also, the thermal compound material 1 is filled over substantially the entire surface of each face-up type semiconductor chip 4. This is to improve heat radiation. Since it is desired to avoid contact between the bonding wire 8 and the heat sink 3, the heat sink 3 can contact only the central portion of the semiconductor chip 4. Therefore, the heat escaping to the outside of the cap 2 is mainly the heat generated in the central portion where the heat sink 3 contacts,
The heat generated in the peripheral I / O circuit is not sufficiently absorbed by the heat sink 3 and escapes to the substrate side. Generally, I /
Since the O circuit has a large amount of heat generation, it is extremely important to effectively dissipate the heat in this portion. Therefore, if the insulating thermal compound material 1 is filled almost all over the face-up type semiconductor chip 4 as in this embodiment,
Heat generated not only in the central portion of the semiconductor chip 4 but also in the peripheral portion I / O circuit can be conducted to the heat sink 3 through the insulating thermal compound material 1. Since the thermal compound material 1 is insulative, the semiconductor chip 4
No problem in performance occurs even if it is filled on the entire surface of the substrate and comes into contact with the bonding wire 8. The insulating thermal compound material 1 is made of, for example, fine powder diamond or an epoxy resin containing a large amount of cubic phase boron nitride (CBN).

【0012】なお、上記ヒートシンク3の形成材料がA
lやCuWのような導体である場合には、ボンディング
ワイヤ間およびTABパッド間のショートが発生しない
ように、ヒートシンク3の先端面積を比較的小さくしな
ければならないが、AlNや立方相窒化ほう素(CB
N)等の絶縁物なら、ボンディングワイヤ8との多少の
接触はかまわないため、余裕度は高くなり、設計自由度
が高くなる。
The material for forming the heat sink 3 is A
In the case of a conductor such as 1 or CuW, the tip area of the heat sink 3 must be made relatively small so that a short circuit between bonding wires and between TAB pads does not occur, but AlN or cubic phase boron nitride is used. (CB
In the case of an insulator such as N), since some contact with the bonding wire 8 is acceptable, the margin is increased and the design flexibility is increased.

【0013】図4は、本実施例の半導体チップモジュー
ルに搭載されているサーマルコンパウンド材1を図示省
略したフェイスアップ型半導体チップ4の上面図であ
る。この半導体チップ4の周辺部にはパッド7が図の破
線上に搭載され、中央部にヒートシンク3が置かれ、さ
らに、絶縁性のサーマルコンパウンド材1がフェイスア
ップ型半導体チップ4のほぼ全面にわたって充填されて
いる。この場合、例えば、ボンディングワイアに25μ
mΦの金線を使用するとパッドサイズt1 は80μm程
度にできるので、半導体チップ端にだけパッドを並べ、
パッド端とチップ端の距離t2 を50μmとすると片側
130μmすなわち両側260μmだけの狭い場所を除
いてヒートシンク3の接触が可能となる。この構成で
は、熱抵抗を10℃/Wから3℃/W程度まで低減させ
ることができる。なお、このフェイスアップ型半導体で
は、パッド7以外はSiNやSiONからなるパッシベ
ーション膜で保護されているので回路面にヒートシンク
3が接触しても性能上の問題は起こらない。本実施例に
係るマルチチップモジュールは、例えば、半導体チップ
4が搭載され、下部基板10に固定された上部基板6の
上面をキャップ2で内包する工程、ヒートシンク3の一
端をキャップ2の穿孔2aに挿入し、その先端を半導体
チップ4の上面に接触させてサーマルコンパウンド材1
を充填する工程、ヒートシンク3と半導体チップ4が接
触した状態で、例えば、キャップの穿孔2aとヒートシ
ンク3の隙間に半田を埋め込めることにより、ヒートシ
ンク3をキャップ2に固定する工程を経てパッケージ化
される。
FIG. 4 is a top view of a face-up type semiconductor chip 4 in which the thermal compound material 1 mounted in the semiconductor chip module of this embodiment is omitted. Pads 7 are mounted on the periphery of the semiconductor chip 4 on the broken line in the figure, a heat sink 3 is placed in the center, and an insulating thermal compound material 1 is filled almost all over the face-up type semiconductor chip 4. Has been done. In this case, for example, 25μ on the bonding wire
Since the pad size t 1 can be set to about 80 μm by using the mΦ gold wire, the pads should be arranged only on the edge of the semiconductor chip.
When the distance t 2 between the pad end and the chip end is 50 μm, the heat sink 3 can be contacted except for a narrow place of 130 μm on one side, that is, 260 μm on both sides. With this configuration, the thermal resistance can be reduced from 10 ° C./W to about 3 ° C./W. In this face-up type semiconductor, since the parts other than the pad 7 are protected by the passivation film made of SiN or SiON, the performance problem does not occur even if the heat sink 3 contacts the circuit surface. In the multi-chip module according to the present embodiment, for example, the step of encapsulating the upper surface of the upper substrate 6 fixed to the lower substrate 10 with the cap 2 on which the semiconductor chip 4 is mounted, and one end of the heat sink 3 in the hole 2 a of the cap 2. The thermal compound material 1 is inserted by inserting the tip into contact with the upper surface of the semiconductor chip 4.
In a state where the heat sink 3 and the semiconductor chip 4 are in contact with each other, the heat sink 3 is fixed to the cap 2 by, for example, embedding solder in a gap between the perforation 2a of the cap and the heat sink 3, and then packaged. It

【0014】また、本実施例では、すべてのフェイスア
ップ型半導体チップ4にヒートシンク3および絶縁性の
サーマルコンパウンド材1を装着しているが、発熱量が
大きい半導体チップに選択的に装着することができる。
このように、ヒートシンク3は1個の半導体チップに対
して1個装着されるので、基板面からの高さが異なる複
数の半導体チップに対しても、確実にヒートシンクを装
着することができる。
Further, in this embodiment, the heat sink 3 and the insulating thermal compound material 1 are mounted on all face-up type semiconductor chips 4, but it may be selectively mounted on the semiconductor chips which generate a large amount of heat. it can.
As described above, one heat sink 3 is attached to one semiconductor chip, so that the heat sink can be surely attached to a plurality of semiconductor chips having different heights from the substrate surface.

【0015】[0015]

【発明の効果】以上、詳細に説明した通り、本発明の構
成によればフェイスアップで実装された半導体チップに
絶縁性のサーマルコンパウンド材をヒートシンクと半導
体チップの両方に接触するように半導体チップほぼ全面
にわたって充填している。このため、半導体チップの中
央部のみならず周辺部に発生した熱も効率良く、キャッ
プ外部に逃すことができる。したがって、良好な放熱設
計が可能で高速設計に支障がなく、熱抵抗の低減を図る
ことができる。しかも、ヒートシンクは選択的に1個の
半導体チップに対してそれぞれ装着することが可能なの
で、フェイスアップ実装方式の半導体チップおよびフェ
イスダウン実装方式の半導体チップが混在するマルチチ
ップモジュールでもフェイスアップ実装チップの熱抵抗
の低減が可能となる。
As described in detail above, according to the structure of the present invention, a semiconductor chip mounted face-up is provided with an insulative thermal compound material so that the semiconductor chip is almost in contact with both the heat sink and the semiconductor chip. The entire surface is filled. Therefore, heat generated not only in the central portion of the semiconductor chip but also in the peripheral portion can be efficiently dissipated to the outside of the cap. Therefore, good heat dissipation design is possible, there is no hindrance to high-speed design, and thermal resistance can be reduced. Moreover, since the heat sink can be selectively attached to one semiconductor chip respectively, even in a multi-chip module in which face-up mounting type semiconductor chips and face-down mounting type semiconductor chips are mixed, The thermal resistance can be reduced.

【0016】[0016]

【図面の簡単な説明】[Brief description of drawings]

【図1】本実施例の半導体チップモジュールの斜視図。FIG. 1 is a perspective view of a semiconductor chip module of this embodiment.

【図2】本実施例の半導体チップモジュールの断面図。FIG. 2 is a cross-sectional view of the semiconductor chip module of this embodiment.

【図3】本発明の方式を説明するための図。FIG. 3 is a diagram for explaining the method of the present invention.

【図4】本実施例の半導体チップの上面図。FIG. 4 is a top view of the semiconductor chip of this embodiment.

【図5】従来の方式を説明するための図。FIG. 5 is a diagram for explaining a conventional method.

【符号の説明】[Explanation of symbols]

1…絶縁性のサーマルコンパウンド材 2…キャップ 2a…キャップの穿孔 3…ヒートシンク 4…フェイスアップ型半導体チップ 4a…フェイスダウン型半導体チップ 5…リードピン 6…上部基板 7…パッド 8…ボンディングワイヤ 10…下部基板 1 ... Insulating thermal compound material 2 ... Cap 2a ... Perforation of cap 3 ... Heat sink 4 ... Face-up type semiconductor chip 4a ... Face-down type semiconductor chip 5 ... Lead pin 6 ... Upper substrate 7 ... Pad 8 ... Bonding wire 10 ... Bottom substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 配線部が形成された半導体基板と、 回路面が上向きになるように前記配線部上に配置された
1個または複数個の半導体チップと、 前記半導体チップの上面中央部に一端部が対向したヒー
トシンクと、 前記ヒートシンクの他端部を外部に露出させる孔が穿設
され、前記半導体チップを全て内包するキャップと、 前記ヒートシンクの一端部と前記半導体チップ表面の両
方に接触するように、前記半導体チップ上のほぼ全面に
わたって充填されている絶縁性のサーマルコンパウンド
材を備えて構成される半導体チップモジュール。
1. A semiconductor substrate on which a wiring portion is formed, one or a plurality of semiconductor chips arranged on the wiring portion so that a circuit surface faces upward, and one end at a central portion of an upper surface of the semiconductor chip. Portions facing each other, a hole that exposes the other end of the heat sink to the outside, and a cap that encloses all the semiconductor chips, and one end of the heat sink and the surface of the semiconductor chip are in contact with each other. In addition, a semiconductor chip module including an insulating thermal compound material that is filled over substantially the entire surface of the semiconductor chip.
JP3199558A 1991-08-08 1991-08-08 Semiconductor chip module Pending JPH0547967A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP3199558A JPH0547967A (en) 1991-08-08 1991-08-08 Semiconductor chip module
AU20775/92A AU657774B2 (en) 1991-08-08 1992-08-04 Semiconductor chip module and method for manufacturing the same
CA002075593A CA2075593A1 (en) 1991-08-08 1992-08-07 Semiconductor chip module and method for manufacturing the same
EP19920113478 EP0528291A3 (en) 1991-08-08 1992-08-07 Semiconductor chip module and method for manufacturing the same
US08/232,346 US5525835A (en) 1991-08-08 1994-04-22 Semiconductor chip module having an electrically insulative thermally conductive thermal dissipator directly in contact with the semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3199558A JPH0547967A (en) 1991-08-08 1991-08-08 Semiconductor chip module

Publications (1)

Publication Number Publication Date
JPH0547967A true JPH0547967A (en) 1993-02-26

Family

ID=16409825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3199558A Pending JPH0547967A (en) 1991-08-08 1991-08-08 Semiconductor chip module

Country Status (1)

Country Link
JP (1) JPH0547967A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5705851A (en) * 1995-06-28 1998-01-06 National Semiconductor Corporation Thermal ball lead integrated package
US6272034B1 (en) 1998-01-29 2001-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5705851A (en) * 1995-06-28 1998-01-06 National Semiconductor Corporation Thermal ball lead integrated package
US6272034B1 (en) 1998-01-29 2001-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device

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