JPH0521349B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In an image sensor using a charge transfer device with a MIS (Metal Insulator Semiconductor) structure, electrodes on a plurality of charge storage regions are connected in parallel and connected to potential displacement detection/control means. , with its output,
Automatic gain control is performed by controlling a transmission gate for transferring charge from each charge storage region to a shift register section consisting of a CCD.

[Industrial application field]

The present invention relates to an image sensor using a charge transfer device, and particularly to an image sensor having an automatic gain control (AGC) function that senses the optical state of the device in real time and determines the charge accumulation time based on this. Regarding improvements.

The present invention can be used in fields where the input optical signal has a large dynamic range, such as cameras, etc.
It is thought that it will demonstrate its great power.

[Conventional technology]

FIG. 5 schematically shows an image sensor using a charge-coupled device. In the figure, a large number of pixel diodes D _i are arranged in a plurality of columns on a semiconductor substrate 1, and a first transfer gate common to each column of pixel diodes D _i is arranged between each pixel diode column. T _G1 and horizontal shift registers (charge-coupled devices) HR ₁ , HR ₂ , HR ₃ , HR ₄ , etc. are arranged,
A second transfer gate T _G2 common to each horizontal shift register HR ₁ , HR ₂ , HR ₃ , HR _4, etc. and a vertical shift register VR are arranged at one end of the horizontal shift register, and a vertical shift register VR is disposed at one end of the horizontal shift register. shift register
It has a structure in which an amplifier A is connected to one end of the VR. Note that b is a barrier, and m ₁ and m ₂ are arrows indicating the charge transfer direction.

However, in the image sensor using the charge-coupled device shown in Fig. 5, the charges generated and accumulated in the pixel diode D _i by the incidence of light are simply sent to the amplifier sequentially by each shift register and output as an electrical signal. It only has the functions to be used.

Therefore, it functions well in applications where the intensity of light to be handled is limited within a limited range, such as facsimile equipment, but when the dynamic range of the optical signal is large, such as when used in cameras, it depends on the illuminance of the subject. , the amount of light may become excessive. In this case, a charge overflow condition will occur. On the other hand, if the amount of light is insufficient, there is a problem that the sensor cannot function satisfactorily as an optical sensor, such as a decrease in sensitivity due to insufficient charge.

Therefore, the patent application filed in 1983, which is an earlier invention according to the present invention,
In No.-111221, we proposed a charge transfer device equipped with an automatic gain control (AGC) function that senses the optical state of the device in real time and determines the charge storage time accordingly.

This is shown in FIG. 6, which is a schematic plan view. In the figure, 1 is a p-type silicon substrate, 2
3 is a barrier gate ( _GB ), 4 is a storage gate ( _GST ), 5 is a transfer gate ( _Gr ), and 6 is a photodiode (PD) that generates an electron-hole pair, that is, a charge upon the incidence of an optical signal. Grier gate (G _c ), 7 is drain (d), and 8 is horizontal shift register (HR). Reference numeral 10 denotes automatic gain control means equipped with an amplifier, and the charge accumulation time is controlled by the output thereof.

In this structure, a predetermined positive potential is applied to each of the barrier gate 3, the storage gate 4, and the transfer gate 5, and a potential profile is formed on the surface of the substrate 1.

First, the clear gate 6 is opened to completely release the charge stored in the potential well under the storage gate 4 to the drain 7, and then the clear gate 6 is closed at a predetermined timing, and at the same time, the photodiode 2 is Charges flowing in through the barrier gate 3 begin to accumulate in the potential well of the accumulation gate 4, and the accumulation continues until a predetermined timing when the transfer gate 5 is opened. The charge is transferred to the horizontal shift register 8, and sequentially sent to a signal output amplifier (not shown) via the horizontal shift register 8 and a vertical shift register (not shown), and sequentially output as an electric signal via the amplifier.

In the above configuration, the charge generated in the photodiode by the incidence of an optical signal flows into the potential well formed in the semiconductor substrate below the storage gate 4 and is accumulated once, so that the charge is accumulated in the well. The intensity of the incident light can be determined by detecting the speed of the incident light.

In the charge transfer device, the storage gate 4
An automatic gain control means 10 equipped with an amplifier or the like is connected to detect the slope, that is, the rate of decrease in the potential of the storage gate 4, and a signal corresponding to the rate of decrease in the potential is sent to the timing system to determine the charge accumulation time. When the rate of potential decrease is large, that is, when the incident light is strong, the length is adjusted short, and when the rate of potential decrease is small, that is, when the incident light is weak, the length is adjusted.

In this way, it is possible to prevent charge from overflowing from the potential well, and to compensate for the lack of charge.
Improved light receiving accuracy and light receiving sensitivity.

In FIG. 6, normally the storage gate 4
The transfer gate 5 and the clear gate 6, which are arranged side by side with their ends overlapping, are arranged apart from the storage gate 4, and a power supply (n
For example, a shield gate 11 of monolithic construction is provided which is connected directly to V _CC (in the case of the channel). (Reference... also connected to the power supply (for example -V _DD ) in the case of p channel) This shield gate 11 electrically isolates the storage gate 4 from the transfer gate 5 and clear gate 6. Therefore, conventional transfer gate 1
The rising and falling phenomenon of the potential of the storage gate 4, which occurred when the voltage of the 1 or clear gate 16 rose and fell, is completely eliminated. In other words, in the case of a structure in which the storage gate, transfer gate, and clear gate are arranged in contact with each other, the coupling capacitance C _N parasitic in the overlap part when the control signal falls
This prevents the potential of the storage gate before charge storage from decreasing, and reduces the storage gate by reducing the amount of stored charge or by supplying a signal with a rate of change in potential in a high level region with good linearity of the amplifier. It is possible to prevent the detection sensitivity of charge displacement from decreasing.

[Problem that the invention seeks to solve]

However, in the charge transfer device shown in FIG. 6, it is possible to prevent the charge from overflowing from the potential well for each pixel and compensate for the lack of charge, thereby improving the light reception accuracy and light reception sensitivity. ,
Essentially, it is intended to function as a level display element. Therefore, for image sensors with photometric functions such as cameras (requiring tens or hundreds of pixels), the optimum exposure amount must be determined by means other than this sensor, and the optical device is complicated. As a result, conventional CCD sensors did not perform adequately as image sensors.

[Means for solving problems]

In the present invention, a plurality of charge storage gates having an MIS structure are connected in parallel, and connected to automatic gain control means including potential change detection means, and further, the output thereof is connected to a transfer gate.

The structure of the present invention is as follows.

That is, the present invention includes a plurality of light receiving elements 12 and an MIS provided corresponding to the light receiving elements 12 and gradually accumulating charges generated in the corresponding light receiving elements 12.
The structure has a charge storage region (semiconductor region under GST14 in FIG. 2), and the charge storage gates (GST14) existing on the charge storage region are connected in parallel to each other so that each charge storage gate (GST14) ) are controlled by a plurality of blocks (BL1, BL2, BL3, BL4, Fig. 7) that output the potential of the charge storage region (φ _TG ), and the charge in the charge storage region is transferred to a plurality of stages of charge transfer elements ( Transfer gate (GT) for transferring to CCD register 18)
15), and a precharge circuit (V _CC , Q ₁₁ , Q ₁₂ , Q ₁₃ , Q ₁₄ , R; FIG. 7), and the charge storage gate (GST14) potential of each of the plurality of blocks is provided to generate the control signal _φTG .
The image sensor (FIG. 7) is configured to output V _GST .

[Operation] It is known that when a charge is injected into a capacitor of an MIS structure in a floating state, the potential of the MIS electrode changes in proportion to the injected charge.

The present invention utilizes this phenomenon, and MIS
By connecting a plurality of charge storage gates in the structure in parallel and detecting changes in their average potentials, it is possible to detect the average value of the charges from the light receiving section in real time. That is, it is possible to detect the charge on the storage electrode without once extracting it to an output diode or the like.

Then, when the average value of the charge from the light receiving section detected above (the same applies to the partial average value of all pixels divided into several blocks) reaches a predetermined value, the transfer gate is opened and the charge is sent to the CCD register section. Read out to the output diode section. In addition, the exposure amount can be calculated from the transfer gate opening time and the signal magnitude (the predetermined value known in advance), and can be used to determine the optimal exposure amount for a camera or the like.

〔Example〕

FIG. 1 is a circuit diagram showing the main parts of an embodiment of the present invention, in which 12 is a photodiode (PD) of a light receiving section;
13 is the barrier gate (GB), 14 is the storage gate (GST), 15 is the transfer gate (GT), and 16 is the first
of Greer Gate (GC1), 17 Clear Gates (GC1),
Gate (GS2), 18 is a CCD charge transfer unit (CCD register), and 19 and 20 are overflow drains (diffusion regions) corresponding to first and second clear gates 16 and 17, respectively. In the figure, 18A is the electrode of the CCD, and 18B is the electrode transfer direction.

The barrier gate (GB) 13 is connected to a line _L1 at a predetermined DC level, and the first and second clear gates 16 and 17 are connected to lines _L4 and _L5 controlled to a predetermined potential. , overflow drains 19, 20 are commonly connected to line _L3 .
Further, φ ₁ and φ ₂ are transfer clocks and have a complementary relationship.

The most distinctive configuration here is the storage gate (GST)
14 and transfer gate 15. The storage gate (GST) 14 of each pixel is commonly connected to line _L2 ,
Line _L2 is connected to an automatic gain control means 30 (which may be within the IC or outside the IC), the output of which is connected to a transfer gate (GT) _L6 .

The automatic gain control means includes a potential comparator 21 and a timing generation circuit 22. Note that _Q1 is a reset transistor, and _Q2 is an amplification transistor.

The operation begins by inputting a reset pulse to the gate of reset transistor _Q1 , and then
Turn on Q ₁ and set L ₂ and the storage gate (GST) 14 to a predetermined high potential (V _cc ). Next, when the reset input goes low, _Q1 is turned off, causing line _L2 and each of the storage gates (GST) 14 connected thereto to be in a floating state. In the photodiode (PD) 12 of each pixel, charges generated according to the intensity of incident light are accumulated under the storage gate (GST) 14 via the barrier gate 13. As charge accumulates, the potential of the storage gate in the floating state tends to decrease, but since each storage gate is connected in parallel to line _L2 , the accumulated charge under each storage gate 14 decreases. The potential of each storage gate 14 and the line _L2 connected thereto decreases in accordance with the average value.

Then, this decrease in the potential of line _L2 is input to the potential comparator circuit 21 via transistor _Q2 ,
By comparing with the reference voltage V _ref , the potential of line L ₂ is reduced to a predetermined potential, so that the average value of the charges under each (all) storage electrodes is reduced to a predetermined value (CCD
(a range in which charge transfer is normally performed), the output of the potential comparator circuit 21 becomes high level,
The timing generation circuit (TG) 22 detects this rising edge and generates a transfer pulse, which is applied to the transfer gate (GT) 15 via the line _L6 . As a result, the transfer gate 15 opens and the charges under each storage electrode 14 are sent to the CCD transfer section (CCD register 18).

Figure 2 shows the longitudinal cross-sectional configuration of Figure 1.
The potential of each part is shown below. The symbols and numbers of each part are the same as in Figure 1. In this configuration, a predetermined positive potential is applied to the barrier gate 13 and the storage gate 14, and a potential profile as shown by the thick line in the figure is formed on the surface of the substrate SUB.

In this state, the storage gate 14 is put into a floating state, and at the same time, charges flowing from the photodiode (PD) 12 through the barrier gate 13 begin to be stored in the potential well below the storage gate 14, and the transfer gate 15 The charge is accumulated until a predetermined timing when the transfer gate 15 is opened, and the accumulated charge is transferred to the CCD register 1 at the time when the transfer gate 15 is opened (the potential decreases as shown by the broken line in the figure).
Transferred to 8.

In the above, since each storage gate 14 is connected in parallel as described above, the potential of the storage gate 14 decreases according to the average value of the amount of charge accumulated in all the storage gates connected in parallel. . Then, as described above, when the average value of charge accumulation reaches a predetermined value, a transfer pulse is applied to the transfer gate 15, and the accumulated charges are transferred.

FIG. 3 shows a timing waveform diagram of the operation. When the reset pulse R is applied, the transistor _Q1 becomes conductive, and the potential V _GST of the storage gate 14 is precharged to a high potential. When the reset pulse is cut off, the storage gate 14 is precharged to a high potential. 14 is in a high potential floating state.

As charges are accumulated under the accumulation gate 14, its potential decreases; however, in this embodiment, since the accumulation gates 14 are connected in parallel for all pixels as described above, the average value of the accumulated charges for all pixels When it reaches a predetermined value, the automatic gain control means 30 is activated, a transfer pulse _φTG is applied to the transfer gate (TG), the transfer gate 18 is opened, and the CCD The charge stored in the register is sent out.

In the above operation, when the amount of light incident on the screen is large, V _GST reaches the predetermined value quickly, so the transfer gate opens in a short cycle (t ₁ ), and when the amount of light is small, the transfer gate opens in a long cycle (t ₂ ). The gate will open.

In this way, the CCD image sensor of this example is
The frequency at which the transfer gate opens automatically changes depending on the average amount of light incident on the screen, ensuring that a predetermined amount of charge is always maintained.
The charge is sent to the CCD register to prevent charge overflow.

On the other hand, the exposure amount can be calculated based on the period of the transfer pulse _φTG , and the shutter time of these cameras can be determined.

Next, FIG. 4 is a general plan view of the image sensor of the embodiment, and the same parts as in FIG. 1 are designated by the same numbers. In the figure, 31 is an output gate of the CCD register, and 32 is an output circuit. The shaded area represents the diffusion area, and the white frame (13, 14, 15, 16, 17,
18A, 31) is an electrode of MIS structure. In addition,
In the circuit shown in Figure 4, if AGC is not required,
Just give a fixed potential to _VST connected to line _L2 .

The above was an example of connecting all pixels in parallel and detecting the total average of charges from the CCD light receiving blowout in real time.
Divide into several blocks such as 1, BL2, BL3, BL4, etc., take the average value (partial average value) of each block, and use the average value of one of these blocks,
It is also possible to perform arithmetic processing on the average value of two or more blocks and apply AGC. In FIG. 7, 14 (GST) corresponds to the storage gate 14 shown in FIG. 1, and is connected in parallel for each block, with line L ₂₁ for each block corresponding to line L ₂ in FIG. ~ _L24 to the circuit of transistors _Q11 ~ _Q14 , _Q21 ~ _Q24 , which are provided for each block and correspond to the transistors _Q1 , _Q2 in FIG.
Automatic gain control voltages V _AGC1 to _{V AGC4} are connected to the automatic gain control means.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the average value of charges from the CCD light receiving section (for all pixels or partial pixels) can be detected in real time, and the average value (or partial average value) of accumulated charges can be detected in real time. When the value) reaches a predetermined value, the transfer gate is opened and the charge is read out, thereby preventing the charge from overflowing. Further, the exposure amount can be calculated based on the period of the transfer pulse, and this can be used to determine the shutter time of the camera.

Furthermore, according to the present invention, the storage gate can be divided into several blocks, and the storage time can be determined by focusing on the block with the largest amount of charge among each block, so that the storage time can be controlled by the potential of this block. This has the advantage that reading accuracy is improved compared to the case where each block is electrically connected in common.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of main parts of an embodiment of the present invention, FIG. 2 is an operational explanatory diagram using a longitudinal cross-sectional view of the embodiment of the present invention,
Fig. 3 is an operational waveform diagram of the embodiment, Fig. 4 is an overall configuration diagram of the embodiment, Fig. 5 is a schematic diagram of a charge-coupled device used in a conventional image sensor, and Fig. 6 shows an automatic gain control function. FIG. 7 is a plan view of a charge transfer device according to an embodiment of the present invention, and is a configuration diagram in which pixels are divided into blocks. Main code, 12...Photodiode, 13...
...Barrier gate (electrode), 14...Storage gate (electrode), 15...Transfer gate (electrode), 18...
CCD register (charge transfer unit), 30... automatic gain control means.

Claims (1)

[Scope of Claims] 1. A plurality of light-receiving elements, and a charge accumulation region having an MIS structure provided corresponding to each light-receiving element and gradually accumulating charges generated in the corresponding light-receiving element, the charge accumulation region A plurality of blocks that connect charge storage gates located above in parallel to each other and output the potential of each charge storage gate; and a plurality of blocks that output the potential of each charge storage gate; a transfer gate for transferring the charge to the device; and a precharge circuit that precharges each charge storage gate to a predetermined potential and puts the charge storage gate into a floating state, and the plurality of blocks for generating the control signal. An image sensor characterized in that the image sensor is configured so that each charge storage gate potential is output.