JPH05211284A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate power source noise based on an inductance component of a lead of a package and to obtain accurate analog characteristics by providing a capacitor under an interconnection of an interconnection region. CONSTITUTION:A silicon oxide film is formed on an interconnection region 2 on a semiconductor substrate 3 made of silicon, etc., and a lower electrode 5 of a capacitor is formed thereon by patterning a polycrystalline silicon layer. Then, after a dielectric film 6 such as a silicon oxide film, etc., is formed, a polycrystalline silicon layer is formed thereon, and patterned to form an upper electrode 7. Thereafter, after a first interlayer insulating film 8 made of PSG, etc., is formed, a first aluminum interconnection 9 is formed. In this case, the electrode 5 is connected to a first aluminum interconnection 9A to be connected to a ground potential via a contact hole 10, and the electrode 7 is connected to a first aluminum interconnection 9B to be connected to a power source potential via a contact hole 10. An upper layer second aluminum interconnection 11 is connected to the interconnection 9 via a through hole 13 opened at a second interlayer insulating film 12, and covered with a cover film 14 such as a nitride film, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having an analog / digital mixed circuit.

[0002]

2. Description of the Related Art In recent years, in an analog / digital mixed integrated circuit, the noise generated in the digital section becomes large due to high-speed operation of the digital section, and the characteristics of the analog circuit are often deteriorated. Especially, since the precision of analog circuits is increasing, the influence of noise is increasing. The inductance component of the lead of the package in which the semiconductor integrated circuit is mounted can be considered as a cause of this noise generation.

Usually, a coupling capacitor for reducing noise between power supplies is provided on a printed circuit board on which a semiconductor integrated circuit is mounted. Therefore, the noise due to the inductance component of the wiring of the printed circuit board is eliminated, but the noise due to the inductance component of the lead of the package mounting the semiconductor chip is not eliminated.

In order to eliminate this noise, it is necessary to insert a capacitor having a large capacitance value between the power supplies inside the semiconductor integrated circuit. However, the layout is largely restricted, and thus the capacitor has a sufficient capacitance value. No capacitors were placed. Therefore, noise generated from the high-speed digital section affects the high-accuracy analog section, making it difficult to improve the characteristics.

[0005]

As described above, in the coupling capacitor provided on the conventional printed circuit board,
There is a problem that it is difficult to improve the analog characteristics of the semiconductor integrated circuit because the noise due to the inductance component of the lead of the package on which the semiconductor integrated circuit is mounted cannot be eliminated.

[0006]

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit having an active region in which an element is formed and a wiring region in which a wiring is formed, which is provided on a semiconductor substrate. A capacitor is provided below the wiring.

[0007]

By providing the capacitor in the semiconductor integrated circuit, it is possible to eliminate the noise between the power supplies due to the inductance component of the lead of the package, so that it is possible to obtain a highly accurate analog characteristic.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a first embodiment of the present invention.

In recent years, semiconductor integrated circuits have been designed by automatic placement and routing using a computer as the functions become complicated and the chip area increases. Therefore, as shown in FIG. 3, the semiconductor substrate 3 forming the chip is divided into an active region 1 in which transistors and the like are arranged and a wiring region 2 in which wirings for connecting the transistors and the like are provided, The proportion of the wiring area occupies a considerably large portion.

In this embodiment, a capacitor is formed in the wiring region 2 by utilizing a two-layer structure of polycrystalline silicon as shown in FIG.

That is, a silicon oxide film 4 is formed on a wiring region 2 on a semiconductor substrate 3 made of silicon or the like, and a lower electrode 5 of a capacitor is formed on the silicon oxide film 4 by patterning a polycrystalline silicon layer. Next, a dielectric film 6 such as a silicon oxide film
Is formed by the CVD method or the like, and then a polycrystalline silicon layer is formed thereon and patterned to form the upper electrode 7. This upper electrode 7 is formed, for example, in the active region 1 by M
It is formed at the same time as the gate electrode of the OS transistor. Next, after forming the first interlayer insulating film 8 made of PSG or the like, the first aluminum wiring 9 is formed.

At this time, the lower electrode 5 is connected to the first aluminum wiring 9A connected to the ground potential and the upper electrode 7 is connected to the first aluminum wiring 9B connected to the power supply potential through the contact holes 10. Second upper layer aluminum wiring 11
Is a through hole 1 formed in the second interlayer insulating film 12.
It is connected to the lower first aluminum wiring 9 by 3 and is covered with a cover film 14 such as a nitride film.

According to the first embodiment constructed as described above, since the coupling capacitor is formed in the wiring region, when the semiconductor chip is mounted on the package,
Since noise due to the inductance component of the package lead can be eliminated, the analog characteristics of the semiconductor integrated circuit can be improved.

FIG. 2 is a sectional view showing a second embodiment of the present invention. In the second embodiment, a high-concentration diffusion layer is used as the lower electrode of the capacitor for eliminating noise between power supplies.

That is, as shown in FIG. 2, a high-concentration N-type diffusion layer 15 is formed on the semiconductor substrate 3 in the wiring region to serve as a lower electrode, and a dielectric film 6A such as a silicon oxide film is formed thereon. . Next, an upper electrode 7 made of a polycrystalline silicon layer is grown on this dielectric film 6A.

In the second embodiment thus constructed, the noise improving capacitor can be formed in the semiconductor integrated circuit even in the semiconductor integrated circuit having a structure using one layer of polycrystalline silicon. At this time, the contact hole 10 is formed in the first aluminum wiring 9 connected to the ground potential and the upper electrode 7 is connected to the ground potential by using the diffusion layer 15 as the lower electrode and the N-type semiconductor. By connecting through, it is possible to prevent the diffusion layer from being depleted, and it is possible to obtain a capacitor having no bias dependence.

[0017]

As described above, according to the present invention, by providing the capacitor for eliminating the noise between the power sources in the wiring region, the noise due to the inductance component of the lead of the package mounting the semiconductor chip can be eliminated. Therefore, there is an effect that a semiconductor integrated circuit having highly accurate analog characteristics can be realized. Moreover, since this capacitor is provided in the conventional wiring region, it does not increase the layout area.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

FIG. 2 is a sectional view of a second embodiment of the present invention.

FIG. 3 is a plan view of a semiconductor chip.

[Explanation of symbols]

 1 Active Area 2 Wiring Area 3 Semiconductor Substrate 4 Silicon Oxide Film 5 Lower Electrode 6,6A Dielectric Film 7 Upper Electrode 8 First Interlayer Insulation Film 9 First Aluminum Wiring 10 Contact Hole 11 Second Aluminum Wiring 12 Second Interlayer insulation film 13 Through hole 14 Cover film 15 Diffusion layer

Claims (2)

[Claims] 1. A semiconductor integrated circuit having an active region on a semiconductor substrate, in which an element is formed, and a wiring region in which a wiring is formed, wherein a capacitor is provided below the wiring in the wiring region. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the lower electrode forming the capacitor is an impurity diffusion layer.